ar71xx: enable TX/RX flow control on the AR7240

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_phy.c

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
index 029d8ee..3e3d383 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx built-in ethernet mac driver
  *
- *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Based on Atheros' AG7100 driver
@@ -27,20 +27,11 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
        return "?";
 }
 
-#define AR71XX_PLL_VAL_1000    0x00110000
-#define AR71XX_PLL_VAL_100     0x00001099
-#define AR71XX_PLL_VAL_10      0x00991099
-
-#define AR91XX_PLL_VAL_1000    0x1a000000
-#define AR91XX_PLL_VAL_100     0x13000a44
-#define AR91XX_PLL_VAL_10      0x00441099
-
 static void ag71xx_phy_link_update(struct ag71xx *ag)
 {
        struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
        u32 cfg2;
        u32 ifctl;
-       u32 pll;
        u32 fifo5;
        u32 mii_speed;
 
@@ -65,31 +56,32 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
        case SPEED_1000:
                mii_speed =  MII_CTRL_SPEED_1000;
                cfg2 |= MAC_CFG2_IF_1000;
-               pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
-                                      : AR71XX_PLL_VAL_1000;
                fifo5 |= FIFO_CFG5_BM;
                break;
        case SPEED_100:
                mii_speed = MII_CTRL_SPEED_100;
                cfg2 |= MAC_CFG2_IF_10_100;
                ifctl |= MAC_IFCTL_SPEED;
-               pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
-                                      : AR71XX_PLL_VAL_100;
                break;
        case SPEED_10:
                mii_speed = MII_CTRL_SPEED_10;
                cfg2 |= MAC_CFG2_IF_10_100;
-               pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
-                                      : AR71XX_PLL_VAL_10;
                break;
        default:
                BUG();
                return;
        }
 
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
-                       pdata->is_ar91xx ? 0x780fff : 0x008001ff);
-       pdata->set_pll(pll);
+       if (pdata->is_ar91xx)
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
+       else if (pdata->is_ar724x)
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
+       else
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
+
+       if (pdata->set_pll)
+               pdata->set_pll(ag->speed);
+
        ag71xx_mii_ctrl_set_speed(ag, mii_speed);
 
        ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
@@ -217,7 +209,7 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
 
                DBG("%s: PHY found at %s, uid=%08x\n",
                        dev->name,
-                       ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
+                       dev_name(&ag->mii_bus->phy_map[phy_addr]->dev),
                        ag->mii_bus->phy_map[phy_addr]->phy_id);
 
                if (phydev == NULL)
@@ -233,12 +225,12 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
                ret = -ENODEV;
                break;
        case 1:
-               ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
+               ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev),
                        &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
 
                if (IS_ERR(ag->phy_dev)) {
                        printk(KERN_ERR "%s: could not connect to PHY at %s\n",
-                               dev->name, phydev->dev.bus_id);
+                               dev->name, dev_name(&phydev->dev));
                        return PTR_ERR(ag->phy_dev);
                }
 
@@ -252,7 +244,7 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
 
                printk(KERN_DEBUG "%s: connected to PHY at %s "
                        "[uid=%08x, driver=%s]\n",
-                       dev->name, phydev->dev.bus_id,
+                       dev->name, dev_name(&phydev->dev),
                        phydev->phy_id, phydev->drv->name);
 
                ag->link = 0;
@@ -270,10 +262,59 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
        return ret;
 }
 
+static int dev_is_class(struct device *dev, void *class)
+{
+       if (dev->class != NULL && !strcmp(dev->class->name, class))
+               return 1;
+
+       return 0;
+}
+
+static struct device *dev_find_class(struct device *parent, char *class)
+{
+       if (dev_is_class(parent, class)) {
+               get_device(parent);
+               return parent;
+       }
+
+       return device_find_child(parent, class, dev_is_class);
+}
+
+static struct mii_bus *dev_to_mii_bus(struct device *dev)
+{
+       struct device *d;
+
+       d = dev_find_class(dev, "mdio_bus");
+       if (d != NULL) {
+               struct mii_bus *bus;
+
+               bus = to_mii_bus(d);
+               put_device(d);
+
+               return bus;
+       }
+
+       return NULL;
+}
+
 int ag71xx_phy_connect(struct ag71xx *ag)
 {
        struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 
+       ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev);
+       if (ag->mii_bus == NULL) {
+               printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n",
+                       ag->dev->name, dev_name(pdata->mii_bus_dev));
+               return -ENODEV;
+       }
+
+       /* Reset the mdio bus explicitly */
+       if (ag->mii_bus->reset) {
+               mutex_lock(&ag->mii_bus->mdio_lock);
+               ag->mii_bus->reset(ag->mii_bus);
+               mutex_unlock(&ag->mii_bus->mdio_lock);
+       }
+
        if (pdata->phy_mask)
                return ag71xx_phy_connect_multi(ag);