+
+static void rt288x_fe_reset(void)
+{
+ rt288x_sysc_wr(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
+}
+
+static struct resource rt288x_eth_resources[] = {
+ {
+ .start = RT2880_FE_BASE,
+ .end = RT2880_FE_BASE + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT288X_CPU_IRQ_FE,
+ .end = RT288X_CPU_IRQ_FE,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct ramips_eth_platform_data rt288x_eth_data;
+static struct platform_device rt288x_eth_device = {
+ .name = "ramips_eth",
+ .resource = rt288x_eth_resources,
+ .num_resources = ARRAY_SIZE(rt288x_eth_resources),
+ .dev = {
+ .platform_data = &rt288x_eth_data,
+ }
+};
+
+void __init rt288x_register_ethernet(void)
+{
+ struct clk *clk;
+
+ clk = clk_get(NULL, "sys");
+ if (IS_ERR(clk))
+ panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
+
+ rt288x_eth_data.sys_freq = clk_get_rate(clk);
+ rt288x_eth_data.reset_fe = rt288x_fe_reset;
+ rt288x_eth_data.min_pkt_len = 64;
+
+ if (!is_valid_ether_addr(rt288x_eth_data.mac))
+ random_ether_addr(rt288x_eth_data.mac);
+
+ platform_device_register(&rt288x_eth_device);
+}
+
+static struct resource rt288x_wdt_resources[] = {
+ {
+ .start = RT2880_TIMER_BASE,
+ .end = RT2880_TIMER_BASE + RT2880_TIMER_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device rt288x_wdt_device = {
+ .name = "ramips-wdt",
+ .id = -1,
+ .resource = rt288x_wdt_resources,
+ .num_resources = ARRAY_SIZE(rt288x_wdt_resources),
+};
+
+void __init rt288x_register_wdt(void)
+{
+ u32 t;
+
+ /* enable WDT reset output on pin SRAM_CS_N */
+ t = rt288x_sysc_rr(SYSC_REG_CLKCFG);
+ t |= CLKCFG_SRAM_CS_N_WDT;
+ rt288x_sysc_wr(t, SYSC_REG_CLKCFG);
+
+ platform_device_register(&rt288x_wdt_device);
+}