-Index: linux-2.6.23/arch/mips/kernel/genex.S
-===================================================================
---- linux-2.6.23.orig/arch/mips/kernel/genex.S 2007-10-13 11:29:46.219648163 +0200
-+++ linux-2.6.23/arch/mips/kernel/genex.S 2007-10-13 11:29:49.619841933 +0200
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
@@ -51,6 +51,10 @@
NESTED(except_vec3_generic, 0, sp)
.set push
#if R5432_CP0_INTERRUPT_WAR
mfc0 k0, CP0_INDEX
#endif
-Index: linux-2.6.23/arch/mips/mm/c-r4k.c
-===================================================================
---- linux-2.6.23.orig/arch/mips/mm/c-r4k.c 2007-10-13 11:29:46.227648623 +0200
-+++ linux-2.6.23/arch/mips/mm/c-r4k.c 2007-10-13 11:29:49.619841933 +0200
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
@@ -30,6 +30,9 @@
#include <asm/cacheflush.h> /* for run_uncached() */
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -623,6 +635,8 @@
+@@ -638,6 +650,8 @@
unsigned long addr = (unsigned long) arg;
R4600_HIT_CACHEOP_WAR_IMPL;
if (dc_lsize)
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1198,6 +1212,17 @@
+@@ -1213,6 +1227,17 @@
* silly idea of putting something else there ...
*/
switch (current_cpu_data.cputype) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1228,6 +1253,15 @@
+@@ -1243,6 +1268,15 @@
/* Default cache error handler for R4000 and R5000 family */
set_uncached_handler (0x100, &except_vec2_generic, 0x80);
probe_pcache();
setup_scache();
-@@ -1273,5 +1307,13 @@
+@@ -1288,5 +1322,13 @@
build_clear_page();
build_copy_page();
local_r4k___flush_cache_all(NULL);
coherency_setup();
+#endif
}
-Index: linux-2.6.23/arch/mips/mm/tlbex.c
-===================================================================
---- linux-2.6.23.orig/arch/mips/mm/tlbex.c 2007-10-13 11:29:46.235649074 +0200
-+++ linux-2.6.23/arch/mips/mm/tlbex.c 2007-10-13 11:35:46.076155216 +0200
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
@@ -1273,6 +1273,9 @@
/* No need for i_nop */
}
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
#else
-Index: linux-2.6.23/include/asm-mips/r4kcache.h
-===================================================================
---- linux-2.6.23.orig/include/asm-mips/r4kcache.h 2007-10-13 11:29:46.255650214 +0200
-+++ linux-2.6.23/include/asm-mips/r4kcache.h 2007-10-13 11:29:49.631842613 +0200
+--- a/include/asm-mips/r4kcache.h
++++ b/include/asm-mips/r4kcache.h
@@ -17,6 +17,20 @@
#include <asm/cpu-features.h>
#include <asm/mipsmtregs.h>
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
#endif /* _ASM_R4KCACHE_H */
-Index: linux-2.6.23/include/asm-mips/stackframe.h
-===================================================================
---- linux-2.6.23.orig/include/asm-mips/stackframe.h 2007-10-13 11:29:46.263650671 +0200
-+++ linux-2.6.23/include/asm-mips/stackframe.h 2007-10-13 11:33:38.504885346 +0200
+--- a/include/asm-mips/stackframe.h
++++ b/include/asm-mips/stackframe.h
@@ -350,6 +350,10 @@
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)