bool port4_phy;
char buf[80];
+ bool init;
+
/* all fields below are cleared on reset */
bool vlan;
u16 vlan_id[AR8X16_MAX_VLANS];
u16 lo, hi;
split_addr((u32) reg, &r1, &r2, &page);
- phy->bus->write(phy->bus, 0x18, 0, page);
+ mdiobus_write(phy->bus, 0x18, 0, page);
msleep(1); /* wait for the page switch to propagate */
- lo = phy->bus->read(phy->bus, 0x10 | r2, r1);
- hi = phy->bus->read(phy->bus, 0x10 | r2, r1 + 1);
+ lo = mdiobus_read(phy->bus, 0x10 | r2, r1);
+ hi = mdiobus_read(phy->bus, 0x10 | r2, r1 + 1);
return (hi << 16) | lo;
}
u16 lo, hi;
split_addr((u32) reg, &r1, &r2, &r3);
- phy->bus->write(phy->bus, 0x18, 0, r3);
+ mdiobus_write(phy->bus, 0x18, 0, r3);
msleep(1); /* wait for the page switch to propagate */
lo = val & 0xffff;
hi = (u16) (val >> 16);
- phy->bus->write(phy->bus, 0x10 | r2, r1 + 1, hi);
- phy->bus->write(phy->bus, 0x10 | r2, r1, lo);
+ mdiobus_write(phy->bus, 0x10 | r2, r1 + 1, hi);
+ mdiobus_write(phy->bus, 0x10 | r2, r1, lo);
}
static u32
switch (id) {
case 0x0101:
return AR8216;
+ case 0x0301:
+ return AR8236;
case 0x1000:
case 0x1001:
return AR8316;
"ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
(int)(id >> AR8216_CTRL_VERSION_S),
(int)(id & AR8216_CTRL_REVISION),
- priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 2),
- priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 3));
+ mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
+ mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
return UNKNOWN;
}
priv->write(priv, AR8216_REG_VTU, op);
}
+static void
+ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
+ u32 members, u32 pvid)
+{
+ u32 header;
+
+ if (priv->vlan && port == AR8216_PORT_CPU && priv->chip == AR8216)
+ header = AR8216_PORT_CTRL_HEADER;
+ else
+ header = 0;
+
+ ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
+ AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
+ AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
+ AR8216_PORT_CTRL_LEARN | header |
+ (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
+ (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
+
+ ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
+ AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
+ AR8216_PORT_VLAN_DEFAULT_ID,
+ (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
+ (ingress << AR8216_PORT_VLAN_MODE_S) |
+ (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
+}
+
+static void
+ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
+ u32 members, u32 pvid)
+{
+ ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
+ AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
+ AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
+ AR8216_PORT_CTRL_LEARN |
+ (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
+ (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
+
+ ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
+ AR8236_PORT_VLAN_DEFAULT_ID,
+ (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
+
+ ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
+ AR8236_PORT_VLAN2_VLAN_MODE |
+ AR8236_PORT_VLAN2_MEMBER,
+ (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
+ (members << AR8236_PORT_VLAN2_MEMBER_S));
+}
+
static int
ar8216_hw_apply(struct switch_dev *dev)
{
ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
memset(portmask, 0, sizeof(portmask));
- if (priv->vlan) {
+ if (!priv->init) {
/* calculate the port destination masks and load vlans
* into the vlan translation unit */
for (j = 0; j < AR8X16_MAX_VLANS; j++) {
pvid = i;
}
- if (priv->vlan && (priv->vlan_tagged & (1 << i))) {
- egress = AR8216_OUT_ADD_VLAN;
+ if (priv->vlan) {
+ if (priv->vlan_tagged & (1 << i))
+ egress = AR8216_OUT_ADD_VLAN;
+ else
+ egress = AR8216_OUT_STRIP_VLAN;
} else {
- egress = AR8216_OUT_STRIP_VLAN;
+ egress = AR8216_OUT_KEEP;
}
if (priv->vlan) {
ingress = AR8216_IN_SECURE;
ingress = AR8216_IN_PORT_ONLY;
}
- ar8216_rmw(priv, AR8216_REG_PORT_CTRL(i),
- AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
- AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
- AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
- AR8216_PORT_CTRL_LEARN |
- (priv->vlan && i == AR8216_PORT_CPU && (priv->chip == AR8216) ?
- AR8216_PORT_CTRL_HEADER : 0) |
- (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
- (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
-
- ar8216_rmw(priv, AR8216_REG_PORT_VLAN(i),
- AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
- AR8216_PORT_VLAN_DEFAULT_ID,
- (portmask[i] << AR8216_PORT_VLAN_DEST_PORTS_S) |
- (ingress << AR8216_PORT_VLAN_MODE_S) |
- (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
+ if (priv->chip == AR8236)
+ ar8236_setup_port(priv, i, egress, ingress, portmask[i],
+ pvid);
+ else
+ ar8216_setup_port(priv, i, egress, ingress, portmask[i],
+ pvid);
}
mutex_unlock(&priv->reg_mutex);
return 0;
}
+static int
+ar8236_hw_init(struct ar8216_priv *priv) {
+ static int initialized;
+ int i;
+ struct mii_bus *bus;
+
+ if (initialized)
+ return 0;
+
+ /* Initialize the PHYs */
+ bus = priv->phy->bus;
+ for (i = 0; i < 5; i++) {
+ bus->write(bus, i, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
+ ADVERTISE_PAUSE_ASYM);
+ bus->write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+ msleep(1000);
+
+ initialized = true;
+ return 0;
+}
+
static int
ar8316_hw_init(struct ar8216_priv *priv) {
int i;
if ((i == 4) && priv->port4_phy &&
priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
/* work around for phy4 rgmii mode */
- bus->write(bus, i, MII_ATH_DBG_ADDR, 0x12);
- bus->write(bus, i, MII_ATH_DBG_DATA, 0x480c);
+ mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12);
+ mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c);
/* rx delay */
- bus->write(bus, i, MII_ATH_DBG_ADDR, 0x0);
- bus->write(bus, i, MII_ATH_DBG_DATA, 0x824e);
+ mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0);
+ mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e);
/* tx delay */
- bus->write(bus, i, MII_ATH_DBG_ADDR, 0x5);
- bus->write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
+ mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5);
+ mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
msleep(1000);
}
/* initialize the port itself */
- bus->write(bus, i, MII_ADVERTISE,
+ mdiobus_write(bus, i, MII_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
- bus->write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- bus->write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
msleep(1000);
}
if (priv->chip == AR8216) {
ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8216_GCTRL_MTU, 1518 + 8 + 2);
- } else if (priv->chip == AR8316) {
+ } else if (priv->chip == AR8316 ||
+ priv->chip == AR8236) {
/* enable jumbo frames */
ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
/* port 5 connected to the other mac, therefore unusable */
swdev->ports = (AR8216_NUM_PORTS - 1);
}
+ } else if (priv->chip == AR8236) {
+ swdev->name = "Atheros AR8236";
+ swdev->vlans = AR8216_NUM_VLANS;
+ swdev->ports = AR8216_NUM_PORTS;
} else {
swdev->name = "Atheros AR8216";
swdev->vlans = AR8216_NUM_VLANS;
goto done;
}
+ priv->init = true;
+
if (priv->chip == AR8316) {
ret = ar8316_hw_init(priv);
if (ret) {
}
}
+ if (priv->chip == AR8236) {
+ ret = ar8236_hw_init(priv);
+ if (ret) {
+ kfree(priv);
+ goto done;
+ }
+ }
+
ret = ar8216_reset_switch(&priv->dev);
if (ret) {
kfree(priv);
dev->netdev_ops = &priv->ndo;
}
+ priv->init = false;
+
done:
return ret;
}
static struct phy_driver ar8216_driver = {
.phy_id = 0x004d0000,
- .name = "Atheros AR8216/AR8316",
+ .name = "Atheros AR8216/AR8316/AR8326",
.phy_id_mask = 0xffff0000,
.features = PHY_BASIC_FEATURES,
.probe = ar8216_probe,
projects / openwrt.git / blobdiff