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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6516 3c298f89-4303-0410-b956-a3cf2f4a3e73
[openwrt.git] / target / linux / brcm-2.6 / patches / 003-bcm4710_cache_fixes.patch
diff --git a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
index c8a08eb..d9e4dd7 100644 (file)
--- a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
+++ b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
@@ -1,34 +1,37 @@
-diff -Nur linux-2.6.17/arch/mips/kernel/genex.S linux-2.6.17-owrt/arch/mips/kernel/genex.S
---- linux-2.6.17/arch/mips/kernel/genex.S      2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/kernel/genex.S 2006-06-18 15:36:58.000000000 +0200
+diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S
+--- linux-2.6.19.ref/arch/mips/kernel/genex.S  2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/arch/mips/kernel/genex.S      2006-12-04 21:34:09.000000000 +0100
 @@ -73,6 +73,10 @@
        .set    push
        .set    mips3
        .set    noat
 @@ -73,6 +73,10 @@
        .set    push
        .set    mips3
        .set    noat
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +      nop
 +      nop
 +#endif
        mfc0    k1, CP0_CAUSE
        li      k0, 31<<2
        andi    k1, k1, 0x7c
 +      nop
 +      nop
 +#endif
        mfc0    k1, CP0_CAUSE
        li      k0, 31<<2
        andi    k1, k1, 0x7c
-diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k.c
---- linux-2.6.17/arch/mips/mm/c-r4k.c  2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/mm/c-r4k.c     2006-06-18 15:36:58.000000000 +0200
-@@ -14,6 +14,12 @@
+diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
+--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c      2006-12-04 21:34:04.000000000 +0100
++++ linux-2.6.19/arch/mips/mm/c-r4k.c  2006-12-04 21:34:09.000000000 +0100
+@@ -13,6 +13,15 @@
  #include <linux/mm.h>
  #include <linux/bitops.h>
  
  #include <linux/mm.h>
  #include <linux/bitops.h>
  
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +#include "../bcm947xx/include/typedefs.h"
 +#include "../bcm947xx/include/sbconfig.h"
 +#include "../bcm947xx/include/typedefs.h"
 +#include "../bcm947xx/include/sbconfig.h"
++#include "../bcm947xx/include/mipsinc.h"
++#undef MTC0
++#undef MFC0
++#undef cache_op
 +#include <asm/paccess.h>
 +#endif
 +#include <asm/paccess.h>
 +#endif
-+
  #include <asm/bcache.h>
  #include <asm/bootinfo.h>
  #include <asm/cache.h>
  #include <asm/bcache.h>
  #include <asm/bootinfo.h>
  #include <asm/cache.h>
-@@ -30,6 +36,9 @@
+@@ -29,6 +38,9 @@
  #include <asm/cacheflush.h> /* for run_uncached() */
  
  
  #include <asm/cacheflush.h> /* for run_uncached() */
  
  
@@ -38,53 +41,60 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
-@@ -94,7 +103,9 @@
+@@ -93,6 +105,9 @@
  {
        unsigned long  dc_lsize = cpu_dcache_line_size();
  
  {
        unsigned long  dc_lsize = cpu_dcache_line_size();
  
--      if (dc_lsize == 16)
 +      if (bcm4710)
 +              r4k_blast_dcache_page = blast_dcache_page;
 +      if (bcm4710)
 +              r4k_blast_dcache_page = blast_dcache_page;
-+      else if (dc_lsize == 16)
-               r4k_blast_dcache_page = blast_dcache16_page;
-       else if (dc_lsize == 32)
-               r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
-@@ -106,7 +117,9 @@
++      else
+       if (dc_lsize == 0)
+               r4k_blast_dcache_page = (void *)cache_noop;
+       else if (dc_lsize == 16)
+@@ -107,6 +122,9 @@
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
--      if (dc_lsize == 16)
 +      if (bcm4710)
 +              r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
 +      if (bcm4710)
 +              r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+      else if (dc_lsize == 16)
-               r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
-       else if (dc_lsize == 32)
-               r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
-@@ -118,7 +131,9 @@
++      else
+       if (dc_lsize == 0)
+               r4k_blast_dcache_page_indexed = (void *)cache_noop;
+       else if (dc_lsize == 16)
+@@ -121,6 +139,9 @@
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
--      if (dc_lsize == 16)
 +      if (bcm4710)
 +              r4k_blast_dcache = blast_dcache;
 +      if (bcm4710)
 +              r4k_blast_dcache = blast_dcache;
-+      else if (dc_lsize == 16)
-               r4k_blast_dcache = blast_dcache16;
-       else if (dc_lsize == 32)
-               r4k_blast_dcache = blast_dcache32;
-@@ -683,6 +698,8 @@
++      else
+       if (dc_lsize == 0)
+               r4k_blast_dcache = (void *)cache_noop;
+       else if (dc_lsize == 16)
+@@ -538,6 +559,9 @@
+               r4k_blast_icache();
+       else
+               protected_blast_icache_range(start, end);
++
++      if (bcm4710)
++              r4k_flush_cache_all();
+ }
+ 
+ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
+@@ -618,6 +642,8 @@
        unsigned long addr = (unsigned long) arg;
  
        R4600_HIT_CACHEOP_WAR_IMPL;
 +      BCM4710_PROTECTED_FILL_TLB(addr);
 +      BCM4710_PROTECTED_FILL_TLB(addr + 4);
        unsigned long addr = (unsigned long) arg;
  
        R4600_HIT_CACHEOP_WAR_IMPL;
 +      BCM4710_PROTECTED_FILL_TLB(addr);
 +      BCM4710_PROTECTED_FILL_TLB(addr + 4);
-       protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+       if (dc_lsize)
+               protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
        if (!cpu_icache_snoops_remote_store && scache_size)
        if (!cpu_icache_snoops_remote_store && scache_size)
-               protected_writeback_scache_line(addr & ~(sc_lsize - 1));
-@@ -1189,6 +1206,16 @@
- static inline void coherency_setup(void)
+@@ -1135,6 +1161,16 @@
+ static void __init coherency_setup(void)
  {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
  {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
-+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
++#ifdef CONFIG_BCM947XX
 +      if (BCM330X(current_cpu_data.processor_id)) {
 +              __u32 cm = read_c0_diag();
 +              /* Enable icache */
 +      if (BCM330X(current_cpu_data.processor_id)) {
 +              __u32 cm = read_c0_diag();
 +              /* Enable icache */
@@ -97,13 +107,13 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
  
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
-@@ -1227,6 +1254,15 @@
+@@ -1173,6 +1209,15 @@
  
        /* Default cache error handler for R4000 and R5000 family */
        set_uncached_handler (0x100, &except_vec2_generic, 0x80);
 +      
 +      /* Check if special workarounds are required */
  
        /* Default cache error handler for R4000 and R5000 family */
        set_uncached_handler (0x100, &except_vec2_generic, 0x80);
 +      
 +      /* Check if special workarounds are required */
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +      if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
 +              printk("Enabling BCM4710A0 cache workarounds.\n");
 +              bcm4710 = 1;
 +      if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
 +              printk("Enabling BCM4710A0 cache workarounds.\n");
 +              bcm4710 = 1;
@@ -113,25 +123,25 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
  
        probe_pcache();
        setup_scache();
  
        probe_pcache();
        setup_scache();
-diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
---- linux-2.6.17/arch/mips/mm/tlbex.c  2006-06-18 15:34:19.000000000 +0200
-+++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c     2006-06-18 15:36:58.000000000 +0200
-@@ -38,6 +38,10 @@
- 
- /* #define DEBUG_TLB */
+diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c
+--- linux-2.6.19.ref/arch/mips/mm/tlbex.c      2006-12-04 21:33:48.000000000 +0100
++++ linux-2.6.19/arch/mips/mm/tlbex.c  2006-12-04 21:34:09.000000000 +0100
+@@ -1174,6 +1174,10 @@
+ #endif
+ }
  
  
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +extern int bcm4710;
 +#endif
 +
 +extern int bcm4710;
 +#endif
 +
- static __init int __attribute__((unused)) r45k_bvahwbug(void)
+ static void __init build_r4000_tlb_refill_handler(void)
  {
  {
-       /* XXX: We should probe for the presence of this bug, but we don't. */
-@@ -1184,6 +1188,12 @@
+       u32 *p = tlb_handler;
+@@ -1188,6 +1192,12 @@
        memset(relocs, 0, sizeof(relocs));
        memset(final_handler, 0, sizeof(final_handler));
  
        memset(relocs, 0, sizeof(relocs));
        memset(final_handler, 0, sizeof(final_handler));
  
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +      if (bcm4710) {
 +              i_nop(&p);
 +      }
 +      if (bcm4710) {
 +              i_nop(&p);
 +      }
@@ -140,14 +150,14 @@ diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex
        /*
         * create the plain linear handler
         */
        /*
         * create the plain linear handler
         */
-diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm-mips/r4kcache.h
---- linux-2.6.17/include/asm-mips/r4kcache.h   2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/r4kcache.h      2006-06-18 15:56:57.000000000 +0200
+diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h
+--- linux-2.6.19.ref/include/asm-mips/r4kcache.h       2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/include/asm-mips/r4kcache.h   2006-12-04 21:34:09.000000000 +0100
 @@ -17,6 +17,18 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
  
 @@ -17,6 +17,18 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
  
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
 +
 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
 +
 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
@@ -281,7 +291,7 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
        __##pfx##flush_prologue                                         \
                                                                        \
        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
        __##pfx##flush_prologue                                         \
                                                                        \
        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
-@@ -393,24 +458,25 @@
+@@ -393,28 +458,30 @@
        __##pfx##flush_epilogue                                         \
  }
  
        __##pfx##flush_epilogue                                         \
  }
  
@@ -306,7 +316,7 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
  
  /* build blast_xxx_range, protected_blast_xxx_range */
 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
  
  /* build blast_xxx_range, protected_blast_xxx_range */
 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
  static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
                                                    unsigned long end)  \
  {                                                                     \
  static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
                                                    unsigned long end)  \
  {                                                                     \
@@ -317,7 +327,12 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
                                                                        \
        __##pfx##flush_prologue                                         \
                                                                        \
                                                                        \
        __##pfx##flush_prologue                                         \
                                                                        \
-@@ -424,13 +490,13 @@
+       while (1) {                                                     \
++              war2                                            \
+               prot##cache_op(hitop, addr);                            \
+               if (addr == aend)                                       \
+                       break;                                          \
+@@ -424,13 +491,13 @@
        __##pfx##flush_epilogue                                         \
  }
  
        __##pfx##flush_epilogue                                         \
  }
  
@@ -326,26 +341,26 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
  /* blast_inv_dcache_range */
 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
  /* blast_inv_dcache_range */
 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
  
  #endif /* _ASM_R4KCACHE_H */
  
  #endif /* _ASM_R4KCACHE_H */
-diff -Nur linux-2.6.17/include/asm-mips/stackframe.h linux-2.6.17-owrt/include/asm-mips/stackframe.h
---- linux-2.6.17/include/asm-mips/stackframe.h 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17-owrt/include/asm-mips/stackframe.h    2006-06-18 15:36:58.000000000 +0200
-@@ -361,6 +361,10 @@
+diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h
+--- linux-2.6.19.ref/include/asm-mips/stackframe.h     2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100
+@@ -334,6 +334,10 @@
                .macro  RESTORE_SP_AND_RET
                LONG_L  sp, PT_R29(sp)
                .set    mips3
                .macro  RESTORE_SP_AND_RET
                LONG_L  sp, PT_R29(sp)
                .set    mips3
-+#ifdef CONFIG_BCM4710
++#ifdef CONFIG_BCM947XX
 +              nop
 +              nop
 +#endif
 +              nop
 +              nop
 +#endif
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