-diff -urN linux-2.4.30/Makefile linux-2.4.30.dev/Makefile
---- linux-2.4.30/Makefile 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/Makefile 2005-06-14 15:36:59.000000000 +0200
-@@ -91,7 +91,7 @@
-
- CPPFLAGS := -D__KERNEL__ -I$(HPATH)
-
--CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
-+CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
- -fno-strict-aliasing -fno-common
- ifndef CONFIG_FRAME_POINTER
- CFLAGS += -fomit-frame-pointer
-diff -urN linux-2.4.30/arch/mips/Makefile linux-2.4.30.dev/arch/mips/Makefile
---- linux-2.4.30/arch/mips/Makefile 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/Makefile 2005-06-14 15:36:59.000000000 +0200
-@@ -369,6 +369,16 @@
- endif
-
- #
-+# Texas Instruments AR7
-+#
-+
-+ifdef CONFIG_AR7
-+LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
-+SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
-+LOADADDR += 0x94020000
-+endif
-+
-+#
- # DECstation family
- #
- ifdef CONFIG_DECSTATION
-diff -urN linux-2.4.30/arch/mips/ar7/Makefile linux-2.4.30.dev/arch/mips/ar7/Makefile
---- linux-2.4.30/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/Makefile 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,12 @@
-+.S.s:
-+ $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+ $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+O_TARGET := ar7.o
-+
-+obj-y := tnetd73xx_misc.o
-+obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
-+
-+include $(TOPDIR)/Rules.make
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/Makefile linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile
---- linux-2.4.30/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,13 @@
-+.S.s:
-+ $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+ $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
-+
-+O_TARGET := avalanche.o
-+
-+obj-y += avalanche_paging.o avalanche_jump.o
+diff -urN kernel-base/arch/mips/ar7/ar7/ar7_jump.S kernel-current/arch/mips/ar7/ar7/ar7_jump.S
+--- kernel-base/arch/mips/ar7/ar7/ar7_jump.S 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/ar7_jump.S 2005-07-10 06:40:39.582267168 +0200
+@@ -0,0 +1,89 @@
++/*
++ * $Id$
++ * Copyright (C) $Date$ $Author$
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ *
++ */
+
-+include $(TOPDIR)/Rules.make
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S
---- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,69 @@
+#include <linux/config.h>
+#include <linux/threads.h>
+
+END(jump_dedicated_interrupt)
+
+ .set at
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c
---- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/ar7/ar7/ar7_paging.c kernel-current/arch/mips/ar7/ar7/ar7_paging.c
+--- kernel-base/arch/mips/ar7/ar7/ar7_paging.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/ar7_paging.c 2005-07-10 07:08:33.725758672 +0200
@@ -0,0 +1,314 @@
+/*
+ * -*- linux-c -*-
+
+ return;
+}
-diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.dev/arch/mips/ar7/cmdline.c
---- linux-2.4.30/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/cmdline.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,64 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
-+ */
-+#include <linux/init.h>
-+#include <linux/string.h>
+diff -urN kernel-base/arch/mips/ar7/ar7/gpio.c kernel-current/arch/mips/ar7/ar7/gpio.c
+--- kernel-base/arch/mips/ar7/ar7/gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/gpio.c 2005-07-10 09:46:52.164776456 +0200
+@@ -0,0 +1,132 @@
++#include <linux/kernel.h>
++#include <asm/uaccess.h>
++#include <linux/spinlock.h>
++#include <linux/proc_fs.h>
++#include <linux/fs.h>
++#include <linux/timer.h>
++#include <linux/module.h>
++#include <linux/stddef.h>
+
-+#include <asm/bootinfo.h>
++#include <asm/ar7/tnetd73xx_err.h>
++#include <asm/ar7/tnetd73xx_misc.h>
++#include <asm/ar7/ledapp.h>
+
-+extern int prom_argc;
-+extern int *_prom_argv;
+
-+/*
-+ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
-+ * This macro take care of sign extension.
-+ */
-+#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
++#if defined (CONFIG_AR7RD) || defined(CONFIG_AR7WRD)
+
-+char arcs_cmdline[CL_SIZE];
++#define AR7_RESET_FILE "led_mod/ar7reset"
++#define AR7_RESET_GPIO 11
++#define RESET_POLL_TIME 1
++#define RESET_HOLD_TIME 4
++#define NO_OF_LEDS
++#define TRUE 1
++#define FALSE 0
+
-+char * __init prom_getcmdline(void)
++static struct proc_dir_entry *reset_file;
++static int res_state = 0;
++static int count;
++static struct timer_list *pTimer = NULL;
++static ssize_t proc_read_reset_fops(struct file *filp, char *buf, size_t count, loff_t * offp);
++
++struct file_operations reset_fops = {
++ read:proc_read_reset_fops
++};
++
++#endif
++
++static spinlock_t device_lock;
++led_reg_t temp[15];
++
++static void gpio_led_on(unsigned long param)
+{
-+ return &(arcs_cmdline[0]);
++ unsigned int flags;
++
++ spin_lock_irqsave(&device_lock, flags);
++ tnetd73xx_gpio_out(param, FALSE);
++ spin_unlock_irqrestore(&device_lock, flags);
+}
+
++static void gpio_led_off(unsigned long param)
++{
++ unsigned int flags = 0x00;
++
++ spin_lock_irqsave(&device_lock, flags);
++ tnetd73xx_gpio_out(param, TRUE);
++ spin_unlock_irqrestore(&device_lock, flags);
++}
+
-+void __init prom_init_cmdline(void)
++static void gpio_led_init(unsigned long param)
+{
-+ char *cp;
-+ int actr;
++ tnetd73xx_gpio_ctrl(param, GPIO_PIN, GPIO_OUTPUT_PIN);
++}
+
-+ actr = 1; /* Always ignore argv[0] */
++static void board_gpio_reset(void)
++{
++ tnetd73xx_gpio_init();
+
-+ cp = &(arcs_cmdline[0]);
-+#ifdef CONFIG_CMDLINE_BOOL
-+ strcpy(cp, CONFIG_CMDLINE);
-+ cp += strlen(CONFIG_CMDLINE);
-+ *cp++ = ' ';
-+#endif
-+ while(actr < prom_argc) {
-+ strcpy(cp, prom_argv(actr));
-+ cp += strlen(prom_argv(actr));
-+ *cp++ = ' ';
-+ actr++;
-+ }
-+ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
-+ --cp;
-+ *cp = '\0';
++ /* Initialize the link mask */
++ device_lock = SPIN_LOCK_UNLOCKED;
++ return;
+}
-diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.c
---- linux-2.4.30/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/init.c 2005-06-14 19:15:15.000000000 +0200
-@@ -0,0 +1,144 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * PROM library initialisation code.
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/string.h>
-+#include <linux/kernel.h>
+
-+#include <asm/io.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/mips-boards/generic.h>
++#if defined(CONFIG_AR7WRD)
+
-+/* Environment variable */
-+typedef struct {
-+ char *name;
-+ char *val;
-+} t_env_var;
++static ssize_t proc_read_reset_fops(struct file *filp, char *buf, size_t count, loff_t * offp)
++{
++ char *pdata = NULL;
++ char line[3];
++ int len = 0;
++ if (*offp != 0)
++ return 0;
+
-+int prom_argc;
-+int *_prom_argv, *_prom_envp;
++ pdata = buf;
++ len = sprintf(line, "%d\n", res_state);
++ res_state = 0;
++ copy_to_user(buf, line, len);
++ *offp = len;
++ return len;
++}
+
-+/* max # of Adam2 environment variables */
-+#define MAX_ENV_ENTRY 80
++static void reset_timer_func(unsigned long data)
++{
++ count = (tnetd73xx_gpio_in(AR7_RESET_GPIO) == 0) ? count + 1 : 0;
++ if (count >= RESET_HOLD_TIME / RESET_POLL_TIME)
++ res_state = 1;
++ pTimer->expires = jiffies + HZ * RESET_POLL_TIME;
++ add_timer(pTimer);
++ return;
++}
+
-+static t_env_var local_envp[MAX_ENV_ENTRY];
++static void reset_init(void)
++{
++ /* Create board reset proc file */
++ reset_file = create_proc_entry(AR7_RESET_FILE, 0777, NULL);
++ if (reset_file == NULL)
++ goto reset_file;
++ reset_file->owner = THIS_MODULE;
++ reset_file->proc_fops = &reset_fops;
++
++ /* Initialise GPIO 11 for input */
++ tnetd73xx_gpio_ctrl(AR7_RESET_GPIO, GPIO_PIN, GPIO_INPUT_PIN);
++
++ /* Create a timer which fires every seconds */
++ pTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
++ init_timer(pTimer);
++ pTimer->function = reset_timer_func;
++ pTimer->data = 0;
++ /* Start the timer */
++ reset_timer_func(0);
++ return;
+
-+int init_debug = 0;
++ reset_file:
++ remove_proc_entry(AR7_RESET_FILE, NULL);
++ return;
++}
++#endif
+
-+char *prom_getenv(char *envname)
++
++void board_gpio_init(void)
+{
-+ /*
-+ * Return a pointer to the given environment variable.
-+ * In 64-bit mode: we're using 64-bit pointers, but all pointers
-+ * in the PROM structures are only 32-bit, so we need some
-+ * workarounds, if we are running in 64-bit mode.
-+ */
-+ int i, index=0;
-+ t_env_var *env = (t_env_var *) local_envp;
++ board_gpio_reset();
++ return;
++}
+diff -urN kernel-base/arch/mips/ar7/ar7/ledmod.c kernel-current/arch/mips/ar7/ar7/ledmod.c
+--- kernel-base/arch/mips/ar7/ar7/ledmod.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/ledmod.c 2005-07-10 09:45:36.692250024 +0200
+@@ -0,0 +1,712 @@
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/proc_fs.h>
++#include <asm/uaccess.h>
++#include <linux/fs.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++#include <asm/ar7/avalanche_regs.h>
++#include <asm/ar7/ledapp.h>
++#include <linux/module.h>
++
++#define LED_ON 1
++#define LED_OFF 2
++#define LED_BLINK 3
++#define LED_FLASH 4
++
++#define LED_BLINK_UP 5
++#define LED_BLINK_DOWN 6
++
++typedef struct state_entry {
++ unsigned char mode;
++ unsigned char led;
++ void (*handler) (struct state_entry * pState);
++ unsigned long param;
++} state_entry_t;
++
++typedef struct mod_entry {
++ state_entry_t *states[MAX_STATE_ID];
++} mod_entry_t;
++
++static mod_entry_t *modArr[MAX_MOD_ID];
++static struct proc_dir_entry *led_proc_dir, *led_file;
++
++/* index of the array is the led number HARDWARE SPECIFIC*/
++typedef struct led_data {
++ led_reg_t *led;
++ int state;
++ struct timer_list *pTimer;
++ unsigned char timer_running;
++ unsigned long param;
++} led_data_t;
++
++led_data_t led_arr[MAX_LED_ID + 1];
++/*!!! The last device is actually being used for ar7 reset to factory default */
++#if 1
++/* Ron add for adsl LED blink */
++#define GPIO_ADSL_ACT (1<<6)
++#define GPIO_ADSL_DOWN (1<<8)
++#define BLINK_FAST 5*HZ/100
++#define BLINK_SLOW 15*HZ/100
++static struct timer_list my_led_timer;
++static int my_blink_count = 0;
++static int my_mode = 1;
++void led_operation(int mod, int state);
++
++static void my_led_on(unsigned long gpio, int logic)
++{
++ if (logic > 0)
++ GPIO_DATA_OUTPUT |= gpio;
++ else
++ GPIO_DATA_OUTPUT &= ~gpio;
+
-+ i = strlen(envname);
-+ while (env->name) {
-+ if(strncmp(envname, env->name, i) == 0) {
-+ return(env->val);
-+ }
-+ env++;
-+ }
++}
++static void my_led_off(unsigned long gpio, int logic)
++{
++ if (logic > 0)
++ GPIO_DATA_OUTPUT &= ~gpio;
++ else
++ GPIO_DATA_OUTPUT |= gpio;
+
-+ return NULL;
+}
+
-+static inline unsigned char str2hexnum(unsigned char c)
++static void my_led_init(unsigned long gpio, int init, int logic)
+{
-+ if (c >= '0' && c <= '9')
-+ return c - '0';
-+ if (c >= 'a' && c <= 'f')
-+ return c - 'a' + 10;
-+ return 0; /* foo */
++ GPIO_DATA_ENABLE |= gpio;
++ GPIO_DATA_DIR &= ~gpio;
++ if (init)
++ my_led_on(gpio, logic);
++ else
++ my_led_off(gpio, logic);
+}
+
-+static inline void str2eaddr(unsigned char *ea, unsigned char *str)
++static void my_led_blink_timer(unsigned long data)
+{
-+ int i;
++ unsigned long gpio = GPIO_ADSL_ACT;
++ unsigned int speed = BLINK_FAST;
++ if (my_mode == 2) {
++ gpio = GPIO_ADSL_DOWN;
++ speed = BLINK_SLOW;
++ }
++ if (my_blink_count) {
++ if (GPIO_DATA_OUTPUT & gpio) {
++ GPIO_DATA_OUTPUT &= ~gpio;
++ if (my_mode != 2)
++ my_blink_count = 0;
++ } else {
++ GPIO_DATA_OUTPUT |= gpio;
++ }
++ }
++ my_led_timer.expires = jiffies + speed;
++ add_timer(&my_led_timer);
++}
+
-+ for (i = 0; i < 6; i++) {
-+ unsigned char num;
++/* Ron add for ADSL led blink */
++#endif
++static spinlock_t config_lock;
+
-+ if((*str == '.') || (*str == ':'))
-+ str++;
-+ num = str2hexnum(*str++) << 4;
-+ num |= (str2hexnum(*str++));
-+ ea[i] = num;
++static void board_led_link_up(state_entry_t * pState);
++static void board_led_link_down(state_entry_t * pState);
++static void board_led_activity_on(state_entry_t * pState);
++static void board_led_activity_off(state_entry_t * pState);
++static void led_timer_func(unsigned long data);
++
++extern void board_gpio_init(void);
++extern void uart_led_init(void);
++
++static ssize_t proc_read_led_fops(struct file *filp, char *buf, size_t count, loff_t * offp);
++static ssize_t proc_write_led_fops(struct file *filp, const char *buffer, size_t count, loff_t * offp);
++static int config_led(unsigned long y);
++
++struct file_operations led_fops = {
++ read:proc_read_led_fops,
++ write:proc_write_led_fops,
++};
++
++static int led_atoi(char *name)
++{
++ int val = 0;
++ for (;; name++) {
++ switch (*name) {
++ case '0'...'9':
++ val = val * 10 + (*name - '0');
++ break;
++ default:
++ return val;
++ }
+ }
+}
+
-+int get_ethernet_addr(char *ethernet_addr)
++static int free_memory(void)
+{
-+ char *ethaddr_str;
-+
-+ ethaddr_str = prom_getenv("ethaddr");
-+ if (!ethaddr_str) {
-+ printk("ethaddr not set in boot prom\n");
-+ return -1;
-+ }
-+ str2eaddr(ethernet_addr, ethaddr_str);
++ int i, j;
+
-+ if (init_debug > 1) {
-+ int i;
-+ printk("get_ethernet_addr: ");
-+ for (i=0; i<5; i++)
-+ printk("%02x:", (unsigned char)*(ethernet_addr+i));
-+ printk("%02x\n", *(ethernet_addr+i));
++ for (i = 0; i < MAX_MOD_ID; i++) {
++ if (modArr[i] != NULL) {
++ for (j = 0; j < MAX_STATE_ID; j++) {
++ if (modArr[i]->states[j] != NULL)
++ kfree(modArr[i]->states[j]);
++ }
++ kfree(modArr[i]);
++ modArr[i] = NULL;
++ }
+ }
-+
+ return 0;
+}
+
-+int __init prom_init(int argc, char **argv, char **envp)
++static int led_on(state_entry_t * pState)
+{
-+ int i;
-+ t_env_var *env = (t_env_var *) envp;
-+
-+ prom_argc = argc;
-+ _prom_argv = (int *)argv;
-+ _prom_envp = (int *)envp;
-+
-+ /* Copy what we need locally so we are not dependent on
-+ * bootloader RAM. In Adam2, the environment parameters
-+ * are in flash but the table that references them is in
-+ * RAM
-+ */
-+ for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
-+ if (env->name) {
-+ local_envp[i].name = env->name;
-+ local_envp[i].val = env->val;
-+ } else {
-+ local_envp[i].name = NULL;
-+ local_envp[i].val = NULL;
-+ }
-+ }
-+
-+ set_io_port_base(0);
-+
-+ prom_printf("\nLINUX started...\n");
-+ prom_init_cmdline();
-+ prom_meminit();
++ if (led_arr[pState->led].led == NULL)
++ return -1;
++ led_arr[pState->led].led->onfunc(led_arr[pState->led].led->param);
++ return 0;
++}
+
++static int led_off(state_entry_t * pState)
++{
++ if (led_arr[pState->led].led == NULL)
++ return -1;
++ led_arr[pState->led].led->offfunc(led_arr[pState->led].led->param);
+ return 0;
+}
-diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
---- linux-2.4.30/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/irq.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,669 @@
-+/*
-+ * Nitin Dhingra, iamnd@ti.com
-+ * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Routines for generic manipulation of the interrupts found on the Texas
-+ * Instruments avalanche board
-+ *
-+ */
+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/proc_fs.h>
-+#include <asm/irq.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
-+#include <asm/ar7/avalanche_intc.h>
-+#include <asm/gdb-stub.h>
++static void board_led_link_up(state_entry_t * pState)
++{
++ led_arr[pState->led].state = LED_ON;
++ if (led_arr[pState->led].timer_running == 0)
++ led_on(pState);
++ return;
++}
+
++static void board_led_link_down(state_entry_t * pState)
++{
++ led_arr[pState->led].state = LED_OFF;
++ if (led_arr[pState->led].timer_running == 0)
++ led_off(pState);
++ return;
++}
+
-+#define shutdown_avalanche_irq disable_avalanche_irq
-+#define mask_and_ack_avalanche_irq disable_avalanche_irq
++static void add_led_timer(state_entry_t * pState)
++{
++ led_arr[pState->led].pTimer->expires =
++ jiffies + HZ * (pState->param) / 1000;
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].pTimer->data = pState;
++ add_timer(led_arr[pState->led].pTimer);
++}
+
-+static unsigned int startup_avalanche_irq(unsigned int irq);
-+static void end_avalanche_irq(unsigned int irq);
-+void enable_avalanche_irq(unsigned int irq_nr);
-+void disable_avalanche_irq(unsigned int irq_nr);
++static void board_led_activity_on(state_entry_t * pState)
++{
++ if (led_arr[pState->led].timer_running == 0) {
++ led_on(pState);
++ add_led_timer(pState);
++ led_arr[pState->led].timer_running = 1;
++ led_arr[pState->led].state = LED_BLINK_UP;
++ } else if (led_arr[pState->led].timer_running > 0xF0) {
++ led_arr[pState->led].state = LED_BLINK_UP;
++ led_arr[pState->led].pTimer->expires =
++ jiffies + HZ * (pState->param) / 1000;
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].pTimer->data = pState;
++ }
++ return;
++}
+
-+static struct hw_interrupt_type avalanche_irq_type = {
-+ "TI AVALANCHE",
-+ startup_avalanche_irq,
-+ shutdown_avalanche_irq,
-+ enable_avalanche_irq,
-+ disable_avalanche_irq,
-+ mask_and_ack_avalanche_irq,
-+ end_avalanche_irq,
-+ NULL
-+};
++static void board_led_activity_off(state_entry_t * pState)
++{
++ if (led_arr[pState->led].timer_running == 0) {
++ led_off(pState);
++ add_led_timer(pState);
++ led_arr[pState->led].timer_running = 1;
++ led_arr[pState->led].state = LED_BLINK_UP;
++ } else if (led_arr[pState->led].timer_running > 0xF0) {
++ led_arr[pState->led].state = LED_BLINK_UP;
++ led_arr[pState->led].pTimer->expires =
++ jiffies + HZ * (pState->param) / 1000;
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].pTimer->data = pState;
++ }
++ return;
++}
+
-+irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
-+{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
++static void board_led_link_flash(state_entry_t * pState)
++{
++ if (led_on(pState))
++ return;
++ if (led_arr[pState->led].timer_running == 0)
++ add_led_timer(pState);
++ else
++ led_arr[pState->led].param = pState->param;
++ led_arr[pState->led].timer_running = 0xFF;
++ led_arr[pState->led].state = LED_FLASH;
++ return;
++}
+
++static void led_timer_func(unsigned long data)
++{
++ state_entry_t *pState = NULL;
++ mod_entry_t *pMod = NULL;
++ unsigned int flags;
+
-+unsigned long spurious_count = 0;
++ spin_lock_irqsave(&config_lock, flags);
+
-+struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
-+struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
-+struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
-+struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
++ pState = (state_entry_t *) data;
+
-+extern asmlinkage void mipsIRQ(void);
++ if (led_arr[pState->led].state == LED_BLINK_DOWN) {
++ led_arr[pState->led].timer_running = 0;
++ if (pState->mode == 2)
++ led_arr[pState->led].state = LED_OFF;
++ else
++ led_arr[pState->led].state = LED_ON;
++ } else if (led_arr[pState->led].state == LED_BLINK_UP) {
++ led_arr[pState->led].pTimer->expires =
++ jiffies + HZ * (led_arr[pState->led].param) / 1000;
++ led_arr[pState->led].pTimer->data = pState;
++ add_timer(led_arr[pState->led].pTimer);
++ if (pState->mode == 2) {
++ led_off(pState);
++ led_arr[pState->led].state = LED_BLINK_DOWN;
++ } else {
++ led_on(pState);
++ led_arr[pState->led].state = LED_BLINK_DOWN;
++ }
++ led_arr[pState->led].timer_running = 1;
++ } else if (led_arr[pState->led].state == LED_FLASH) {
++ led_arr[pState->led].pTimer->expires =
++ jiffies + HZ * (led_arr[pState->led].param) / 1000;
++ led_arr[pState->led].pTimer->data = pState;
++ add_timer(led_arr[pState->led].pTimer);
++
++ if (led_arr[pState->led].timer_running == 0xFF) {
++ led_off(pState);
++ led_arr[pState->led].timer_running--;
++ } else {
++ led_on(pState);
++ led_arr[pState->led].timer_running++;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ } else if (led_arr[pState->led].state == LED_OFF) {
++ led_off(pState);
++ led_arr[pState->led].timer_running = 0;
++ } else if (led_arr[pState->led].state == LED_ON) {
++ led_on(pState);
++ led_arr[pState->led].timer_running = 0;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++}
+
++static ssize_t proc_read_led_fops(struct file *filp,
++ char *buf, size_t count, loff_t * offp)
++{
++ char *pdata = NULL;
++ int i = 0, j = 0, len = 0, totallen = 0;
++ char line[255];
+
-+/*
-+ * The avalanche/MIPS interrupt line numbers are used to represent the
-+ * interrupts within the irqaction arrays. The index notation is
-+ * is as follows:
-+ *
-+ * 0-7 MIPS CPU Exceptions (HW/SW)
-+ * 8-47 Primary Interrupts (Avalanche)
-+ * 48-79 Secondary Interrupts (Avalanche)
-+ *
-+ */
++ if (*offp != 0)
++ return 0;
+
++ pdata = buf;
++ len += sprintf(line, "LEDS Registered for use are:");
++ for (i = 0; i < MAX_LED_ID; i++)
++ if (led_arr[i].led != NULL)
++ len += sprintf(&line[len], " %d ", i);
++ line[len++] = '\n';
++
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ len = sprintf(line, "USER MODULE INFORMATION:\n");
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ for (i = 0; i < MAX_MOD_ID; i++) {
++ if (modArr[i] != NULL) {
++ len = sprintf(line, " Module ID = %d \n", i);
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++ len = 0;
++ for (j = 0; j < MAX_STATE_ID; j++) {
++ if (modArr[i]->states[j] != NULL) {
++ len = sprintf(line, " State = %d , Led = %d,", j,
++ modArr[i]->states[j]->led);
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++
++ len = 0;
++ switch (modArr[i]->states[j]->mode) {
++ case 1:
++ len = sprintf(line, " Mode = OFF\n");
++ break;
++ case 2:
++ len = sprintf(line, " Mode = BLINK_ON , On Time(ms) = %d\n",
++ (unsigned int) modArr[i]->states[j]->
++ param);
++ break;
++ case 3:
++ len = sprintf(line, " Mode = BLINK_OFF , Off Time(ms) = %d\n",
++ (unsigned int) modArr[i]->states[j]->
++ param);
++ break;
++ case 4:
++ len = sprintf(line, " Mode = ON \n");
++ break;
++ case 5:
++ len = sprintf(line, " Mode = FLASH , Time Period(ms) = %d\n",
++ (unsigned int) modArr[i]->states[j]->
++ param);
++ break;
++ default:
++ break;
++
++ }
++ copy_to_user(pdata, line, len);
++ pdata += len;
++ totallen += len;
++
++ len = 0;
++ }
++ }
++ }
++ }
++ /* Return with configuration information for LEDs */
++ *offp = totallen;
++ return totallen;
++}
+
-+static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
++static ssize_t proc_write_led_fops(struct file *filp, const char *buffer, size_t count, loff_t * offp)
+{
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL
-+};
++ char *pdata = NULL, *ptemp = NULL;
++ char line[10], temp[10];
++ int i = 0;
++ int mod = 0xFFFF, state = 0xFFFF;
++ int flag = 0;
++
++ /* Check if this write is for configuring stuff */
++ if (*(int *) (buffer) == 0xFFEEDDCC) {
++ printk("<1>proc write:Calling Configuration\n");
++ config_led((unsigned long) (buffer + sizeof(int)));
++ return count;
++ }
+
-+static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
++ if (count >= 10) {
++ printk("<1>proc write:Input too long,max length = %d\n", 10);
++ return count;
++ }
++ memset(temp, 0x00, 10);
++ memset(line, 0x00, 10);
++ copy_from_user(line, buffer, count);
++ line[count] = 0x00;
++ pdata = line;
++ ptemp = temp;
++ while (flag == 0) {
++ if (i > 10)
++ break;
++ if (((*pdata) >= '0') && ((*pdata) <= '9')) {
++ *ptemp = *pdata;
++ ptemp++;
++ } else if ((*pdata) == ',') {
++ *ptemp = 0x00;
++ flag = 1;
++ }
++ pdata++;
++ i++;
++ };
++ if (flag == 1)
++ mod = led_atoi(temp);
++ else
++ return count;
++
++ ptemp = temp;
++ *ptemp = 0x00;
++ flag = 0;
++ while (flag == 0) {
++ if (i > 10)
++ break;
++ if (((*pdata) >= '0') && ((*pdata) <= '9')) {
++ *ptemp = *pdata;
++ ptemp++;
++ } else if ((*pdata) == 0x00) {
++ *ptemp = 0x00;
++ flag = 1;
++ }
++ pdata++;
++ i++;
++ };
++ if (flag == 1)
++ state = led_atoi(temp);
++ else
++ return count;
++ if ((mod == 0xFFFF) || (state == 0xFFFF))
++ return count;
++ else
++ led_operation(mod, state);
++ return count;
++}
++
++static int config_led(unsigned long y)
+{
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL,
-+ NULL, NULL, NULL, NULL
-+};
++ config_elem_t *pcfg = NULL;
++ char *pdata = NULL;
++ int i;
++ int length = 0, number = 0;
++ unsigned int flags;
++
++ spin_lock_irqsave(&config_lock, flags);
++
++ /* ioctl to configure */
++ length = *((int *) y);
++ pdata = (char *) y + sizeof(int);
++ number = (length - sizeof(int)) / sizeof(config_elem_t);
++ pcfg = (config_elem_t *) (pdata);
++
++ /* Check if an earlier configuration exists IF yes free it up */
++ free_memory();
++
++ for (i = 0; i < number; i++) {
++ /* If no structure has been allocated for the module do so */
++ if (modArr[pcfg->name] == NULL) {
++ printk("<1>module = %d\n", pcfg->name);
++ if (pcfg->name >= MAX_MOD_ID) {
++ printk
++ ("<1>Exiting Configuration: Module ID too large %d\n",
++ pcfg->name);
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ modArr[pcfg->name] = kmalloc(sizeof(mod_entry_t), GFP_KERNEL);
++ if (modArr[pcfg->name] == NULL) {
++ printk
++ ("<1>Exiting Configuration: Error in allocating memory\n");
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ memset(modArr[pcfg->name], 0x00, sizeof(mod_entry_t));
++ }
+
-+/*
-+ This remaps interrupts to exist on other channels than the default
-+ channels. essentially we can use the line # as the index for this
-+ array
-+ */
++ /* if no structure is allocated previously for this state
++ allocate a structure, if it's already there fill it up */
++ if (modArr[pcfg->name]->states[pcfg->state] == NULL) {
++ printk("<1>STATE = %d\n", pcfg->state);
++ if (pcfg->state >= MAX_STATE_ID) {
++ printk("<1>Exiting Configuration: State ID too large\n");
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ modArr[pcfg->name]->states[pcfg->state] =
++ kmalloc(sizeof(state_entry_t), GFP_KERNEL);
++ if (modArr[pcfg->name]->states[pcfg->state] == NULL) {
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ memset(modArr[pcfg->name]->states[pcfg->state], 0x00,
++ sizeof(state_entry_t));
++ }
++ /* Fill up the fields of the state */
++ if (pcfg->led >= MAX_LED_ID) {
++ printk("<1>led = %d\n", pcfg->led);
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ modArr[pcfg->name]->states[pcfg->state]->led = pcfg->led;
++ modArr[pcfg->name]->states[pcfg->state]->mode = pcfg->mode;
++ modArr[pcfg->name]->states[pcfg->state]->param = pcfg->param;
++ switch (pcfg->mode) {
++ case 1:
++ modArr[pcfg->name]->states[pcfg->state]->handler =
++ board_led_link_down;
++ break;
++ case 2:
++ case 3:
++ case 5:
++ if (pcfg->mode == 2)
++ modArr[pcfg->name]->states[pcfg->state]->handler =
++ board_led_activity_on;
++ else if (pcfg->mode == 3)
++ modArr[pcfg->name]->states[pcfg->state]->handler =
++ board_led_activity_off;
++ else
++ modArr[pcfg->name]->states[pcfg->state]->handler =
++ board_led_link_flash;
++ break;
++ case 4:
++ modArr[pcfg->name]->states[pcfg->state]->handler =
++ board_led_link_up;
++ break;
++ default:
++ printk("<1>Exiting Configuration: Unknown LED Mode\n");
++ free_memory();
++ spin_unlock_irqrestore(&config_lock, flags);
++ return -1;
++ }
++ pcfg++;
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
++ return 0;
++}
+
+
-+static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
-+unsigned long uni_secondary_interrupt = 0;
++int led_init(void)
++{
+
-+static struct irqaction r4ktimer_action = {
-+ NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
-+};
++ /* Clear our memory */
++ memset(modArr, 0x00, sizeof(mod_entry_t *) * MAX_MOD_ID);
++ memset(led_arr, 0x00, sizeof(led_data_t *) * MAX_LED_ID);
++
++ /* Create spin lock for config data structure */
++ config_lock = SPIN_LOCK_UNLOCKED;
++
++ /* Create directory */
++ led_proc_dir = proc_mkdir("led_mod", NULL);
++ if (led_proc_dir == NULL)
++ goto out;
++
++ /* Create adsl file */
++ led_file = create_proc_entry("led", 0777, led_proc_dir);
++ if (led_file == NULL)
++ goto led_file;
++ led_file->owner = THIS_MODULE;
++ led_file->proc_fops = &led_fops;
++
++ memset(modArr, 0x00, sizeof(mod_entry_t *) * MAX_MOD_ID);
++ /* Reset the GPIO pins */
++ board_gpio_init();
++
++ /* Ron add for ADSL LED blink */
++ my_mode = 1;
++ my_led_init(GPIO_ADSL_ACT, 0, -1);
++ my_led_init(GPIO_ADSL_DOWN, 0, -1);
++ init_timer(&my_led_timer);
++ my_led_timer.function = my_led_blink_timer;
++ my_led_timer.data = 0;
++ my_led_timer.expires = jiffies + BLINK_SLOW;
++ add_timer(&my_led_timer);
++ /* Ron add for ADSL LED blink */
++ return 0;
+
-+static struct irqaction *irq_action[8] = {
-+ NULL, /* SW int 0 */
-+ NULL, /* SW int 1 */
-+ NULL, /* HW int 0 */
-+ NULL,
-+ NULL,
-+ NULL, /* HW int 3 */
-+ NULL, /* HW int 4 */
-+ &r4ktimer_action /* HW int 5 */
-+};
++ led_file:
++ remove_proc_entry("led", led_proc_dir);
++ out:
++ return 0;
+
-+static void end_avalanche_irq(unsigned int irq)
-+{
-+ if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-+ enable_avalanche_irq(irq);
+}
+
-+void disable_avalanche_irq(unsigned int irq_nr)
++void led_operation(int mod, int state)
+{
-+ unsigned long flags;
-+ unsigned long chan_nr=0;
-+ unsigned long int_bit=0;
+
-+ if(irq_nr >= AVALANCHE_INT_END)
-+ {
-+ printk("whee, invalid irq_nr %d\n", irq_nr);
-+ panic("IRQ, you lose...");
++ unsigned int flags;
++
++ spin_lock_irqsave(&config_lock, flags);
++#if 1
++ /* Ron Add for ADSL LED blink */
++ //printk("mod==%d state==%d\n",mod,state);
++
++ if (mod == 1) {
++ switch (state) {
++ /* off */
++ case 1:
++ my_mode = 1;
++ my_blink_count = 0;
++ my_led_off(GPIO_ADSL_ACT, -1);
++ my_led_off(GPIO_ADSL_DOWN, -1);
++ break;
++ /* sync */
++ case 2:
++ if (my_mode == 1) {
++ my_mode = 2;
++ my_led_off(GPIO_ADSL_ACT, -1);
++ my_blink_count++;
++ }
++ break;
++ /* on */
++ case 3:
++ my_mode = 3;
++ my_blink_count = 0;
++ my_led_off(GPIO_ADSL_DOWN, -1);
++ my_led_on(GPIO_ADSL_ACT, -1);
++ break;
++ /* off */
++ case 4:
++ my_mode = 4;
++ my_led_off(GPIO_ADSL_DOWN, -1);
++ my_blink_count++;
++ break;
++ }
++ } /* Ron add for ADSL LED Blink */
++#endif
++ if ((mod >= MAX_MOD_ID) || (state >= MAX_STATE_ID)) {
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
+ }
-+
-+ save_and_cli(flags);
-+
-+
-+ if(irq_nr < MIPS_EXCEPTION_OFFSET)
-+ {
-+ /* disable mips exception */
-+
-+ int_bit = read_c0_status() & ~(1 << (8+irq_nr));
-+ change_c0_status(ST0_IM,int_bit);
-+ restore_flags(flags);
++ if (modArr[mod] == NULL) {
++ spin_unlock_irqrestore(&config_lock, flags);
++ return;
++ }
++ if (modArr[mod]->states[state] == NULL) {
++ spin_unlock_irqrestore(&config_lock, flags);
+ return;
+ }
++ /* Call the function handler */
++ modArr[mod]->states[state]->handler(modArr[mod]->states[state]);
+
-+ /* irq_nr represents the line number for the interrupt. We must
-+ * disable the channel number associated with that line number.
-+ */
++ spin_unlock_irqrestore(&config_lock, flags);
++}
+
-+ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
-+ chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
-+ else
-+ chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
++void register_led_drv(int device, led_reg_t * pInfo)
++{
++ unsigned int flags;
++ struct timer_list *pTimer = NULL;
+
-+ /* disable the interrupt channel bit */
++ spin_lock_irqsave(&config_lock, flags);
+
-+ /* primary interrupt #'s 0-31 */
++ led_arr[device].led = pInfo;
++ if (led_arr[device].led->init != 0x00)
++ led_arr[device].led->init(led_arr[device].led->param);
++ if (led_arr[device].led->offfunc != 0x00)
++ led_arr[device].led->offfunc(led_arr[device].led->param);
+
-+ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
-+ avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
++ /* Create a timer for blinking */
++ pTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
++ init_timer(pTimer);
++ pTimer->function = led_timer_func;
++ pTimer->data = 0;
++ led_arr[device].pTimer = pTimer;
++ led_arr[device].timer_running = 0;
+
-+ /* primary interrupt #'s 32-39 */
-+
-+ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
-+ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
-+ avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
-+
-+ else /* secondary interrupt #'s 0-31 */
-+ avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
++ spin_unlock_irqrestore(&config_lock, flags);
+
-+ restore_flags(flags);
++ return;
+}
+
-+void enable_avalanche_irq(unsigned int irq_nr)
++void deregister_led_drv(int device)
+{
-+ unsigned long flags;
-+ unsigned long chan_nr=0;
-+ unsigned long int_bit=0;
++ unsigned int flags;
+
-+ if(irq_nr > AVALANCHE_INT_END) {
-+ printk("whee, invalid irq_nr %d\n", irq_nr);
-+ panic("IRQ, you lose...");
-+ }
++ spin_lock_irqsave(&config_lock, flags);
++ led_arr[device].led = NULL;
+
-+ save_and_cli(flags);
++ if (led_arr[device].pTimer != NULL) {
++ del_timer(led_arr[device].pTimer);
++ kfree(led_arr[device].pTimer);
++ }
++ spin_unlock_irqrestore(&config_lock, flags);
+
++ return;
++}
+
-+ if(irq_nr < MIPS_EXCEPTION_OFFSET)
-+ {
-+ /* Enable MIPS exceptions */
-+ int_bit = read_c0_status();
-+ change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
-+ restore_flags(flags);
-+ return;
-+ }
++EXPORT_SYMBOL_NOVERS(led_init);
++EXPORT_SYMBOL_NOVERS(led_operation);
++EXPORT_SYMBOL_NOVERS(register_led_drv);
++EXPORT_SYMBOL_NOVERS(deregister_led_drv);
+diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-current/arch/mips/ar7/ar7/Makefile
+--- kernel-base/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/Makefile 2005-07-10 09:31:33.038504888 +0200
+@@ -0,0 +1,31 @@
++# $Id$
++# Copyright (C) $Date$ $Author$
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
-+ /* irq_nr represents the line number for the interrupt. We must
-+ * disable the channel number associated with that line number.
-+ */
++.S.s:
++ $(CPP) $(AFLAGS) $< -o $*.s
+
-+ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
-+ chan_nr = AVINTNUM(irq_nr);
-+ else
-+ chan_nr = line_to_channel[AVINTNUM(irq_nr)];
++.S.o:
++ $(CC) $(AFLAGS) -c $< -o $*.o
+
-+ /* enable the interrupt channel bit */
++EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
+
-+ /* primary interrupt #'s 0-31 */
-+ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
-+ avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
++O_TARGET := ar7.o
+
-+ /* primary interrupt #'s 32 throuth 39 */
-+ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
-+ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
-+ avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++export-objs:= ledmod.o gpio.o
++obj-y += ar7_paging.o ar7_jump.o ledmod.o gpio.o tnetd73xx_misc.o
+
-+ else /* secondary interrupt #'s 0-31 */
-+ avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
++include $(TOPDIR)/Rules.make
+diff -urN kernel-base/arch/mips/ar7/ar7/tnetd73xx_misc.c kernel-current/arch/mips/ar7/ar7/tnetd73xx_misc.c
+--- kernel-base/arch/mips/ar7/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/tnetd73xx_misc.c 2005-07-10 09:57:09.935860976 +0200
+@@ -0,0 +1,926 @@
++/******************************************************************************
++ * FILE PURPOSE: TNETD73xx Misc modules API Source
++ ******************************************************************************
++ * FILE NAME: tnetd73xx_misc.c
++ *
++ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
++ * FSER Modules API
++ * As per TNETD73xx specifications
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - Sharath Kumar PSP TII
++ * 14 Feb 03 - Anant Gole PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
+
-+ restore_flags(flags);
-+}
+
-+static unsigned int startup_avalanche_irq(unsigned int irq)
-+{
-+ enable_avalanche_irq(irq);
-+ return 0; /* never anything pending */
-+}
++#include <linux/stddef.h>
++#include <linux/types.h>
++#include <asm/ar7/tnetd73xx.h>
++#include <asm/ar7/tnetd73xx_misc.h>
+
++#define TRUE 1
++#define FALSE 0
+
-+int get_irq_list(char *buf)
++/* TNETD73XX Revision */
++__u32 tnetd73xx_get_revision(void)
+{
-+ int i, len = 0;
-+ int num = 0;
-+ struct irqaction *action;
-+
-+ for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
-+ {
-+ action = irq_action[i];
-+ if (!action)
-+ continue;
-+ len += sprintf(buf+len, "%2d: %8d %c %s",
-+ num, kstat.irqs[0][num],
-+ (action->flags & SA_INTERRUPT) ? '+' : ' ',
-+ action->name);
-+ for (action=action->next; action; action = action->next) {
-+ len += sprintf(buf+len, ",%s %s",
-+ (action->flags & SA_INTERRUPT) ? " +" : "",
-+ action->name);
-+ }
-+ len += sprintf(buf+len, " [MIPS interrupt]\n");
-+ }
++ /* Read Chip revision register - This register is from GPIO module */
++ return ( (__u32) REG32_DATA(TNETD73XX_CVR));
++}
+
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/
+
-+ for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
-+ {
-+ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
-+ action = hw0_irq_action_primary[i];
-+ else
-+ action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
-+ if (!action)
-+ continue;
-+ len += sprintf(buf+len, "%2d: %8d %c %s",
-+ num, kstat.irqs[0][ LNXINTNUM(i) ],
-+ (action->flags & SA_INTERRUPT) ? '+' : ' ',
-+ action->name);
+
-+ for (action=action->next; action; action = action->next)
-+ {
-+ len += sprintf(buf+len, ",%s %s",
-+ (action->flags & SA_INTERRUPT) ? " +" : "",
-+ action->name);
-+ }
++void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
++{
++ __u32 reset_status;
++
++ /* read current reset register */
++ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++
++ if (reset_ctrl == OUT_OF_RESET)
++ {
++ /* bring module out of reset */
++ reset_status |= (1 << reset_module);
++ }
++ else
++ {
++ /* put module in reset */
++ reset_status &= (~(1 << reset_module));
++ }
++
++ /* write to the reset register */
++ REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
++}
+
-+ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
-+ len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
-+ else
-+ len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
+
-+ }
++TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
++{
++ __u32 reset_status;
+
-+ return len;
++ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++ return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
+}
+
-+int request_irq(unsigned int irq,
-+ void (*handler)(int, void *, struct pt_regs *),
-+ unsigned long irqflags,
-+ const char * devname,
-+ void *dev_id)
++void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
+{
-+ struct irqaction *action;
++ REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
++}
+
-+ if (irq > AVALANCHE_INT_END)
-+ return -EINVAL;
-+ if (!handler)
-+ return -EINVAL;
++#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
+
-+ action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
-+ if(!action)
-+ return -ENOMEM;
++TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
++{
++ __u32 sys_reset_status;
+
-+ action->handler = handler;
-+ action->flags = irqflags;
-+ action->mask = 0;
-+ action->name = devname;
-+ irq_desc_ti[irq].action = action;
-+ action->dev_id = dev_id;
++ REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
+
-+ action->next = 0;
++ return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
++}
+
-+ if(irq < MIPS_EXCEPTION_OFFSET)
-+ {
-+ irq_action[irq] = action;
-+ enable_avalanche_irq(irq);
-+ return 0;
-+ }
+
-+ if(irq < AVALANCHE_INT_END_PRIMARY)
-+ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
-+ else
-+ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
++#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
+
-+ enable_avalanche_irq(irq);
+
-+ return 0;
++void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
++{
++ __u32 power_status;
++
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++
++ if (power_ctrl == POWER_CTRL_POWER_DOWN)
++ {
++ /* power down the module */
++ power_status |= (1 << power_module);
++ }
++ else
++ {
++ /* power on the module */
++ power_status &= (~(1 << power_module));
++ }
++
++ /* write to the reset register */
++ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
+}
+
-+void free_irq(unsigned int irq, void *dev_id)
++TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
+{
-+ struct irqaction *action;
++ __u32 power_status;
+
-+ if (irq > AVALANCHE_INT_END) {
-+ printk("Trying to free IRQ%d\n",irq);
-+ return;
-+ }
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
+
-+ if(irq < MIPS_EXCEPTION_OFFSET)
-+ {
-+ action = irq_action[irq];
-+ irq_action[irq] = NULL;
-+ irq_desc_ti[irq].action = NULL;
-+ disable_avalanche_irq(irq);
-+ kfree(action);
-+ return;
-+ }
++ return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
++}
+
-+ if(irq < AVALANCHE_INT_END_PRIMARY) {
-+ action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
-+ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
-+ irq_desc_ti[irq].action = NULL;
-+ }
-+ else {
-+ action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
-+ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
-+ irq_desc_ti[irq].action = NULL;
-+ }
++void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
++{
++ __u32 power_status;
+
-+ disable_avalanche_irq(irq);
-+ kfree(action);
-+}
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
+
-+#ifdef CONFIG_KGDB
-+extern void breakpoint(void);
-+extern int remote_debug;
-+#endif
++ power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
++ power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
+
-+//void init_IRQ(void) __init;
-+void __init init_IRQ(void)
++ /* write to power down control register */
++ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
++}
++
++TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
+{
-+ int i;
++ __u32 power_status;
+
-+ avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
-+ avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
-+ avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
-+ avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
++ /* read current power down control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
+
-+ /* Disable interrupts and clear pending
-+ */
++ power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
++ power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
+
-+ avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
-+ avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
-+ avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
-+ avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
-+ avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
-+ avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
++ return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
++}
+
+
-+ // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
-+ /* hack for speeding up the pacing. */
-+ printk("the pacing pre-scalar has been set as 600.\n");
-+ avalanche_hw0_ipaceregs->ipacep = 600;
-+ /* Channel to line mapping, Line to Channel mapping */
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/
+
-+ for(i = 0; i < 40; i++)
-+ avalanche_int_set(i,i);
++#define TNETD73XX_WAKEUP_POLARITY_BIT 16
+
-+ /* Now safe to set the exception vector. */
-+ set_except_vector(0, mipsIRQ);
++void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
++ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
++ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
++{
++ __u32 wakeup_status;
++
++ /* read the wakeup control register */
++ REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++
++ /* enable/disable */
++ if (wakeup_ctrl == WAKEUP_ENABLED)
++ {
++ /* enable wakeup */
++ wakeup_status |= wakeup_int;
++ }
++ else
++ {
++ /* disable wakeup */
++ wakeup_status &= (~wakeup_int);
++ }
++
++ /* set polarity */
++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
++ {
++ wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
++ }
++ else
++ {
++ wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
++ }
++
++ /* write the wakeup control register */
++ REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++}
+
-+ /* Setup the IRQ description array. These will be mapped
-+ * as flat interrupts numbers. The mapping is as follows
-+ *
-+ * 0-7 MIPS CPU Exceptions (HW/SW)
-+ * 8-46 Primary Interrupts (Avalanche)
-+ * 47-78 Secondary Interrupts (Avalanche)
-+ */
+
-+ for (i = 0; i <= AVALANCHE_INT_END; i++)
-+ {
-+ irq_desc_ti[i].status = IRQ_DISABLED;
-+ irq_desc_ti[i].action = 0;
-+ irq_desc_ti[i].depth = 1;
-+ irq_desc_ti[i].handler = &avalanche_irq_type;
-+ }
++/*****************************************************************************
++ * FSER Control
++ *****************************************************************************/
+
-+#ifdef CONFIG_KGDB
-+ if (remote_debug)
-+ {
-+ set_debug_traps();
-+ breakpoint();
-+ }
-+#endif
++void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
++{
++ REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
+}
+
++/*****************************************************************************
++ * Clock Control
++ *****************************************************************************/
+
-+void avalanche_hw0_irqdispatch(struct pt_regs *regs)
++#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
++#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
++#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
++#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
++
++#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
++#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
++
++#define CLKC_PRE_DIVIDER 0x0000001F
++#define CLKC_POST_DIVIDER 0x001F0000
++
++#define CLKC_PLL_STATUS 0x1
++#define CLKC_PLL_FACTOR 0x0000F000
++
++#define BOOTCR_PLL_BYPASS (1 << 5)
++#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
++
++#define MIPS_PLL_SELECT 0x00030000
++#define SYSTEM_PLL_SELECT 0x0000C000
++#define USB_PLL_SELECT 0x000C0000
++#define ADSLSS_PLL_SELECT 0x00C00000
++
++#define MIPS_AFECLKI_SELECT 0x00000000
++#define MIPS_REFCLKI_SELECT 0x00010000
++#define MIPS_XTAL3IN_SELECT 0x00020000
++
++#define SYSTEM_AFECLKI_SELECT 0x00000000
++#define SYSTEM_REFCLKI_SELECT 0x00004000
++#define SYSTEM_XTAL3IN_SELECT 0x00008000
++#define SYSTEM_MIPSPLL_SELECT 0x0000C000
++
++#define USB_SYSPLL_SELECT 0x00000000
++#define USB_REFCLKI_SELECT 0x00040000
++#define USB_XTAL3IN_SELECT 0x00080000
++#define USB_MIPSPLL_SELECT 0x000C0000
++
++#define ADSLSS_AFECLKI_SELECT 0x00000000
++#define ADSLSS_REFCLKI_SELECT 0x00400000
++#define ADSLSS_XTAL3IN_SELECT 0x00800000
++#define ADSLSS_MIPSPLL_SELECT 0x00C00000
++
++#define SYS_MAX CLK_MHZ(150)
++#define SYS_MIN CLK_MHZ(1)
++
++#define MIPS_SYNC_MAX SYS_MAX
++#define MIPS_ASYNC_MAX CLK_MHZ(160)
++#define MIPS_MIN CLK_MHZ(1)
++
++#define USB_MAX CLK_MHZ(100)
++#define USB_MIN CLK_MHZ(1)
++
++#define ADSL_MAX CLK_MHZ(180)
++#define ADSL_MIN CLK_MHZ(1)
++
++#define PLL_MUL_MAXFACTOR 15
++#define MAX_DIV_VALUE 32
++#define MIN_DIV_VALUE 1
++
++#define MIN_PLL_INP_FREQ CLK_MHZ(8)
++#define MAX_PLL_INP_FREQ CLK_MHZ(100)
++
++#define DIVIDER_LOCK_TIME 10100
++#define PLL_LOCK_TIME 10100 * 75
++
++
++
++/****************************************************************************
++ * DATA PURPOSE: PRIVATE Variables
++ **************************************************************************/
++static __u32 *clk_src[4];
++static __u32 mips_pll_out;
++static __u32 sys_pll_out;
++static __u32 afeclk_inp;
++static __u32 refclk_inp;
++static __u32 xtal_inp;
++static __u32 present_min;
++static __u32 present_max;
++
++/* Forward References */
++static __u32 find_gcd(__u32 min, __u32 max);
++static __u32 compute_prediv( __u32 divider, __u32 min, __u32 max);
++static void get_val(__u32 base_freq, __u32 output_freq,__u32 *multiplier, __u32 *divider);
++static __u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
++static void find_approx(__u32 *,__u32 *,__u32);
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_init
++ ****************************************************************************
++ * Description: The routine initializes the internal variables depending on
++ * on the sources selected for different clocks.
++ ***************************************************************************/
++void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in)
+{
-+ struct irqaction *action;
-+ int irq, cpu = smp_processor_id();
-+ unsigned long int_line_number,status;
-+ int i,secondary = 0;
-+ int chan_nr=0;
+
-+ int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
-+ chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
++ __u32 choice;
+
++ afeclk_inp = afeclk;
++ refclk_inp = refclk;
++ xtal_inp = xtal3in;
+
-+ if(chan_nr < 32)
-+ {
-+ if( chan_nr != uni_secondary_interrupt)
-+ avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
++ switch(choice)
++ {
++ case MIPS_AFECLKI_SELECT:
++ clk_src[CLKC_MIPS] = &afeclk_inp;
++ break;
+
-+ }
++ case MIPS_REFCLKI_SELECT:
++ clk_src[CLKC_MIPS] = &refclk_inp;
++ break;
+
-+ if((chan_nr < 40) && (chan_nr > 31))
-+ {
-+ avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
-+ }
++ case MIPS_XTAL3IN_SELECT:
++ clk_src[CLKC_MIPS] = &xtal_inp;
++ break;
+
++ default :
++ clk_src[CLKC_MIPS] = 0;
+
-+ /* If the Priority Interrupt Index Register returns 40 then no
-+ * interrupts are pending
-+ */
++ }
+
-+ if(chan_nr == 40)
-+ return;
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
++ switch(choice)
++ {
++ case SYSTEM_AFECLKI_SELECT:
++ clk_src[CLKC_SYS] = &afeclk_inp;
++ break;
+
-+ if(chan_nr == uni_secondary_interrupt)
-+ {
-+ status = avalanche_hw0_ecregs->exsr;
-+ for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
-+ {
-+ if (status & 1<<i)
-+ {
-+ /* clear secondary interrupt */
-+ avalanche_hw0_ecregs->excr = 1 << i;
-+ break;
-+ }
-+ }
-+ irq = i;
-+ secondary = 1;
++ case SYSTEM_REFCLKI_SELECT:
++ clk_src[CLKC_SYS] = &refclk_inp;
++ break;
+
-+ /* clear the universal secondary interrupt */
-+ avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
++ case SYSTEM_XTAL3IN_SELECT:
++ clk_src[CLKC_SYS] = &xtal_inp;
++ break;
+
-+ }
-+ else
-+ irq = chan_nr;
++ case SYSTEM_MIPSPLL_SELECT:
++ clk_src[CLKC_SYS] = &mips_pll_out;
++ break;
+
-+ /* Suraj Add code to clear secondary interrupt */
++ default :
++ clk_src[CLKC_SYS] = 0;
+
-+ if(secondary)
-+ action = hw0_irq_action_secondary[irq];
-+ else
-+ action = hw0_irq_action_primary[irq];
++ }
+
-+ /* if action == NULL, then we don't have a handler for the irq */
+
-+ if ( action == NULL ) {
-+ printk("No handler for hw0 irq: %i\n", irq);
-+ return;
-+ }
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
++ switch(choice)
++ {
++ case ADSLSS_AFECLKI_SELECT:
++ clk_src[CLKC_ADSLSS] = &afeclk_inp;
++ break;
+
-+ irq_enter(cpu,irq);
-+ if(secondary)
-+ {
-+ kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
-+ action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
-+ }
-+ else
-+ {
-+ kstat.irqs[0][irq + 8]++;
-+ action->handler(LNXINTNUM(irq), action->dev_id, regs);
-+ }
++ case ADSLSS_REFCLKI_SELECT:
++ clk_src[CLKC_ADSLSS] = &refclk_inp;
++ break;
+
-+ irq_exit(cpu,irq);
++ case ADSLSS_XTAL3IN_SELECT:
++ clk_src[CLKC_ADSLSS] = &xtal_inp;
++ break;
+
-+ if(softirq_pending(cpu))
-+ do_softirq();
++ case ADSLSS_MIPSPLL_SELECT:
++ clk_src[CLKC_ADSLSS] = &mips_pll_out;
++ break;
+
-+ return;
++ default :
++ clk_src[CLKC_ADSLSS] = 0;
++
++ }
++
++
++ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
++ switch(choice)
++ {
++ case USB_SYSPLL_SELECT:
++ clk_src[CLKC_USB] = &sys_pll_out ;
++ break;
++
++ case USB_REFCLKI_SELECT:
++ clk_src[CLKC_USB] = &refclk_inp;
++ break;
++
++ case USB_XTAL3IN_SELECT:
++ clk_src[CLKC_USB] = &xtal_inp;
++ break;
++
++ case USB_MIPSPLL_SELECT:
++ clk_src[CLKC_USB] = &mips_pll_out;
++ break;
++
++ default :
++ clk_src[CLKC_USB] = 0;
++
++ }
+}
+
-+void avalanche_int_set(int channel, int line)
++
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_set_freq
++ ****************************************************************************
++ * Description: The above routine is called to set the output_frequency of the
++ * selected clock(using clk_id) to the required value given
++ * by the variable output_freq.
++ ***************************************************************************/
++TNETD73XX_ERR tnetd73xx_clkc_set_freq
++(
++ TNETD73XX_CLKC_ID_T clk_id,
++ __u32 output_freq
++)
+{
-+ switch(channel)
-+ {
-+ case(0):
-+ avalanche_hw0_chregs->cintnr0 = line;
-+ break;
-+ case(1):
-+ avalanche_hw0_chregs->cintnr1 = line;
-+ break;
-+ case(2):
-+ avalanche_hw0_chregs->cintnr2 = line;
-+ break;
-+ case(3):
-+ avalanche_hw0_chregs->cintnr3 = line;
-+ break;
-+ case(4):
-+ avalanche_hw0_chregs->cintnr4 = line;
-+ break;
-+ case(5):
-+ avalanche_hw0_chregs->cintnr5 = line;
-+ break;
-+ case(6):
-+ avalanche_hw0_chregs->cintnr6 = line;
-+ break;
-+ case(7):
-+ avalanche_hw0_chregs->cintnr7 = line;
-+ break;
-+ case(8):
-+ avalanche_hw0_chregs->cintnr8 = line;
-+ break;
-+ case(9):
-+ avalanche_hw0_chregs->cintnr9 = line;
-+ break;
-+ case(10):
-+ avalanche_hw0_chregs->cintnr10 = line;
-+ break;
-+ case(11):
-+ avalanche_hw0_chregs->cintnr11 = line;
-+ break;
-+ case(12):
-+ avalanche_hw0_chregs->cintnr12 = line;
-+ break;
-+ case(13):
-+ avalanche_hw0_chregs->cintnr13 = line;
-+ break;
-+ case(14):
-+ avalanche_hw0_chregs->cintnr14 = line;
-+ break;
-+ case(15):
-+ avalanche_hw0_chregs->cintnr15 = line;
-+ break;
-+ case(16):
-+ avalanche_hw0_chregs->cintnr16 = line;
-+ break;
-+ case(17):
-+ avalanche_hw0_chregs->cintnr17 = line;
-+ break;
-+ case(18):
-+ avalanche_hw0_chregs->cintnr18 = line;
-+ break;
-+ case(19):
-+ avalanche_hw0_chregs->cintnr19 = line;
-+ break;
-+ case(20):
-+ avalanche_hw0_chregs->cintnr20 = line;
-+ break;
-+ case(21):
-+ avalanche_hw0_chregs->cintnr21 = line;
-+ break;
-+ case(22):
-+ avalanche_hw0_chregs->cintnr22 = line;
-+ break;
-+ case(23):
-+ avalanche_hw0_chregs->cintnr23 = line;
-+ break;
-+ case(24):
-+ avalanche_hw0_chregs->cintnr24 = line;
-+ break;
-+ case(25):
-+ avalanche_hw0_chregs->cintnr25 = line;
-+ break;
-+ case(26):
-+ avalanche_hw0_chregs->cintnr26 = line;
-+ break;
-+ case(27):
-+ avalanche_hw0_chregs->cintnr27 = line;
-+ break;
-+ case(28):
-+ avalanche_hw0_chregs->cintnr28 = line;
-+ break;
-+ case(29):
-+ avalanche_hw0_chregs->cintnr29 = line;
-+ break;
-+ case(30):
-+ avalanche_hw0_chregs->cintnr30 = line;
-+ break;
-+ case(31):
-+ avalanche_hw0_chregs->cintnr31 = line;
-+ break;
-+ case(32):
-+ avalanche_hw0_chregs->cintnr32 = line;
-+ break;
-+ case(33):
-+ avalanche_hw0_chregs->cintnr33 = line;
-+ break;
-+ case(34):
-+ avalanche_hw0_chregs->cintnr34 = line;
-+ break;
-+ case(35):
-+ avalanche_hw0_chregs->cintnr35 = line;
-+ break;
-+ case(36):
-+ avalanche_hw0_chregs->cintnr36 = line;
-+ break;
-+ case(37):
-+ avalanche_hw0_chregs->cintnr37 = line;
-+ break;
-+ case(38):
-+ avalanche_hw0_chregs->cintnr38 = line;
-+ break;
-+ case(39):
-+ avalanche_hw0_chregs->cintnr39 = line;
-+ break;
-+ default:
-+ printk("Error: Unknown Avalanche interrupt channel\n");
-+ }
++ __u32 base_freq;
++ __u32 multiplier;
++ __u32 divider;
++ __u32 min_prediv;
++ __u32 max_prediv;
++ __u32 prediv;
++ __u32 postdiv;
++ __u32 temp;
++
++ /* check if PLLs are bypassed*/
++ if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ /*check if the requested output_frequency is in valid range*/
++ switch( clk_id )
++ {
++ case CLKC_SYS:
++ if( output_freq < SYS_MIN || output_freq > SYS_MAX)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = SYS_MIN;
++ present_max = SYS_MAX;
++ break;
++
++ case CLKC_MIPS:
++ if((output_freq < MIPS_MIN) ||
++ (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = MIPS_MIN;
++ present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
++ break;
++
++ case CLKC_USB:
++ if( output_freq < USB_MIN || output_freq > USB_MAX)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = USB_MIN;
++ present_max = USB_MAX;
++ break;
++
++ case CLKC_ADSLSS:
++ if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++ present_min = ADSL_MIN;
++ present_max = ADSL_MAX;
++ break;
++ }
++
++
++ base_freq = get_base_frequency(clk_id);
++
++
++ /* check for minimum base frequency value */
++ if( base_freq < MIN_PLL_INP_FREQ)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ get_val(output_freq, base_freq, &multiplier, ÷r);
++
++ /* check multiplier range */
++ if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ /* check divider value */
++ if( divider == 0 )
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++ /*compute minimum and maximum predivider values */
++ min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
++ max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
++
++ /*adjust the value of divider so that it not less than minimum predivider value*/
++ if (divider < min_prediv)
++ {
++ temp = CEIL(min_prediv, divider);
++ if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
++ {
++ return TNETD73XX_ERR_ERROR ;
++ }
++ else
++ {
++ multiplier = temp * multiplier;
++ divider = min_prediv;
++ }
++
++ }
++
++ /* compute predivider and postdivider values */
++ prediv = compute_prediv (divider, min_prediv, max_prediv);
++ postdiv = CEIL(divider,prediv);
++
++ /*return fail if postdivider value falls out of range */
++ if(postdiv > MAX_DIV_VALUE)
++ {
++ return TNETD73XX_ERR_ERROR;
++ }
++
++
++ /*write predivider and postdivider values*/
++ /* pre-Divider and post-divider are 5 bit N+1 dividers */
++ REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
++
++ /*wait for divider output to stabilise*/
++ for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
++
++ /*write to PLL clock register*/
++
++ if(clk_id == CLKC_SYS)
++ {
++ /* but before writing put DRAM to hold mode */
++ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
++ }
++ /*Bring PLL into div mode */
++ REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
++
++ /*compute the word to be written to PLLCR
++ *corresponding to multiplier value
++ */
++ multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
++
++ /* wait till PLL enters div mode */
++ while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
++ /*nothing*/;
++
++ REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
++
++ while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
++ /*nothing*/;
++
++
++ /*wait for External pll to lock*/
++ for(temp =0; temp < PLL_LOCK_TIME; temp++);
++
++ if(clk_id == CLKC_SYS)
++ {
++ /* Bring DRAM out of hold */
++ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
++ }
+
-+ line_to_channel[line] = channel; /* Suraj check */
++ return TNETD73XX_ERR_OK ;
++}
+
-+ if (channel == UNIFIED_SECONDARY_INTERRUPT)
-+ uni_secondary_interrupt = line;
++/****************************************************************************
++ * FUNCTION: tnetd73xx_clkc_get_freq
++ ****************************************************************************
++ * Description: The above routine is called to get the output_frequency of the
++ * selected clock( clk_id)
++ ***************************************************************************/
++__u32 tnetd73xx_clkc_get_freq
++(
++ TNETD73XX_CLKC_ID_T clk_id
++)
++{
++
++ __u32 clk_ctrl_register;
++ __u32 clk_pll_setting;
++ __u32 clk_predivider;
++ __u32 clk_postdivider;
++ __u16 pll_factor;
++ __u32 base_freq;
++ __u32 divider;
++
++ base_freq = get_base_frequency(clk_id);
++
++ clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
++
++ /* pre-Divider and post-divider are 5 bit N+1 dividers */
++ clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
++ clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
++
++ divider = clk_predivider * clk_postdivider;
++
++
++ if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
++ {
++ return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
++ }
++
++
++ else
++ {
++ /* return the current clock speed based upon the PLL setting */
++ clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
++
++ /* Get the PLL multiplication factor */
++ pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
++
++ /* Check if we're in divide mode or multiply mode */
++ if((clk_pll_setting & 0x1) == 0)
++ {
++ /* We're in divide mode */
++ if(pll_factor < 0x10)
++ return (CEIL(base_freq >> 1, divider));
++ else
++ return (CEIL(base_freq >> 2, divider));
++ }
++
++ else /* We're in PLL mode */
++ {
++ /* See if PLLNDIV & PLLDIV are set */
++ if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
++ {
++ if(clk_pll_setting & 0x1000)
++ {
++ /* clk = base_freq * k/2 */
++ return(CEIL((base_freq * pll_factor) >> 1, divider));
++ }
++ else
++ {
++ /* clk = base_freq * (k-1) / 4)*/
++ return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
++ }
++ }
++ else
++ {
++ if(pll_factor < 0x10)
++ {
++ /* clk = base_freq * k */
++ return(CEIL(base_freq * pll_factor, divider));
++ }
++
++ else
++ {
++ /* clk = base_freq */
++ return(CEIL(base_freq, divider));
++ }
++ }
++ }
++ return(0); /* Should never reach here */
++
++ }
+
+}
+
-diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/memory.c
---- linux-2.4.30/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/memory.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,130 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * PROM library functions for acquiring/using memory descriptors given to
-+ * us from the YAMON.
-+ *
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/bootmem.h>
+
-+#include <asm/bootinfo.h>
-+#include <asm/page.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
++/* local helper functions */
+
-+enum yamon_memtypes {
-+ yamon_dontuse,
-+ yamon_prom,
-+ yamon_free,
-+};
-+struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
++ /****************************************************************************
++ * FUNCTION: get_base_frequency
++ ****************************************************************************
++ * Description: The above routine is called to get base frequency of the clocks.
++ ***************************************************************************/
+
-+/* References to section boundaries */
-+extern char _end;
++static __u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
++{
++ /* update the current MIPs PLL output value, if the required
++ * source is MIPS PLL
++ */
++ if ( clk_src[clk_id] == &mips_pll_out)
++ {
++ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
++ }
+
-+#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
+
++ /* update the current System PLL output value, if the required
++ * source is system PLL
++ */
++ if ( clk_src[clk_id] == &sys_pll_out)
++ {
++ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
++ }
+
-+struct prom_pmemblock * __init prom_getmdesc(void)
-+{
-+ char *memsize_str;
-+ unsigned int memsize;
++ return (*clk_src[clk_id]);
+
-+ memsize_str = prom_getenv("memsize");
-+ if (!memsize_str) {
-+ memsize = 0x02000000;
-+ } else {
-+ memsize = simple_strtol(memsize_str, NULL, 0);
-+ }
++}
+
-+ memset(mdesc, 0, sizeof(mdesc));
+
-+ mdesc[0].type = yamon_dontuse;
-+ mdesc[0].base = 0x00000000;
-+ mdesc[0].size = AVALANCHE_SDRAM_BASE;
+
-+ mdesc[1].type = yamon_prom;
-+ mdesc[1].base = AVALANCHE_SDRAM_BASE;
-+ mdesc[1].size = 0x00020000;
++/****************************************************************************
++ * FUNCTION: find_gcd
++ ****************************************************************************
++ * Description: The above routine is called to find gcd of 2 numbers.
++ ***************************************************************************/
++static __u32 find_gcd
++(
++__u32 min,
++__u32 max
++)
++{
++ if (max % min == 0)
++ {
++ return min;
++ }
++ else
++ {
++ return find_gcd(max % min, min);
++ }
++}
+
-+ mdesc[2].type = yamon_free;
-+ mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
-+ mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
++/****************************************************************************
++ * FUNCTION: compute_prediv
++ ****************************************************************************
++ * Description: The above routine is called to compute predivider value
++ ***************************************************************************/
++static __u32 compute_prediv(__u32 divider, __u32 min, __u32 max)
++{
++__u16 prediv;
+
-+ return &mdesc[0];
++/* return the divider itself it it falls within the range of predivider*/
++if (min <= divider && divider <= max)
++{
++ return divider;
+}
+
-+static int __init prom_memtype_classify (unsigned int type)
++/* find a value for prediv such that it is a factor of divider */
++for (prediv = max; prediv >= min ; prediv--)
+{
-+ switch (type) {
-+ case yamon_free:
-+ return BOOT_MEM_RAM;
-+ case yamon_prom:
-+ return BOOT_MEM_ROM_DATA;
-+ default:
-+ return BOOT_MEM_RESERVED;
-+ }
++ if ( (divider % prediv) == 0 )
++ {
++ return prediv;
++ }
+}
+
-+void __init prom_meminit(void)
++/* No such factor exists, return min as prediv */
++return min;
++}
++
++/****************************************************************************
++ * FUNCTION: get_val
++ ****************************************************************************
++ * Description: This routine is called to get values of divider and multiplier.
++ ***************************************************************************/
++
++static void get_val(__u32 output_freq, __u32 base_freq,__u32 *multiplier, __u32 *divider)
+{
-+ struct prom_pmemblock *p;
++ __u32 temp_mul;
++ __u32 temp_div;
++ __u32 gcd;
++ __u32 min_freq;
++ __u32 max_freq;
+
-+ p = prom_getmdesc();
++ /* find gcd of base_freq, output_freq */
++ min_freq = (base_freq < output_freq) ? base_freq : output_freq;
++ max_freq = (base_freq > output_freq) ? base_freq : output_freq;
++ gcd = find_gcd(min_freq , max_freq);
+
-+ while (p->size) {
-+ long type;
-+ unsigned long base, size;
++ if(gcd == 0)
++ return; /* ERROR */
+
-+ type = prom_memtype_classify (p->type);
-+ base = p->base;
-+ size = p->size;
++ /* compute values of multiplier and divider */
++ temp_mul = output_freq / gcd;
++ temp_div = base_freq / gcd;
+
-+ add_memory_region(base, size, type);
-+ p++;
-+ }
++
++ /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
++ if( temp_mul > PLL_MUL_MAXFACTOR )
++ {
++ if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
++ return;
++
++ find_approx(&temp_mul,&temp_div,base_freq);
++ }
++
++ *multiplier = temp_mul;
++ *divider = temp_div;
+}
+
-+void __init prom_free_prom_memory (void)
++/****************************************************************************
++ * FUNCTION: find_approx
++ ****************************************************************************
++ * Description: This function gets the approx value of num/denom.
++ ***************************************************************************/
++
++static void find_approx(__u32 *num,__u32 *denom,__u32 base_freq)
+{
-+ int i;
-+ unsigned long freed = 0;
-+ unsigned long addr;
++ __u32 num1;
++ __u32 denom1;
++ __u32 num2;
++ __u32 denom2;
++ int closest;
++ int prev_closest;
++ __u32 temp_num;
++ __u32 temp_denom;
++ __u32 normalize;
++ __u32 gcd;
++ __u32 output_freq;
++
++ num1 = *num;
++ denom1 = *denom;
++
++ prev_closest = 0x7fffffff; /* maximum possible value */
++ num2 = num1;
++ denom2 = denom1;
++
++ /* start with max */
++ for(temp_num = 15; temp_num >=1; temp_num--)
++ {
++
++ temp_denom = CEIL(temp_num * denom1, num1);
++ output_freq = (temp_num * base_freq) / temp_denom;
++
++ if(temp_denom < 1)
++ {
++ break;
++ }
++ else
++ {
++ normalize = CEIL(num1,temp_num);
++ closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
++ if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
++ {
++ prev_closest = closest;
++ num2 = temp_num;
++ denom2 = temp_denom;
++ }
++
++ }
++
++ }
++
++ gcd = find_gcd(num2,denom2);
++ num2 = num2 / gcd;
++ denom2 = denom2 /gcd;
++
++ *num = num2;
++ *denom = denom2;
++}
+
-+ for (i = 0; i < boot_mem_map.nr_map; i++) {
-+ if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
-+ continue;
+
-+ addr = boot_mem_map.map[i].addr;
-+ while (addr < boot_mem_map.map[i].addr
-+ + boot_mem_map.map[i].size) {
-+ ClearPageReserved(virt_to_page(__va(addr)));
-+ set_page_count(virt_to_page(__va(addr)), 1);
-+ free_page((unsigned long)__va(addr));
-+ addr += PAGE_SIZE;
-+ freed += PAGE_SIZE;
-+ }
-+ }
-+ printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_init
++ ***************************************************************************/
++void tnetd73xx_gpio_init()
++{
++ /* Bring module out of reset */
++ tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
++ REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
+}
-diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S
---- linux-2.4.30/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,120 @@
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_ctrl
++ ***************************************************************************/
++void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
++ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
++ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
++{
++ __u32 pin_status;
++ REG32_READ(TNETD73XX_GPIOENR, pin_status);
++ if (pin_mode == GPIO_PIN)
++ {
++ pin_status |= (1 << gpio_pin);
++ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++
++ /* Set pin direction */
++ REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
++ if (pin_direction == GPIO_INPUT_PIN)
++ {
++ pin_status |= (1 << gpio_pin);
++ }
++ else /* GPIO_OUTPUT_PIN */
++ {
++ pin_status &= (~(1 << gpio_pin));
++ }
++ REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
++ }
++ else /* FUNCTIONAL PIN */
++ {
++ pin_status &= (~(1 << gpio_pin));
++ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++ }
++
++}
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_out
++ ***************************************************************************/
++void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
++{
++ __u32 pin_value;
++
++ REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
++ if (value == TRUE)
++ {
++ pin_value |= (1 << gpio_pin);
++ }
++ else
++ {
++ pin_value &= (~(1 << gpio_pin));
++ }
++ REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
++}
++
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_in
++ ***************************************************************************/
++int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
++{
++ __u32 pin_value;
++ REG32_READ(TNETD73XX_GPIODINR, pin_value);
++ return ( (pin_value & (1 << gpio_pin)) ? TRUE : FALSE );
++}
++
+diff -urN kernel-base/arch/mips/ar7/cmdline.c kernel-current/arch/mips/ar7/cmdline.c
+--- kernel-base/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266864 +0200
+@@ -0,0 +1,64 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
-+ * ########################################################################
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Interrupt exception dispatch code.
-+ *
-+ */
-+#include <linux/config.h>
-+
-+#include <asm/asm.h>
-+#include <asm/mipsregs.h>
-+#include <asm/regdef.h>
-+#include <asm/stackframe.h>
-+
-+/* A lot of complication here is taken away because:
-+ *
-+ * 1) We handle one interrupt and return, sitting in a loop and moving across
-+ * all the pending IRQ bits in the cause register is _NOT_ the answer, the
-+ * common case is one pending IRQ so optimize in that direction.
-+ *
-+ * 2) We need not check against bits in the status register IRQ mask, that
-+ * would make this routine slow as hell.
-+ *
-+ * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
-+ * between like BSD spl() brain-damage.
-+ *
-+ * Furthermore, the IRQs on the MIPS board look basically (barring software
-+ * IRQs which we don't use at all and all external interrupt sources are
-+ * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
-+ *
-+ * MIPS IRQ Source
-+ * -------- ------
-+ * 0 Software (ignored)
-+ * 1 Software (ignored)
-+ * 2 Combined hardware interrupt (hw0)
-+ * 3 Hardware (ignored)
-+ * 4 Hardware (ignored)
-+ * 5 Hardware (ignored)
-+ * 6 Hardware (ignored)
-+ * 7 R4k timer (what we use)
-+ *
-+ * Note: On the SEAD board thing are a little bit different.
-+ * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
-+ * wired to UART1.
-+ *
-+ * We handle the IRQ according to _our_ priority which is:
-+ *
-+ * Highest ---- R4k Timer
-+ * Lowest ---- Combined hardware interrupt
-+ *
-+ * then we just return, if multiple IRQs are pending then we will just take
-+ * another exception, big deal.
++ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
+ */
++#include <linux/init.h>
++#include <linux/string.h>
+
-+.text
-+.set noreorder
-+.set noat
-+ .align 5
-+NESTED(mipsIRQ, PT_SIZE, sp)
-+ SAVE_ALL
-+ CLI
-+ .set at
-+
-+ mfc0 s0, CP0_CAUSE # get irq bits
++#include <asm/bootinfo.h>
+
-+ /* First we check for r4k counter/timer IRQ. */
-+ andi a0, s0, CAUSEF_IP7
-+ beq a0, zero, 1f
-+ andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
++extern int prom_argc;
++extern int *_prom_argv;
+
-+ /* Wheee, a timer interrupt. */
-+ move a0, sp
-+ jal ar7_timer_interrupt
-+ nop
++/*
++ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
++ * This macro take care of sign extension.
++ */
++#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
+
-+ j ret_from_irq
-+ nop
++char arcs_cmdline[CL_SIZE];
+
-+ 1:
-+ beq a0, zero, 1f # delay slot, check hw3 interrupt
-+ nop
++char * __init prom_getcmdline(void)
++{
++ return &(arcs_cmdline[0]);
++}
+
-+ /* Wheee, combined hardware level zero interrupt. */
-+ jal avalanche_hw0_irqdispatch
-+ move a0, sp # delay slot
+
-+ j ret_from_irq
-+ nop # delay slot
++void __init prom_init_cmdline(void)
++{
++ char *cp;
++ int actr;
+
-+ 1:
-+ /*
-+ * Here by mistake? This is possible, what can happen is that by the
-+ * time we take the exception the IRQ pin goes low, so just leave if
-+ * this is the case.
-+ */
-+ move a1,s0
-+ PRINT("Got interrupt: c0_cause = %08x\n")
-+ mfc0 a1, CP0_EPC
-+ PRINT("c0_epc = %08x\n")
++ actr = 1; /* Always ignore argv[0] */
+
-+ j ret_from_irq
-+ nop
-+END(mipsIRQ)
-diff -urN linux-2.4.30/arch/mips/ar7/printf.c linux-2.4.30.dev/arch/mips/ar7/printf.c
---- linux-2.4.30/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/printf.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,51 @@
++ cp = &(arcs_cmdline[0]);
++#ifdef CONFIG_CMDLINE_BOOL
++ strcpy(cp, CONFIG_CMDLINE);
++ cp += strlen(CONFIG_CMDLINE);
++ *cp++ = ' ';
++#endif
++ while(actr < prom_argc) {
++ strcpy(cp, prom_argv(actr));
++ cp += strlen(prom_argv(actr));
++ *cp++ = ' ';
++ actr++;
++ }
++ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
++ --cp;
++ *cp = '\0';
++}
+diff -urN kernel-base/arch/mips/ar7/init.c kernel-current/arch/mips/ar7/init.c
+--- kernel-base/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/init.c 2005-07-10 06:40:39.584266864 +0200
+@@ -0,0 +1,146 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
-+ * Putting things on the screen/serial line using Adam2 facilities.
++ * PROM library initialisation code.
+ */
-+
+#include <linux/config.h>
+#include <linux/init.h>
++#include <linux/string.h>
+#include <linux/kernel.h>
-+#include <linux/serial_reg.h>
-+#include <linux/spinlock.h>
++#include <linux/module.h>
++
+#include <asm/io.h>
-+#include <asm/serial.h>
-+#include <asm/addrspace.h>
-+#include <asm/ar7/ar7.h>
++#include <asm/mips-boards/prom.h>
++#include <asm/mips-boards/generic.h>
+
-+static char ppbuf[1024];
++/* Environment variable */
++typedef struct {
++ char *name;
++ char *val;
++} t_env_var;
+
-+void (*prom_print_str)(unsigned int out, char *s, int len);
++int prom_argc;
++int *_prom_argv, *_prom_envp;
+
-+void prom_printf(char *fmt, ...) __init;
-+void prom_printf(char *fmt, ...)
-+{
-+ va_list args;
-+ int len;
-+ prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
++/* max # of Adam2 environment variables */
++#define MAX_ENV_ENTRY 80
+
-+ va_start(args, fmt);
-+ vsprintf(ppbuf, fmt, args);
-+ len = strlen(ppbuf);
++static t_env_var local_envp[MAX_ENV_ENTRY];
++int init_debug = 0;
+
-+ prom_print_str(1, ppbuf, len);
++char *prom_getenv(char *envname)
++{
++ /*
++ * Return a pointer to the given environment variable.
++ * In 64-bit mode: we're using 64-bit pointers, but all pointers
++ * in the PROM structures are only 32-bit, so we need some
++ * workarounds, if we are running in 64-bit mode.
++ */
++ int i, index=0;
++ t_env_var *env = (t_env_var *) local_envp;
+
-+ va_end(args);
-+ return;
++ i = strlen(envname);
++ while (env->name) {
++ if(strncmp(envname, env->name, i) == 0) {
++ return(env->val);
++ }
++ env++;
++ }
+
++ return NULL;
+}
-diff -urN linux-2.4.30/arch/mips/ar7/reset.c linux-2.4.30.dev/arch/mips/ar7/reset.c
---- linux-2.4.30/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/reset.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,54 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Reset the MIPS boards.
-+ *
-+ */
-+#include <linux/config.h>
-+
-+#include <asm/reboot.h>
-+#include <asm/mips-boards/generic.h>
-+
-+static void ar7_machine_restart(char *command);
-+static void ar7_machine_halt(void);
-+static void ar7_machine_power_off(void);
+
-+static void ar7_machine_restart(char *command)
++static inline unsigned char str2hexnum(unsigned char c)
+{
-+
++ if (c >= '0' && c <= '9')
++ return c - '0';
++ if (c >= 'a' && c <= 'f')
++ return c - 'a' + 10;
++ return 0; /* foo */
+}
+
-+static void ar7_machine_halt(void)
++static inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
++ int i;
+
++ for (i = 0; i < 6; i++) {
++ unsigned char num;
++
++ if((*str == '.') || (*str == ':'))
++ str++;
++ num = str2hexnum(*str++) << 4;
++ num |= (str2hexnum(*str++));
++ ea[i] = num;
++ }
+}
+
-+static void ar7_machine_power_off(void)
++int get_ethernet_addr(char *ethernet_addr)
+{
++ char *ethaddr_str;
+
++ ethaddr_str = prom_getenv("ethaddr");
++ if (!ethaddr_str) {
++ printk("ethaddr not set in boot prom\n");
++ return -1;
++ }
++ str2eaddr(ethernet_addr, ethaddr_str);
++
++ if (init_debug > 1) {
++ int i;
++ printk("get_ethernet_addr: ");
++ for (i=0; i<5; i++)
++ printk("%02x:", (unsigned char)*(ethernet_addr+i));
++ printk("%02x\n", *(ethernet_addr+i));
++ }
++
++ return 0;
+}
+
-+void ar7_reboot_setup(void)
++int __init prom_init(int argc, char **argv, char **envp)
+{
-+ _machine_restart = ar7_machine_restart;
-+ _machine_halt = ar7_machine_halt;
-+ _machine_power_off = ar7_machine_power_off;
++ int i;
++ t_env_var *env = (t_env_var *) envp;
++
++ prom_argc = argc;
++ _prom_argv = (int *)argv;
++ _prom_envp = (int *)envp;
++
++ /* Copy what we need locally so we are not dependent on
++ * bootloader RAM. In Adam2, the environment parameters
++ * are in flash but the table that references them is in
++ * RAM
++ */
++ for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
++ if (env->name) {
++ local_envp[i].name = env->name;
++ local_envp[i].val = env->val;
++ } else {
++ local_envp[i].name = NULL;
++ local_envp[i].val = NULL;
++ }
++ }
++
++ set_io_port_base(0);
++
++ prom_printf("\nLINUX started...\n");
++ prom_init_cmdline();
++ prom_meminit();
++
++ return 0;
+}
-diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.dev/arch/mips/ar7/setup.c
---- linux-2.4.30/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/setup.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,150 @@
++
++EXPORT_SYMBOL(prom_getenv);
+diff -urN kernel-base/arch/mips/ar7/irq.c kernel-current/arch/mips/ar7/irq.c
+--- kernel-base/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/irq.c 2005-07-10 10:02:30.212171576 +0200
+@@ -0,0 +1,705 @@
+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
++ * Nitin Dhingra, iamnd@ti.com
++ * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
++ *
++ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Routines for generic manipulation of the interrupts found on the Texas
++ * Instruments avalanche board
++ *
+ */
++
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
-+#include <linux/mc146818rtc.h>
-+#include <linux/ioport.h>
-+
-+#include <asm/cpu.h>
-+#include <asm/bootinfo.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/proc_fs.h>
+#include <asm/irq.h>
-+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/prom.h>
++#include <asm/ar7/ar7.h>
++#include <asm/ar7/avalanche_intc.h>
++#include <asm/gdb-stub.h>
+
-+#include <asm/dma.h>
-+#include <asm/time.h>
-+#include <asm/traps.h>
+
++#define shutdown_avalanche_irq disable_avalanche_irq
++#define mask_and_ack_avalanche_irq disable_avalanche_irq
+
-+#define _LINK_KSEG0_
-+#define LITTLE_ENDIAN
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
++static unsigned int startup_avalanche_irq(unsigned int irq);
++static void end_avalanche_irq(unsigned int irq);
++void enable_avalanche_irq(unsigned int irq_nr);
++void disable_avalanche_irq(unsigned int irq_nr);
+
-+// Specific for ar7wrd
-+unsigned int tnetd73xx_vbus_freq;
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
++static struct hw_interrupt_type avalanche_irq_type = {
++ "TI AVALANCHE",
++ startup_avalanche_irq,
++ shutdown_avalanche_irq,
++ enable_avalanche_irq,
++ disable_avalanche_irq,
++ mask_and_ack_avalanche_irq,
++ end_avalanche_irq,
++ NULL
++};
+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
++irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
++{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
+
+
-+#ifdef CONFIG_KGDB
-+extern void rs_kgdb_hook(int);
-+int remote_debug = 0;
-+#endif
++unsigned long spurious_count = 0;
+
-+extern struct rtc_ops no_rtc_ops;
++struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
++struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
++struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
++struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
+
-+extern void ar7_reboot_setup(void);
++extern asmlinkage void mipsIRQ(void);
++
++
++/*
++ * The avalanche/MIPS interrupt line numbers are used to represent the
++ * interrupts within the irqaction arrays. The index notation is
++ * is as follows:
++ *
++ * 0-7 MIPS CPU Exceptions (HW/SW)
++ * 8-47 Primary Interrupts (Avalanche)
++ * 48-79 Secondary Interrupts (Avalanche)
++ *
++ */
+
-+extern void ar7_time_init(void);
-+extern void ar7_timer_setup(struct irqaction *irq);
+
-+/* maybe some of this is not needed? */
-+static void ar7_platform_init(void)
++static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
+{
-+ //tnetd73xx_gpio_init();
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL
++};
+
-+ tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
-+ //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+ //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
++static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
++{
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL,
++ NULL, NULL, NULL, NULL
++};
+
-+ //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
-+ //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
++/*
++ This remaps interrupts to exist on other channels than the default
++ channels. essentially we can use the line # as the index for this
++ array
++ */
+
-+ tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
+
-+ tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
++static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
++unsigned long uni_secondary_interrupt = 0;
+
-+#if defined(CONFIG_AR7WRD)
-+ if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
-+ tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
-+ }
-+#endif
++static struct irqaction r4ktimer_action = {
++ NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
++};
+
-+}
++static struct irqaction *irq_action[8] = {
++ NULL, /* SW int 0 */
++ NULL, /* SW int 1 */
++ NULL, /* HW int 0 */
++ NULL,
++ NULL,
++ NULL, /* HW int 3 */
++ NULL, /* HW int 4 */
++ &r4ktimer_action /* HW int 5 */
++};
+
-+const char *get_system_type(void)
++static void end_avalanche_irq(unsigned int irq)
+{
-+ return "Texas Instruments AR7";
++ if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
++ enable_avalanche_irq(irq);
+}
+
-+void __init ar7_setup(void)
++void disable_avalanche_irq(unsigned int irq_nr)
+{
-+#ifdef CONFIG_KGDB
-+ int rs_putDebugChar(char);
-+ char rs_getDebugChar(void);
-+ extern int (*generic_putDebugChar)(char);
-+ extern char (*generic_getDebugChar)(void);
-+#endif
-+ char *argptr;
++ unsigned long flags;
++ unsigned long chan_nr=0;
++ unsigned long int_bit=0;
+
-+#ifdef CONFIG_SERIAL_CONSOLE
-+ argptr = prom_getcmdline();
-+ if ((argptr = strstr(argptr, "console=")) == NULL) {
-+ argptr = prom_getcmdline();
-+ strcat(argptr, " console=ttyS0,38400");
++ if(irq_nr >= AVALANCHE_INT_END)
++ {
++ printk("whee, invalid irq_nr %d\n", irq_nr);
++ panic("IRQ, you lose...");
+ }
-+#endif
+
-+#ifdef CONFIG_KGDB
-+ argptr = prom_getcmdline();
-+ if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
-+ int line;
-+ argptr += strlen("kgdb=ttyS");
-+ if (*argptr != '0' && *argptr != '1')
-+ printk("KGDB: Uknown serial line /dev/ttyS%c, "
-+ "falling back to /dev/ttyS1\n", *argptr);
-+ line = *argptr == '0' ? 0 : 1;
-+ printk("KGDB: Using serial line /dev/ttyS%d for session\n",
-+ line ? 1 : 0);
++ save_and_cli(flags);
+
-+ rs_kgdb_hook(line);
-+ generic_putDebugChar = rs_putDebugChar;
-+ generic_getDebugChar = rs_getDebugChar;
+
-+ prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
-+ "please connect your debugger\n", line ? 1 : 0);
++ if(irq_nr < MIPS_EXCEPTION_OFFSET)
++ {
++ /* disable mips exception */
+
-+ remote_debug = 1;
-+ /* Breakpoints are in init_IRQ() */
++ int_bit = read_c0_status() & ~(1 << (8+irq_nr));
++ change_c0_status(ST0_IM,int_bit);
++ restore_flags(flags);
++ return;
+ }
-+#endif
+
-+ argptr = prom_getcmdline();
-+ if ((argptr = strstr(argptr, "nofpu")) != NULL)
-+ cpu_data[0].options &= ~MIPS_CPU_FPU;
++ /* irq_nr represents the line number for the interrupt. We must
++ * disable the channel number associated with that line number.
++ */
+
-+ rtc_ops = &no_rtc_ops;
++ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
++ chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
++ else
++ chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
+
-+ ar7_platform_init();
++ /* disable the interrupt channel bit */
+
-+ ar7_reboot_setup();
++ /* primary interrupt #'s 0-31 */
+
-+ board_time_init = ar7_time_init;
-+ board_timer_setup = ar7_timer_setup;
++ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
++ avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
++
++ /* primary interrupt #'s 32-39 */
++
++ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
++ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
++ avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++
++ else /* secondary interrupt #'s 0-31 */
++ avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
++
++ restore_flags(flags);
+}
-diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.dev/arch/mips/ar7/time.c
---- linux-2.4.30/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/time.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,125 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Setting up the clock on the MIPS boards.
-+ *
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/sched.h>
-+#include <linux/spinlock.h>
-+
-+#include <asm/mipsregs.h>
-+#include <asm/ptrace.h>
-+#include <asm/hardirq.h>
-+#include <asm/div64.h>
-+
-+#include <linux/interrupt.h>
-+#include <linux/mc146818rtc.h>
-+#include <linux/timex.h>
-+
-+#include <asm/mips-boards/generic.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
-+
-+extern asmlinkage void mipsIRQ(void);
+
-+static unsigned long r4k_offset; /* Amount to increment compare reg each time */
-+static unsigned long r4k_cur; /* What counter should be at next timer irq */
++void enable_avalanche_irq(unsigned int irq_nr)
++{
++ unsigned long flags;
++ unsigned long chan_nr=0;
++ unsigned long int_bit=0;
+
-+#define MIPS_CPU_TIMER_IRQ 7
-+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
++ if(irq_nr > AVALANCHE_INT_END) {
++ printk("whee, invalid irq_nr %d\n", irq_nr);
++ panic("IRQ, you lose...");
++ }
+
-+static inline void ack_r4ktimer(unsigned long newval)
-+{
-+ write_c0_compare(newval);
-+}
++ save_and_cli(flags);
+
-+void ar7_timer_interrupt(struct pt_regs *regs)
-+{
-+ int cpu = smp_processor_id();
+
-+ irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
++ if(irq_nr < MIPS_EXCEPTION_OFFSET)
++ {
++ /* Enable MIPS exceptions */
++ int_bit = read_c0_status();
++ change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
++ restore_flags(flags);
++ return;
++ }
+
-+ if (r4k_offset == 0)
-+ goto null;
++ /* irq_nr represents the line number for the interrupt. We must
++ * disable the channel number associated with that line number.
++ */
+
-+ do {
-+ kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
-+ do_timer(regs);
-+ r4k_cur += r4k_offset;
-+ ack_r4ktimer(r4k_cur);
++ if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
++ chan_nr = AVINTNUM(irq_nr);
++ else
++ chan_nr = line_to_channel[AVINTNUM(irq_nr)];
+
-+ } while (((unsigned long)read_c0_count()
-+ - r4k_cur) < 0x7fffffff);
++ /* enable the interrupt channel bit */
+
-+ irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
++ /* primary interrupt #'s 0-31 */
++ if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
++ avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
+
-+ if (softirq_pending(cpu))
-+ do_softirq();
++ /* primary interrupt #'s 32 throuth 39 */
++ else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
++ (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
++ avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
+
-+ return;
++ else /* secondary interrupt #'s 0-31 */
++ avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
+
-+null:
-+ ack_r4ktimer(0);
++ restore_flags(flags);
+}
+
-+/*
-+ * Figure out the r4k offset, the amount to increment the compare
-+ * register for each time tick.
-+ */
-+static unsigned long __init cal_r4koff(void)
++static unsigned int startup_avalanche_irq(unsigned int irq)
+{
-+ return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
++ enable_avalanche_irq(irq);
++ return 0; /* never anything pending */
+}
+
-+void __init ar7_time_init(void)
++
++int get_irq_list(char *buf)
+{
-+ unsigned long flags;
-+ unsigned int est_freq;
++ int i, len = 0;
++ int num = 0;
++ struct irqaction *action;
+
-+ set_except_vector(0, mipsIRQ);
-+ write_c0_count(0);
++ for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
++ {
++ action = irq_action[i];
++ if (!action)
++ continue;
++ len += sprintf(buf+len, "%2d: %8d %c %s",
++ num, kstat.irqs[0][num],
++ (action->flags & SA_INTERRUPT) ? '+' : ' ',
++ action->name);
++ for (action=action->next; action; action = action->next) {
++ len += sprintf(buf+len, ",%s %s",
++ (action->flags & SA_INTERRUPT) ? " +" : "",
++ action->name);
++ }
++ len += sprintf(buf+len, " [MIPS interrupt]\n");
++ }
+
-+ printk("calculating r4koff... ");
-+ r4k_offset = cal_r4koff();
-+ printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+
-+ est_freq = 2*r4k_offset*HZ;
-+ est_freq += 5000; /* round */
-+ est_freq -= est_freq%10000;
-+ printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
-+ (est_freq%1000000)*100/1000000);
-+}
++ for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
++ {
++ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
++ action = hw0_irq_action_primary[i];
++ else
++ action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
++ if (!action)
++ continue;
++ len += sprintf(buf+len, "%2d: %8d %c %s",
++ num, kstat.irqs[0][ LNXINTNUM(i) ],
++ (action->flags & SA_INTERRUPT) ? '+' : ' ',
++ action->name);
+
-+void __init ar7_timer_setup(struct irqaction *irq)
-+{
-+ /* we are using the cpu counter for timer interrupts */
-+ irq->handler = no_action; /* we use our own handler */
-+ setup_irq(MIPS_CPU_TIMER_IRQ, irq);
++ for (action=action->next; action; action = action->next)
++ {
++ len += sprintf(buf+len, ",%s %s",
++ (action->flags & SA_INTERRUPT) ? " +" : "",
++ action->name);
++ }
+
-+ r4k_cur = (read_c0_count() + r4k_offset);
-+ write_c0_compare(r4k_cur);
-+ set_c0_status(ALLINTS);
-+}
-diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c
---- linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,924 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Misc modules API Source
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx_misc.c
-+ *
-+ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
-+ * FSER Modules API
-+ * As per TNETD73xx specifications
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - Sharath Kumar PSP TII
-+ * 14 Feb 03 - Anant Gole PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
++ if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
++ len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
++ else
++ len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
+
-+#define LITTLE_ENDIAN
-+#define _LINK_KSEG0_
++ }
+
-+#include <linux/types.h>
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
++ return len;
++}
+
-+/* TNETD73XX Revision */
-+u32 tnetd73xx_get_revision(void)
++int request_irq(unsigned int irq,
++ void (*handler)(int, void *, struct pt_regs *),
++ unsigned long irqflags,
++ const char * devname,
++ void *dev_id)
+{
-+ /* Read Chip revision register - This register is from GPIO module */
-+ return ( (u32) REG32_DATA(TNETD73XX_CVR));
-+}
++ struct irqaction *action;
+
-+/*****************************************************************************
-+ * Reset Control Module
-+ *****************************************************************************/
++ if (irq > AVALANCHE_INT_END)
++ return -EINVAL;
++ if (!handler)
++ return -EINVAL;
+
++ action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
++ if(!action)
++ return -ENOMEM;
+
-+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
-+{
-+ u32 reset_status;
++ action->handler = handler;
++ action->flags = irqflags;
++ action->mask = 0;
++ action->name = devname;
++ irq_desc_ti[irq].action = action;
++ action->dev_id = dev_id;
+
-+ /* read current reset register */
-+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++ action->next = 0;
+
-+ if (reset_ctrl == OUT_OF_RESET)
-+ {
-+ /* bring module out of reset */
-+ reset_status |= (1 << reset_module);
-+ }
-+ else
++ if(irq < MIPS_EXCEPTION_OFFSET)
+ {
-+ /* put module in reset */
-+ reset_status &= (~(1 << reset_module));
++ irq_action[irq] = action;
++ enable_avalanche_irq(irq);
++ return 0;
+ }
+
-+ /* write to the reset register */
-+ REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+}
-+
-+
-+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
-+{
-+ u32 reset_status;
++ if(irq < AVALANCHE_INT_END_PRIMARY)
++ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
++ else
++ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
+
-+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+ return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
-+}
++ enable_avalanche_irq(irq);
+
-+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
-+{
-+ REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
++ return 0;
+}
+
-+#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
-+
-+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
++void free_irq(unsigned int irq, void *dev_id)
+{
-+ u32 sys_reset_status;
-+
-+ REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
-+
-+ return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
-+}
++ struct irqaction *action;
+
++ if (irq > AVALANCHE_INT_END) {
++ printk("Trying to free IRQ%d\n",irq);
++ return;
++ }
+
-+/*****************************************************************************
-+ * Power Control Module
-+ *****************************************************************************/
-+#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
-+#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
-+
-+
-+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ if (power_ctrl == POWER_CTRL_POWER_DOWN)
-+ {
-+ /* power down the module */
-+ power_status |= (1 << power_module);
-+ }
-+ else
++ if(irq < MIPS_EXCEPTION_OFFSET)
+ {
-+ /* power on the module */
-+ power_status &= (~(1 << power_module));
++ action = irq_action[irq];
++ irq_action[irq] = NULL;
++ irq_desc_ti[irq].action = NULL;
++ disable_avalanche_irq(irq);
++ kfree(action);
++ return;
+ }
+
-+ /* write to the reset register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
-+
-+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++ if(irq < AVALANCHE_INT_END_PRIMARY) {
++ action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
++ hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
++ irq_desc_ti[irq].action = NULL;
++ }
++ else {
++ action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
++ hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
++ irq_desc_ti[irq].action = NULL;
++ }
+
-+ return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
++ disable_avalanche_irq(irq);
++ kfree(action);
+}
+
-+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
-+{
-+ u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
-+ power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
-+
-+ /* write to power down control register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
++#ifdef CONFIG_KGDB
++extern void breakpoint(void);
++extern int remote_debug;
++#endif
+
-+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
++//void init_IRQ(void) __init;
++void __init init_IRQ(void)
+{
-+ u32 power_status;
++ int i;
+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++ avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
++ avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
++ avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
++ avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
+
-+ power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
-+ power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
++ /* Disable interrupts and clear pending
++ */
+
-+ return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
-+}
++ avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
++ avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
++ avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
++ avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
++ avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
++ avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
+
+
-+/*****************************************************************************
-+ * Wakeup Control
-+ *****************************************************************************/
++ /* Channel to line mapping, Line to Channel mapping */
+
-+#define TNETD73XX_WAKEUP_POLARITY_BIT 16
++ for(i = 0; i < 40; i++)
++ avalanche_int_set(i,i);
+
-+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
-+ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
-+ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
-+{
-+ u32 wakeup_status;
++ /* Now safe to set the exception vector. */
++ set_except_vector(0, mipsIRQ);
+
-+ /* read the wakeup control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++ /* Setup the IRQ description array. These will be mapped
++ * as flat interrupts numbers. The mapping is as follows
++ *
++ * 0-7 MIPS CPU Exceptions (HW/SW)
++ * 8-46 Primary Interrupts (Avalanche)
++ * 47-78 Secondary Interrupts (Avalanche)
++ */
+
-+ /* enable/disable */
-+ if (wakeup_ctrl == WAKEUP_ENABLED)
-+ {
-+ /* enable wakeup */
-+ wakeup_status |= wakeup_int;
-+ }
-+ else
++ for (i = 0; i <= AVALANCHE_INT_END; i++)
+ {
-+ /* disable wakeup */
-+ wakeup_status &= (~wakeup_int);
++ irq_desc_ti[i].status = IRQ_DISABLED;
++ irq_desc_ti[i].action = 0;
++ irq_desc_ti[i].depth = 1;
++ irq_desc_ti[i].handler = &avalanche_irq_type;
+ }
+
-+ /* set polarity */
-+ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
-+ {
-+ wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+ }
-+ else
++#ifdef CONFIG_KGDB
++ if (remote_debug)
+ {
-+ wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
++ set_debug_traps();
++ breakpoint();
+ }
-+
-+ /* write the wakeup control register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++#endif
+}
+
+
-+/*****************************************************************************
-+ * FSER Control
-+ *****************************************************************************/
-+
-+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
++void avalanche_hw0_irqdispatch(struct pt_regs *regs)
+{
-+ REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
-+}
-+
-+/*****************************************************************************
-+ * Clock Control
-+ *****************************************************************************/
++ struct irqaction *action;
++ int irq, cpu = smp_processor_id();
++ unsigned long int_line_number,status;
++ int i,secondary = 0;
++ int chan_nr=0;
+
-+#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
-+#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
-+#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
-+#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
++ int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
++ chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
+
-+#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
-+#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
+
-+#define CLKC_PRE_DIVIDER 0x0000001F
-+#define CLKC_POST_DIVIDER 0x001F0000
++ if(chan_nr < 32)
++ {
++ if( chan_nr != uni_secondary_interrupt)
++ avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
+
-+#define CLKC_PLL_STATUS 0x1
-+#define CLKC_PLL_FACTOR 0x0000F000
++ }
+
-+#define BOOTCR_PLL_BYPASS (1 << 5)
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
++ if((chan_nr < 40) && (chan_nr > 31))
++ {
++ avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
++ }
+
-+#define MIPS_PLL_SELECT 0x00030000
-+#define SYSTEM_PLL_SELECT 0x0000C000
-+#define USB_PLL_SELECT 0x000C0000
-+#define ADSLSS_PLL_SELECT 0x00C00000
+
-+#define MIPS_AFECLKI_SELECT 0x00000000
-+#define MIPS_REFCLKI_SELECT 0x00010000
-+#define MIPS_XTAL3IN_SELECT 0x00020000
++ /* If the Priority Interrupt Index Register returns 40 then no
++ * interrupts are pending
++ */
+
-+#define SYSTEM_AFECLKI_SELECT 0x00000000
-+#define SYSTEM_REFCLKI_SELECT 0x00004000
-+#define SYSTEM_XTAL3IN_SELECT 0x00008000
-+#define SYSTEM_MIPSPLL_SELECT 0x0000C000
++ if(chan_nr == 40)
++ return;
+
-+#define USB_SYSPLL_SELECT 0x00000000
-+#define USB_REFCLKI_SELECT 0x00040000
-+#define USB_XTAL3IN_SELECT 0x00080000
-+#define USB_MIPSPLL_SELECT 0x000C0000
++ if(chan_nr == uni_secondary_interrupt)
++ {
++ status = avalanche_hw0_ecregs->exsr;
++ for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
++ {
++ if (status & 1<<i)
++ {
++ /* clear secondary interrupt */
++ avalanche_hw0_ecregs->excr = 1 << i;
++ break;
++ }
++ }
++ irq = i;
++ secondary = 1;
+
-+#define ADSLSS_AFECLKI_SELECT 0x00000000
-+#define ADSLSS_REFCLKI_SELECT 0x00400000
-+#define ADSLSS_XTAL3IN_SELECT 0x00800000
-+#define ADSLSS_MIPSPLL_SELECT 0x00C00000
++ /* clear the universal secondary interrupt */
++ avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
+
-+#define SYS_MAX CLK_MHZ(150)
-+#define SYS_MIN CLK_MHZ(1)
++ }
++ else
++ irq = chan_nr;
+
-+#define MIPS_SYNC_MAX SYS_MAX
-+#define MIPS_ASYNC_MAX CLK_MHZ(160)
-+#define MIPS_MIN CLK_MHZ(1)
++ /* Suraj Add code to clear secondary interrupt */
+
-+#define USB_MAX CLK_MHZ(100)
-+#define USB_MIN CLK_MHZ(1)
++ if(secondary)
++ action = hw0_irq_action_secondary[irq];
++ else
++ action = hw0_irq_action_primary[irq];
+
-+#define ADSL_MAX CLK_MHZ(180)
-+#define ADSL_MIN CLK_MHZ(1)
++ /* if action == NULL, then we don't have a handler for the irq */
+
-+#define PLL_MUL_MAXFACTOR 15
-+#define MAX_DIV_VALUE 32
-+#define MIN_DIV_VALUE 1
++ if ( action == NULL ) {
++ printk("No handler for hw0 irq: %i\n", irq);
++ return;
++ }
+
-+#define MIN_PLL_INP_FREQ CLK_MHZ(8)
-+#define MAX_PLL_INP_FREQ CLK_MHZ(100)
++ irq_enter(cpu,irq);
++ if(secondary)
++ {
++ kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
++ action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
++ }
++ else
++ {
++ kstat.irqs[0][irq + 8]++;
++ action->handler(LNXINTNUM(irq), action->dev_id, regs);
++ }
+
-+#define DIVIDER_LOCK_TIME 10100
-+#define PLL_LOCK_TIME 10100 * 75
++ irq_exit(cpu,irq);
+
++ if(softirq_pending(cpu))
++ do_softirq();
+
++ return;
++}
+
-+ /****************************************************************************
-+ * DATA PURPOSE: PRIVATE Variables
-+ **************************************************************************/
-+ static u32 *clk_src[4];
-+ static u32 mips_pll_out;
-+ static u32 sys_pll_out;
-+ static u32 afeclk_inp;
-+ static u32 refclk_inp;
-+ static u32 xtal_inp;
-+ static u32 present_min;
-+ static u32 present_max;
-+
-+ /* Forward References */
-+ static u32 find_gcd(u32 min, u32 max);
-+ static u32 compute_prediv( u32 divider, u32 min, u32 max);
-+ static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
-+ static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
-+ static void find_approx(u32 *,u32 *,u32);
-+
-+ /****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_init
-+ ****************************************************************************
-+ * Description: The routine initializes the internal variables depending on
-+ * on the sources selected for different clocks.
-+ ***************************************************************************/
-+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
++void avalanche_int_set(int channel, int line)
+{
-+
-+ u32 choice;
-+
-+ afeclk_inp = afeclk;
-+ refclk_inp = refclk;
-+ xtal_inp = xtal3in;
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
-+ switch(choice)
++ switch(channel)
+ {
-+ case MIPS_AFECLKI_SELECT:
-+ clk_src[CLKC_MIPS] = &afeclk_inp;
++ case(0):
++ avalanche_hw0_chregs->cintnr0 = line;
+ break;
-+
-+ case MIPS_REFCLKI_SELECT:
-+ clk_src[CLKC_MIPS] = &refclk_inp;
++ case(1):
++ avalanche_hw0_chregs->cintnr1 = line;
+ break;
-+
-+ case MIPS_XTAL3IN_SELECT:
-+ clk_src[CLKC_MIPS] = &xtal_inp;
++ case(2):
++ avalanche_hw0_chregs->cintnr2 = line;
+ break;
-+
-+ default :
-+ clk_src[CLKC_MIPS] = 0;
-+
-+ }
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case SYSTEM_AFECLKI_SELECT:
-+ clk_src[CLKC_SYS] = &afeclk_inp;
++ case(3):
++ avalanche_hw0_chregs->cintnr3 = line;
+ break;
-+
-+ case SYSTEM_REFCLKI_SELECT:
-+ clk_src[CLKC_SYS] = &refclk_inp;
++ case(4):
++ avalanche_hw0_chregs->cintnr4 = line;
+ break;
-+
-+ case SYSTEM_XTAL3IN_SELECT:
-+ clk_src[CLKC_SYS] = &xtal_inp;
++ case(5):
++ avalanche_hw0_chregs->cintnr5 = line;
+ break;
-+
-+ case SYSTEM_MIPSPLL_SELECT:
-+ clk_src[CLKC_SYS] = &mips_pll_out;
++ case(6):
++ avalanche_hw0_chregs->cintnr6 = line;
+ break;
-+
-+ default :
-+ clk_src[CLKC_SYS] = 0;
-+
-+ }
-+
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case ADSLSS_AFECLKI_SELECT:
-+ clk_src[CLKC_ADSLSS] = &afeclk_inp;
++ case(7):
++ avalanche_hw0_chregs->cintnr7 = line;
+ break;
-+
-+ case ADSLSS_REFCLKI_SELECT:
-+ clk_src[CLKC_ADSLSS] = &refclk_inp;
++ case(8):
++ avalanche_hw0_chregs->cintnr8 = line;
+ break;
-+
-+ case ADSLSS_XTAL3IN_SELECT:
-+ clk_src[CLKC_ADSLSS] = &xtal_inp;
++ case(9):
++ avalanche_hw0_chregs->cintnr9 = line;
+ break;
-+
-+ case ADSLSS_MIPSPLL_SELECT:
-+ clk_src[CLKC_ADSLSS] = &mips_pll_out;
++ case(10):
++ avalanche_hw0_chregs->cintnr10 = line;
+ break;
-+
-+ default :
-+ clk_src[CLKC_ADSLSS] = 0;
-+
-+ }
-+
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case USB_SYSPLL_SELECT:
-+ clk_src[CLKC_USB] = &sys_pll_out ;
++ case(11):
++ avalanche_hw0_chregs->cintnr11 = line;
+ break;
-+
-+ case USB_REFCLKI_SELECT:
-+ clk_src[CLKC_USB] = &refclk_inp;
++ case(12):
++ avalanche_hw0_chregs->cintnr12 = line;
+ break;
-+
-+ case USB_XTAL3IN_SELECT:
-+ clk_src[CLKC_USB] = &xtal_inp;
++ case(13):
++ avalanche_hw0_chregs->cintnr13 = line;
+ break;
-+
-+ case USB_MIPSPLL_SELECT:
-+ clk_src[CLKC_USB] = &mips_pll_out;
++ case(14):
++ avalanche_hw0_chregs->cintnr14 = line;
+ break;
-+
-+ default :
-+ clk_src[CLKC_USB] = 0;
-+
-+ }
-+}
-+
-+
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_set_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to set the output_frequency of the
-+ * selected clock(using clk_id) to the required value given
-+ * by the variable output_freq.
-+ ***************************************************************************/
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id,
-+ u32 output_freq
-+ )
-+{
-+ u32 base_freq;
-+ u32 multiplier;
-+ u32 divider;
-+ u32 min_prediv;
-+ u32 max_prediv;
-+ u32 prediv;
-+ u32 postdiv;
-+ u32 temp;
-+
-+ /* check if PLLs are bypassed*/
-+ if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /*check if the requested output_frequency is in valid range*/
-+ switch( clk_id )
-+ {
-+ case CLKC_SYS:
-+ if( output_freq < SYS_MIN || output_freq > SYS_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = SYS_MIN;
-+ present_max = SYS_MAX;
++ case(15):
++ avalanche_hw0_chregs->cintnr15 = line;
+ break;
-+
-+ case CLKC_MIPS:
-+ if((output_freq < MIPS_MIN) ||
-+ (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = MIPS_MIN;
-+ present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
++ case(16):
++ avalanche_hw0_chregs->cintnr16 = line;
+ break;
-+
-+ case CLKC_USB:
-+ if( output_freq < USB_MIN || output_freq > USB_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = USB_MIN;
-+ present_max = USB_MAX;
++ case(17):
++ avalanche_hw0_chregs->cintnr17 = line;
+ break;
-+
-+ case CLKC_ADSLSS:
-+ if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = ADSL_MIN;
-+ present_max = ADSL_MAX;
++ case(18):
++ avalanche_hw0_chregs->cintnr18 = line;
++ break;
++ case(19):
++ avalanche_hw0_chregs->cintnr19 = line;
++ break;
++ case(20):
++ avalanche_hw0_chregs->cintnr20 = line;
++ break;
++ case(21):
++ avalanche_hw0_chregs->cintnr21 = line;
++ break;
++ case(22):
++ avalanche_hw0_chregs->cintnr22 = line;
++ break;
++ case(23):
++ avalanche_hw0_chregs->cintnr23 = line;
++ break;
++ case(24):
++ avalanche_hw0_chregs->cintnr24 = line;
++ break;
++ case(25):
++ avalanche_hw0_chregs->cintnr25 = line;
++ break;
++ case(26):
++ avalanche_hw0_chregs->cintnr26 = line;
++ break;
++ case(27):
++ avalanche_hw0_chregs->cintnr27 = line;
++ break;
++ case(28):
++ avalanche_hw0_chregs->cintnr28 = line;
++ break;
++ case(29):
++ avalanche_hw0_chregs->cintnr29 = line;
++ break;
++ case(30):
++ avalanche_hw0_chregs->cintnr30 = line;
++ break;
++ case(31):
++ avalanche_hw0_chregs->cintnr31 = line;
++ break;
++ case(32):
++ avalanche_hw0_chregs->cintnr32 = line;
++ break;
++ case(33):
++ avalanche_hw0_chregs->cintnr33 = line;
++ break;
++ case(34):
++ avalanche_hw0_chregs->cintnr34 = line;
++ break;
++ case(35):
++ avalanche_hw0_chregs->cintnr35 = line;
++ break;
++ case(36):
++ avalanche_hw0_chregs->cintnr36 = line;
++ break;
++ case(37):
++ avalanche_hw0_chregs->cintnr37 = line;
++ break;
++ case(38):
++ avalanche_hw0_chregs->cintnr38 = line;
++ break;
++ case(39):
++ avalanche_hw0_chregs->cintnr39 = line;
+ break;
++ default:
++ printk("Error: Unknown Avalanche interrupt channel\n");
+ }
+
++ line_to_channel[line] = channel; /* Suraj check */
+
-+ base_freq = get_base_frequency(clk_id);
++ if (channel == UNIFIED_SECONDARY_INTERRUPT)
++ uni_secondary_interrupt = line;
+
++}
+
-+ /* check for minimum base frequency value */
-+ if( base_freq < MIN_PLL_INP_FREQ)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
+
-+ get_val(output_freq, base_freq, &multiplier, ÷r);
++#define AVALANCHE_MAX_PACING_BLK 3
++#define AVALANCHE_PACING_LOW_VAL 2
++#define AVALANCHE_PACING_HIGH_VAL 63
+
-+ /* check multiplier range */
-+ if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
++ unsigned int pace_value)
++{
++ unsigned int blk_offset;
++ unsigned long flags;
+
-+ /* check divider value */
-+ if( divider == 0 )
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
++ if(irq_nr < MIPS_EXCEPTION_OFFSET &&
++ irq_nr >= AVALANCHE_INT_END_PRIMARY)
++ return (0);
+
-+ /*compute minimum and maximum predivider values */
-+ min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
-+ max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
++ if(blk_num > AVALANCHE_MAX_PACING_BLK)
++ return(-1);
+
-+ /*adjust the value of divider so that it not less than minimum predivider value*/
-+ if (divider < min_prediv)
-+ {
-+ temp = CEIL(min_prediv, divider);
-+ if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
-+ {
-+ return TNETD73XX_ERR_ERROR ;
-+ }
-+ else
-+ {
-+ multiplier = temp * multiplier;
-+ divider = min_prediv;
-+ }
++ if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
++ pace_value < AVALANCHE_PACING_LOW_VAL)
++ return(-1);
+
-+ }
++ blk_offset = blk_num*8;
+
-+ /* compute predivider and postdivider values */
-+ prediv = compute_prediv (divider, min_prediv, max_prediv);
-+ postdiv = CEIL(divider,prediv);
++ save_and_cli(flags);
+
-+ /*return fail if postdivider value falls out of range */
-+ if(postdiv > MAX_DIV_VALUE)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
++ /* disable the interrupt pacing, if enabled previously */
++ avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
+
++ /* clear the pacing map */
++ avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
+
-+ /*write predivider and postdivider values*/
-+ /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+ REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
++ /* setup the new values */
++ avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
++ avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
+
-+ /*wait for divider output to stabilise*/
-+ for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
++ restore_flags(flags);
+
-+ /*write to PLL clock register*/
++ return(0);
++}
+diff -urN kernel-base/arch/mips/ar7/Makefile kernel-current/arch/mips/ar7/Makefile
+--- kernel-base/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/Makefile 2005-07-10 08:23:55.081408136 +0200
+@@ -0,0 +1,29 @@
++# $Id$
++# Copyright (C) $Date$ $Author$
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
-+ if(clk_id == CLKC_SYS)
-+ {
-+ /* but before writing put DRAM to hold mode */
-+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
-+ }
-+ /*Bring PLL into div mode */
-+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
++.S.s:
++ $(CPP) $(AFLAGS) $< -o $*.s
+
-+ /*compute the word to be written to PLLCR
-+ *corresponding to multiplier value
-+ */
-+ multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
++.S.o:
++ $(CC) $(AFLAGS) -c $< -o $*.o
++
++O_TARGET := ar7.o
+
-+ /* wait till PLL enters div mode */
-+ while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+ /*nothing*/;
++export-objs := init.o irq.o
++obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
+
-+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
++include $(TOPDIR)/Rules.make
+diff -urN kernel-base/arch/mips/ar7/memory.c kernel-current/arch/mips/ar7/memory.c
+--- kernel-base/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/memory.c 2005-07-10 06:40:39.586266560 +0200
+@@ -0,0 +1,130 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * PROM library functions for acquiring/using memory descriptors given to
++ * us from the YAMON.
++ *
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/bootmem.h>
+
-+ while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+ /*nothing*/;
++#include <asm/bootinfo.h>
++#include <asm/page.h>
++#include <asm/mips-boards/prom.h>
++#include <asm/ar7/ar7.h>
+
++enum yamon_memtypes {
++ yamon_dontuse,
++ yamon_prom,
++ yamon_free,
++};
++struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
+
-+ /*wait for External pll to lock*/
-+ for(temp =0; temp < PLL_LOCK_TIME; temp++);
++/* References to section boundaries */
++extern char _end;
+
-+ if(clk_id == CLKC_SYS)
-+ {
-+ /* Bring DRAM out of hold */
-+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
-+ }
++#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
+
-+ return TNETD73XX_ERR_OK ;
-+}
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_get_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to get the output_frequency of the
-+ * selected clock( clk_id)
-+ ***************************************************************************/
-+u32 tnetd73xx_clkc_get_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id
-+ )
++struct prom_pmemblock * __init prom_getmdesc(void)
+{
++ char *memsize_str;
++ unsigned int memsize;
+
-+ u32 clk_ctrl_register;
-+ u32 clk_pll_setting;
-+ u32 clk_predivider;
-+ u32 clk_postdivider;
-+ u16 pll_factor;
-+ u32 base_freq;
-+ u32 divider;
++ memsize_str = prom_getenv("memsize");
++ if (!memsize_str) {
++ memsize = 0x02000000;
++ } else {
++ memsize = simple_strtol(memsize_str, NULL, 0);
++ }
+
-+ base_freq = get_base_frequency(clk_id);
++ memset(mdesc, 0, sizeof(mdesc));
+
-+ clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
++ mdesc[0].type = yamon_dontuse;
++ mdesc[0].base = 0x00000000;
++ mdesc[0].size = CONFIG_AR7_MEMORY;
+
-+ /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+ clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
-+ clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
++ mdesc[1].type = yamon_prom;
++ mdesc[1].base = CONFIG_AR7_MEMORY;
++ mdesc[1].size = 0x00020000;
+
-+ divider = clk_predivider * clk_postdivider;
++ mdesc[2].type = yamon_free;
++ mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
++ mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
+
++ return &mdesc[0];
++}
+
-+ if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
-+ {
-+ return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
++static int __init prom_memtype_classify (unsigned int type)
++{
++ switch (type) {
++ case yamon_free:
++ return BOOT_MEM_RAM;
++ case yamon_prom:
++ return BOOT_MEM_ROM_DATA;
++ default:
++ return BOOT_MEM_RESERVED;
+ }
++}
+
++void __init prom_meminit(void)
++{
++ struct prom_pmemblock *p;
+
-+ else
-+ {
-+ /* return the current clock speed based upon the PLL setting */
-+ clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
-+
-+ /* Get the PLL multiplication factor */
-+ pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
++ p = prom_getmdesc();
+
-+ /* Check if we're in divide mode or multiply mode */
-+ if((clk_pll_setting & 0x1) == 0)
-+ {
-+ /* We're in divide mode */
-+ if(pll_factor < 0x10)
-+ return (CEIL(base_freq >> 1, divider));
-+ else
-+ return (CEIL(base_freq >> 2, divider));
-+ }
-+
-+ else /* We're in PLL mode */
-+ {
-+ /* See if PLLNDIV & PLLDIV are set */
-+ if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
-+ {
-+ if(clk_pll_setting & 0x1000)
-+ {
-+ /* clk = base_freq * k/2 */
-+ return(CEIL((base_freq * pll_factor) >> 1, divider));
-+ }
-+ else
-+ {
-+ /* clk = base_freq * (k-1) / 4)*/
-+ return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
-+ }
-+ }
-+ else
-+ {
-+ if(pll_factor < 0x10)
-+ {
-+ /* clk = base_freq * k */
-+ return(CEIL(base_freq * pll_factor, divider));
-+ }
++ while (p->size) {
++ long type;
++ unsigned long base, size;
+
-+ else
-+ {
-+ /* clk = base_freq */
-+ return(CEIL(base_freq, divider));
-+ }
-+ }
-+ }
-+ return(0); /* Should never reach here */
++ type = prom_memtype_classify (p->type);
++ base = p->base;
++ size = p->size;
+
++ add_memory_region(base, size, type);
++ p++;
+ }
-+
+}
+
-+
-+/* local helper functions */
-+
-+/****************************************************************************
-+ * FUNCTION: get_base_frequency
-+ ****************************************************************************
-+ * Description: The above routine is called to get base frequency of the clocks.
-+ ***************************************************************************/
-+
-+static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
++void __init prom_free_prom_memory (void)
+{
-+ /* update the current MIPs PLL output value, if the required
-+ * source is MIPS PLL
-+ */
-+ if ( clk_src[clk_id] == &mips_pll_out)
-+ {
-+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
-+ }
++ int i;
++ unsigned long freed = 0;
++ unsigned long addr;
+
++ for (i = 0; i < boot_mem_map.nr_map; i++) {
++ if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
++ continue;
+
-+ /* update the current System PLL output value, if the required
-+ * source is system PLL
-+ */
-+ if ( clk_src[clk_id] == &sys_pll_out)
-+ {
-+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
++ addr = boot_mem_map.map[i].addr;
++ while (addr < boot_mem_map.map[i].addr
++ + boot_mem_map.map[i].size) {
++ ClearPageReserved(virt_to_page(__va(addr)));
++ set_page_count(virt_to_page(__va(addr)), 1);
++ free_page((unsigned long)__va(addr));
++ addr += PAGE_SIZE;
++ freed += PAGE_SIZE;
++ }
+ }
-+
-+ return (*clk_src[clk_id]);
-+
++ printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
+}
+diff -urN kernel-base/arch/mips/ar7/mipsIRQ.S kernel-current/arch/mips/ar7/mipsIRQ.S
+--- kernel-base/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266408 +0200
+@@ -0,0 +1,120 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Interrupt exception dispatch code.
++ *
++ */
++#include <linux/config.h>
+
++#include <asm/asm.h>
++#include <asm/mipsregs.h>
++#include <asm/regdef.h>
++#include <asm/stackframe.h>
+
++/* A lot of complication here is taken away because:
++ *
++ * 1) We handle one interrupt and return, sitting in a loop and moving across
++ * all the pending IRQ bits in the cause register is _NOT_ the answer, the
++ * common case is one pending IRQ so optimize in that direction.
++ *
++ * 2) We need not check against bits in the status register IRQ mask, that
++ * would make this routine slow as hell.
++ *
++ * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
++ * between like BSD spl() brain-damage.
++ *
++ * Furthermore, the IRQs on the MIPS board look basically (barring software
++ * IRQs which we don't use at all and all external interrupt sources are
++ * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
++ *
++ * MIPS IRQ Source
++ * -------- ------
++ * 0 Software (ignored)
++ * 1 Software (ignored)
++ * 2 Combined hardware interrupt (hw0)
++ * 3 Hardware (ignored)
++ * 4 Hardware (ignored)
++ * 5 Hardware (ignored)
++ * 6 Hardware (ignored)
++ * 7 R4k timer (what we use)
++ *
++ * Note: On the SEAD board thing are a little bit different.
++ * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
++ * wired to UART1.
++ *
++ * We handle the IRQ according to _our_ priority which is:
++ *
++ * Highest ---- R4k Timer
++ * Lowest ---- Combined hardware interrupt
++ *
++ * then we just return, if multiple IRQs are pending then we will just take
++ * another exception, big deal.
++ */
+
-+/****************************************************************************
-+ * FUNCTION: find_gcd
-+ ****************************************************************************
-+ * Description: The above routine is called to find gcd of 2 numbers.
-+ ***************************************************************************/
-+static u32 find_gcd
-+(
-+ u32 min,
-+ u32 max
-+ )
-+{
-+ if (max % min == 0)
-+ {
-+ return min;
-+ }
-+ else
-+ {
-+ return find_gcd(max % min, min);
-+ }
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: compute_prediv
-+ ****************************************************************************
-+ * Description: The above routine is called to compute predivider value
-+ ***************************************************************************/
-+static u32 compute_prediv(u32 divider, u32 min, u32 max)
-+{
-+ u16 prediv;
++.text
++.set noreorder
++.set noat
++ .align 5
++NESTED(mipsIRQ, PT_SIZE, sp)
++ SAVE_ALL
++ CLI
++ .set at
+
-+ /* return the divider itself it it falls within the range of predivider*/
-+ if (min <= divider && divider <= max)
-+ {
-+ return divider;
-+ }
++ mfc0 s0, CP0_CAUSE # get irq bits
+
-+ /* find a value for prediv such that it is a factor of divider */
-+ for (prediv = max; prediv >= min ; prediv--)
-+ {
-+ if ( (divider % prediv) == 0 )
-+ {
-+ return prediv;
-+ }
-+ }
++ /* First we check for r4k counter/timer IRQ. */
++ andi a0, s0, CAUSEF_IP7
++ beq a0, zero, 1f
++ andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
+
-+ /* No such factor exists, return min as prediv */
-+ return min;
-+}
++ /* Wheee, a timer interrupt. */
++ move a0, sp
++ jal ar7_timer_interrupt
++ nop
+
-+/****************************************************************************
-+ * FUNCTION: get_val
-+ ****************************************************************************
-+ * Description: This routine is called to get values of divider and multiplier.
-+ ***************************************************************************/
++ j ret_from_irq
++ nop
+
-+static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
-+{
-+ u32 temp_mul;
-+ u32 temp_div;
-+ u32 gcd;
-+ u32 min_freq;
-+ u32 max_freq;
++ 1:
++ beq a0, zero, 1f # delay slot, check hw3 interrupt
++ nop
+
-+ /* find gcd of base_freq, output_freq */
-+ min_freq = (base_freq < output_freq) ? base_freq : output_freq;
-+ max_freq = (base_freq > output_freq) ? base_freq : output_freq;
-+ gcd = find_gcd(min_freq , max_freq);
++ /* Wheee, combined hardware level zero interrupt. */
++ jal avalanche_hw0_irqdispatch
++ move a0, sp # delay slot
+
-+ if(gcd == 0)
-+ return; /* ERROR */
++ j ret_from_irq
++ nop # delay slot
+
-+ /* compute values of multiplier and divider */
-+ temp_mul = output_freq / gcd;
-+ temp_div = base_freq / gcd;
++ 1:
++ /*
++ * Here by mistake? This is possible, what can happen is that by the
++ * time we take the exception the IRQ pin goes low, so just leave if
++ * this is the case.
++ */
++ move a1,s0
++ PRINT("Got interrupt: c0_cause = %08x\n")
++ mfc0 a1, CP0_EPC
++ PRINT("c0_epc = %08x\n")
+
++ j ret_from_irq
++ nop
++END(mipsIRQ)
+diff -urN kernel-base/arch/mips/ar7/printf.c kernel-current/arch/mips/ar7/printf.c
+--- kernel-base/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/printf.c 2005-07-10 06:40:39.587266408 +0200
+@@ -0,0 +1,54 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Putting things on the screen/serial line using Adam2 facilities.
++ */
+
-+ /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
-+ if( temp_mul > PLL_MUL_MAXFACTOR )
-+ {
-+ if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
-+ return;
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/serial_reg.h>
++#include <linux/spinlock.h>
++#include <asm/io.h>
++#include <asm/serial.h>
++#include <asm/addrspace.h>
++#include <asm/ar7/ar7.h>
+
-+ find_approx(&temp_mul,&temp_div,base_freq);
-+ }
++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
+
-+ *multiplier = temp_mul;
-+ *divider = temp_div;
-+}
++static char ppbuf[1024];
+
-+/****************************************************************************
-+ * FUNCTION: find_approx
-+ ****************************************************************************
-+ * Description: This function gets the approx value of num/denom.
-+ ***************************************************************************/
++void (*prom_print_str)(unsigned int out, char *s, int len);
+
-+static void find_approx(u32 *num,u32 *denom,u32 base_freq)
++void prom_printf(char *fmt, ...) __init;
++void prom_printf(char *fmt, ...)
+{
-+ u32 num1;
-+ u32 denom1;
-+ u32 num2;
-+ u32 denom2;
-+ int32_t closest;
-+ int32_t prev_closest;
-+ u32 temp_num;
-+ u32 temp_denom;
-+ u32 normalize;
-+ u32 gcd;
-+ u32 output_freq;
-+
-+ num1 = *num;
-+ denom1 = *denom;
-+
-+ prev_closest = 0x7fffffff; /* maximum possible value */
-+ num2 = num1;
-+ denom2 = denom1;
-+
-+ /* start with max */
-+ for(temp_num = 15; temp_num >=1; temp_num--)
-+ {
++ va_list args;
++ int len;
++ prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
+
-+ temp_denom = CEIL(temp_num * denom1, num1);
-+ output_freq = (temp_num * base_freq) / temp_denom;
++ va_start(args, fmt);
++ vsprintf(ppbuf, fmt, args);
++ len = strlen(ppbuf);
+
-+ if(temp_denom < 1)
-+ {
-+ break;
-+ }
-+ else
-+ {
-+ normalize = CEIL(num1,temp_num);
-+ closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
-+ if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
-+ {
-+ prev_closest = closest;
-+ num2 = temp_num;
-+ denom2 = temp_denom;
-+ }
++ prom_print_str(1, ppbuf, len);
+
-+ }
++ va_end(args);
++ return;
+
-+ }
++}
+diff -urN kernel-base/arch/mips/ar7/reset.c kernel-current/arch/mips/ar7/reset.c
+--- kernel-base/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/reset.c 2005-07-10 06:40:39.587266408 +0200
+@@ -0,0 +1,54 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Reset the MIPS boards.
++ *
++ */
++#include <linux/config.h>
+
-+ gcd = find_gcd(num2,denom2);
-+ num2 = num2 / gcd;
-+ denom2 = denom2 /gcd;
++#include <asm/reboot.h>
++#include <asm/mips-boards/generic.h>
+
-+ *num = num2;
-+ *denom = denom2;
-+}
++static void ar7_machine_restart(char *command);
++static void ar7_machine_halt(void);
++static void ar7_machine_power_off(void);
+
++static void ar7_machine_restart(char *command)
++{
+
-+/*****************************************************************************
-+ * GPIO Control
-+ *****************************************************************************/
++}
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_init
-+ ***************************************************************************/
-+void tnetd73xx_gpio_init()
++static void ar7_machine_halt(void)
+{
-+ /* Bring module out of reset */
-+ tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+ REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
++
+}
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_ctrl
-+ ***************************************************************************/
-+void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
-+ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
-+ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
++static void ar7_machine_power_off(void)
+{
-+ u32 pin_status;
-+ REG32_READ(TNETD73XX_GPIOENR, pin_status);
-+ if (pin_mode == GPIO_PIN)
-+ {
-+ pin_status |= (1 << gpio_pin);
-+ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
+
-+ /* Set pin direction */
-+ REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
-+ if (pin_direction == GPIO_INPUT_PIN)
-+ {
-+ pin_status |= (1 << gpio_pin);
-+ }
-+ else /* GPIO_OUTPUT_PIN */
-+ {
-+ pin_status &= (~(1 << gpio_pin));
-+ }
-+ REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
-+ }
-+ else /* FUNCTIONAL PIN */
-+ {
-+ pin_status &= (~(1 << gpio_pin));
-+ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
-+ }
++}
+
++void ar7_reboot_setup(void)
++{
++ _machine_restart = ar7_machine_restart;
++ _machine_halt = ar7_machine_halt;
++ _machine_power_off = ar7_machine_power_off;
+}
+diff -urN kernel-base/arch/mips/ar7/setup.c kernel-current/arch/mips/ar7/setup.c
+--- kernel-base/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/setup.c 2005-07-10 06:40:39.588266256 +0200
+@@ -0,0 +1,120 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/mc146818rtc.h>
++#include <linux/ioport.h>
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_out
-+ ***************************************************************************/
-+void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
++#include <asm/cpu.h>
++#include <asm/bootinfo.h>
++#include <asm/irq.h>
++#include <asm/mips-boards/generic.h>
++#include <asm/mips-boards/prom.h>
++
++#include <asm/dma.h>
++#include <asm/time.h>
++#include <asm/traps.h>
++
++#ifdef CONFIG_KGDB
++extern void rs_kgdb_hook(int);
++int remote_debug = 0;
++#endif
++
++extern struct rtc_ops no_rtc_ops;
++
++extern void ar7_reboot_setup(void);
++
++extern void ar7_time_init(void);
++extern void ar7_timer_setup(struct irqaction *irq);
++
++const char *get_system_type(void)
+{
-+ u32 pin_value;
++ return "Texas Instruments AR7";
++}
+
-+ REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
-+ if (value == 1)
-+ {
-+ pin_value |= (1 << gpio_pin);
++void __init ar7_setup(void)
++{
++#ifdef CONFIG_KGDB
++ int rs_putDebugChar(char);
++ char rs_getDebugChar(void);
++ extern int (*generic_putDebugChar)(char);
++ extern char (*generic_getDebugChar)(void);
++#endif
++ char *argptr;
++#ifdef CONFIG_SERIAL_CONSOLE
++ argptr = prom_getcmdline();
++ if ((argptr = strstr(argptr, "console=")) == NULL) {
++ char console[20];
++ char *s;
++ int i = 0;
++
++ s = prom_getenv("modetty0");
++ strcpy(console, "38400");
++
++ if (s != NULL) {
++ while (s[i] >= '0' && s[i] <= '9')
++ i++;
++
++ if (i > 0) {
++ strncpy(console, s, i);
++ console[i] = 0;
++ }
++ }
++
++ argptr = prom_getcmdline();
++ strcat(argptr, " console=ttyS0,");
++ strcat(argptr, console);
+ }
-+ else
-+ {
-+ pin_value &= (~(1 << gpio_pin));
++#endif
++
++#ifdef CONFIG_KGDB
++ argptr = prom_getcmdline();
++ if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
++ int line;
++ argptr += strlen("kgdb=ttyS");
++ if (*argptr != '0' && *argptr != '1')
++ printk("KGDB: Uknown serial line /dev/ttyS%c, "
++ "falling back to /dev/ttyS1\n", *argptr);
++ line = *argptr == '0' ? 0 : 1;
++ printk("KGDB: Using serial line /dev/ttyS%d for session\n",
++ line ? 1 : 0);
++
++ rs_kgdb_hook(line);
++ generic_putDebugChar = rs_putDebugChar;
++ generic_getDebugChar = rs_getDebugChar;
++
++ prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
++ "please connect your debugger\n", line ? 1 : 0);
++
++ remote_debug = 1;
++ /* Breakpoints are in init_IRQ() */
+ }
-+ REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
++#endif
++
++ argptr = prom_getcmdline();
++ if ((argptr = strstr(argptr, "nofpu")) != NULL)
++ cpu_data[0].options &= ~MIPS_CPU_FPU;
++
++ rtc_ops = &no_rtc_ops;
++
++ ar7_reboot_setup();
++
++ board_time_init = ar7_time_init;
++ board_timer_setup = ar7_timer_setup;
+}
+diff -urN kernel-base/arch/mips/ar7/time.c kernel-current/arch/mips/ar7/time.c
+--- kernel-base/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/time.c 2005-07-10 06:40:39.588266256 +0200
+@@ -0,0 +1,125 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Setting up the clock on the MIPS boards.
++ *
++ */
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_in
-+ ***************************************************************************/
-+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
++#include <linux/types.h>
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel_stat.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>
++
++#include <asm/mipsregs.h>
++#include <asm/ptrace.h>
++#include <asm/hardirq.h>
++#include <asm/div64.h>
++
++#include <linux/interrupt.h>
++#include <linux/mc146818rtc.h>
++#include <linux/timex.h>
++
++#include <asm/mips-boards/generic.h>
++#include <asm/mips-boards/prom.h>
++#include <asm/ar7/ar7.h>
++
++extern asmlinkage void mipsIRQ(void);
++
++static unsigned long r4k_offset; /* Amount to increment compare reg each time */
++static unsigned long r4k_cur; /* What counter should be at next timer irq */
++
++#define MIPS_CPU_TIMER_IRQ 7
++#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
++
++static inline void ack_r4ktimer(unsigned long newval)
+{
-+ u32 pin_value;
-+ REG32_READ(TNETD73XX_GPIODINR, pin_value);
-+ return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
++ write_c0_compare(newval);
+}
+
-diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.dev/arch/mips/config-shared.in
---- linux-2.4.30/arch/mips/config-shared.in 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/config-shared.in 2005-06-14 15:36:59.000000000 +0200
-@@ -20,6 +20,15 @@
- mainmenu_option next_comment
- comment 'Machine selection'
- dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
-+dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
-+if [ "$CONFIG_AR7" = "y" ]; then
-+ choice 'Texas Instruments Reference Platform' \
-+ "AR7DB CONFIG_AR7DB \
-+ AR7RD CONFIG_AR7RD \
-+ AR7WRD CONFIG_AR7WRD" AR7DB
-+ int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
-+ hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
-+fi
- dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
- dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
- dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
-@@ -239,6 +248,11 @@
- define_bool CONFIG_NONCOHERENT_IO y
- define_bool CONFIG_PC_KEYB y
- fi
-+if [ "$CONFIG_AR7" = "y" ]; then
-+ define_bool CONFIG_NONCOHERENT_IO y
-+ define_bool CONFIG_SWAP_IO_SPACE y
-+ define_bool CONFIG_AR7_PAGING y
-+fi
- if [ "$CONFIG_CASIO_E55" = "y" ]; then
++void ar7_timer_interrupt(struct pt_regs *regs)
++{
++ int cpu = smp_processor_id();
++
++ irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
++
++ if (r4k_offset == 0)
++ goto null;
++
++ do {
++ kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
++ do_timer(regs);
++ r4k_cur += r4k_offset;
++ ack_r4ktimer(r4k_cur);
++
++ } while (((unsigned long)read_c0_count()
++ - r4k_cur) < 0x7fffffff);
++
++ irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
++
++ if (softirq_pending(cpu))
++ do_softirq();
++
++ return;
++
++null:
++ ack_r4ktimer(0);
++}
++
++/*
++ * Figure out the r4k offset, the amount to increment the compare
++ * register for each time tick.
++ */
++static unsigned long __init cal_r4koff(void)
++{
++ return ((CONFIG_AR7_CPU_FREQUENCY*500000)/HZ);
++}
++
++void __init ar7_time_init(void)
++{
++ unsigned long flags;
++ unsigned int est_freq;
++
++ set_except_vector(0, mipsIRQ);
++ write_c0_count(0);
++
++ printk("calculating r4koff... ");
++ r4k_offset = cal_r4koff();
++ printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
++
++ est_freq = 2*r4k_offset*HZ;
++ est_freq += 5000; /* round */
++ est_freq -= est_freq%10000;
++ printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
++ (est_freq%1000000)*100/1000000);
++}
++
++void __init ar7_timer_setup(struct irqaction *irq)
++{
++ /* we are using the cpu counter for timer interrupts */
++ irq->handler = no_action; /* we use our own handler */
++ setup_irq(MIPS_CPU_TIMER_IRQ, irq);
++
++ r4k_cur = (read_c0_count() + r4k_offset);
++ write_c0_compare(r4k_cur);
++ set_c0_status(ALLINTS);
++}
+diff -urN kernel-base/arch/mips/config-shared.in kernel-current/arch/mips/config-shared.in
+--- kernel-base/arch/mips/config-shared.in 2005-07-10 03:00:44.784181376 +0200
++++ kernel-current/arch/mips/config-shared.in 2005-07-10 06:40:39.589266104 +0200
+@@ -20,6 +20,16 @@
+ mainmenu_option next_comment
+ comment 'Machine selection'
+ dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
++dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
++if [ "$CONFIG_AR7" = "y" ]; then
++ choice 'Texas Instruments Reference Platform' \
++ "AR7DB CONFIG_AR7DB \
++ AR7RD CONFIG_AR7RD \
++ AR7WRD CONFIG_AR7WRD" AR7DB
++ int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU_FREQUENCY 150
++ int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS_FREQUENCY 125
++ hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
++fi
+ dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
+ dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
+ dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
+@@ -239,6 +249,11 @@
+ define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_PC_KEYB y
+ fi
++if [ "$CONFIG_AR7" = "y" ]; then
++ define_bool CONFIG_NONCOHERENT_IO y
++ define_bool CONFIG_SWAP_IO_SPACE y
++ define_bool CONFIG_AR7_PAGING y
++fi
+ if [ "$CONFIG_CASIO_E55" = "y" ]; then
define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_NONCOHERENT_IO y
-@@ -736,6 +750,7 @@
+@@ -736,6 +751,7 @@
mainmenu_option next_comment
comment 'General setup'
if [ "$CONFIG_ACER_PICA_61" = "y" -o \
"$CONFIG_CASIO_E55" = "y" -o \
"$CONFIG_DDB5074" = "y" -o \
"$CONFIG_DDB5476" = "y" -o \
-@@ -797,6 +812,7 @@
+@@ -797,6 +813,7 @@
bool 'Networking support' CONFIG_NET
if [ "$CONFIG_ACER_PICA_61" = "y" -o \
"$CONFIG_CASIO_E55" = "y" -o \
"$CONFIG_DECSTATION" = "y" -o \
"$CONFIG_IBM_WORKPAD" = "y" -o \
-diff -urN linux-2.4.30/arch/mips/kernel/irq.c linux-2.4.30.dev/arch/mips/kernel/irq.c
---- linux-2.4.30/arch/mips/kernel/irq.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/irq.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/kernel/irq.c kernel-current/arch/mips/kernel/irq.c
+--- kernel-base/arch/mips/kernel/irq.c 2005-07-10 03:00:44.784181376 +0200
++++ kernel-current/arch/mips/kernel/irq.c 2005-07-10 06:40:39.589266104 +0200
@@ -76,6 +76,7 @@
* Generic, controller-independent functions:
*/
/*
* IRQ autodetection code..
-diff -urN linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30.dev/arch/mips/kernel/setup.c
---- linux-2.4.30/arch/mips/kernel/setup.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/setup.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/kernel/mips_ksyms.c kernel-current/arch/mips/kernel/mips_ksyms.c
+--- kernel-base/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
++++ kernel-current/arch/mips/kernel/mips_ksyms.c 2005-07-10 10:08:15.469684456 +0200
+@@ -40,6 +40,10 @@
+ extern long __strnlen_user_nocheck_asm(const char *s);
+ extern long __strnlen_user_asm(const char *s);
+
++#ifdef CONFIG_AR7
++extern int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
++#endif
++
+ EXPORT_SYMBOL(mips_machtype);
+ #ifdef CONFIG_EISA
+ EXPORT_SYMBOL(EISA_bus);
+@@ -102,4 +106,8 @@
+ EXPORT_SYMBOL(ide_ops);
+ #endif
+
++#ifdef CONFIG_AR7
++EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
++#endif
++
+ EXPORT_SYMBOL(get_wchan);
+diff -urN kernel-base/arch/mips/kernel/setup.c kernel-current/arch/mips/kernel/setup.c
+--- kernel-base/arch/mips/kernel/setup.c 2005-07-10 03:00:44.785181224 +0200
++++ kernel-current/arch/mips/kernel/setup.c 2005-07-10 06:40:39.590265952 +0200
@@ -109,6 +109,7 @@
unsigned long isa_slot_offset;
EXPORT_SYMBOL(isa_slot_offset);
max_pfn = 0;
first_usable_pfn = -1UL;
for (i = 0; i < boot_mem_map.nr_map; i++) {
-@@ -376,7 +380,7 @@
-
+@@ -377,6 +381,7 @@
/* Reserve the bootmap memory. */
reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
--
+
+#endif
#ifdef CONFIG_BLK_DEV_INITRD
/* Board specific code should have set up initrd_start and initrd_end */
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
-@@ -494,6 +498,7 @@
+@@ -494,6 +499,7 @@
void hp_setup(void);
void au1x00_setup(void);
void frame_info_init(void);
frame_info_init();
#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
-@@ -691,6 +696,11 @@
+@@ -691,6 +697,11 @@
pmc_yosemite_setup();
break;
#endif
default:
panic("Unsupported architecture");
}
-diff -urN linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30.dev/arch/mips/kernel/traps.c
---- linux-2.4.30/arch/mips/kernel/traps.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/traps.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/kernel/traps.c kernel-current/arch/mips/kernel/traps.c
+--- kernel-base/arch/mips/kernel/traps.c 2005-07-10 03:00:44.786181072 +0200
++++ kernel-current/arch/mips/kernel/traps.c 2005-07-10 06:40:39.591265800 +0200
@@ -40,6 +40,10 @@
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
per_cpu_trap_init();
}
-diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.dev/arch/mips/lib/promlib.c
---- linux-2.4.30/arch/mips/lib/promlib.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/lib/promlib.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/lib/promlib.c kernel-current/arch/mips/lib/promlib.c
+--- kernel-base/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200
++++ kernel-current/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265800 +0200
@@ -1,3 +1,4 @@
+#ifndef CONFIG_AR7
#include <stdarg.h>
va_end(args);
}
+#endif
-diff -urN linux-2.4.30/arch/mips/mm/init.c linux-2.4.30.dev/arch/mips/mm/init.c
---- linux-2.4.30/arch/mips/mm/init.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/mm/init.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/Makefile kernel-current/arch/mips/Makefile
+--- kernel-base/arch/mips/Makefile 2005-07-10 03:00:44.786181072 +0200
++++ kernel-current/arch/mips/Makefile 2005-07-10 06:40:39.591265800 +0200
+@@ -369,6 +369,16 @@
+ endif
+
+ #
++# Texas Instruments AR7
++#
++
++ifdef CONFIG_AR7
++LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o
++SUBDIRS += arch/mips/ar7 arch/mips/ar7/ar7
++LOADADDR += 0x94020000
++endif
++
++#
+ # DECstation family
+ #
+ ifdef CONFIG_DECSTATION
+diff -urN kernel-base/arch/mips/mm/init.c kernel-current/arch/mips/mm/init.c
+--- kernel-base/arch/mips/mm/init.c 2005-07-10 03:00:44.787180920 +0200
++++ kernel-current/arch/mips/mm/init.c 2005-07-10 07:09:29.914216728 +0200
@@ -40,8 +40,10 @@
mmu_gather_t mmu_gathers[NR_CPUS];
return;
}
+#endif
-diff -urN linux-2.4.30/arch/mips/mm/tlb-r4k.c linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c
---- linux-2.4.30/arch/mips/mm/tlb-r4k.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/arch/mips/mm/tlb-r4k.c kernel-current/arch/mips/mm/tlb-r4k.c
+--- kernel-base/arch/mips/mm/tlb-r4k.c 2005-07-10 03:00:44.787180920 +0200
++++ kernel-current/arch/mips/mm/tlb-r4k.c 2005-07-10 06:40:39.592265648 +0200
@@ -20,6 +20,10 @@
#include <asm/pgtable.h>
#include <asm/system.h>
+#endif
}
}
-diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.dev/drivers/char/serial.c
---- linux-2.4.30/drivers/char/serial.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/drivers/char/serial.c 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/drivers/char/serial.c kernel-current/drivers/char/serial.c
+--- kernel-base/drivers/char/serial.c 2005-07-10 03:00:44.789180616 +0200
++++ kernel-current/drivers/char/serial.c 2005-07-10 06:42:02.902600552 +0200
@@ -419,7 +419,40 @@
return 0;
}
* needed for certain old 386 machines, I've left these #define's
* in....
*/
-+#ifdef CONFIG_AR7
++#ifndef CONFIG_AR7
#define serial_inp(info, offset) serial_in(info, offset)
#define serial_outp(info, offset, value) serial_out(info, offset, value)
+#endif
/*
-@@ -1728,7 +1763,15 @@
+@@ -1728,7 +1763,16 @@
/* Special case since 134 is really 134.5 */
quot = (2*baud_base / 269);
else if (baud)
+#ifdef CONFIG_AR7
-+ quot = get_avalanche_vbus_freq() / baud;
++ quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
++ //quot = get_avalanche_vbus_freq() / baud;
+
+ if ((quot%16)>7)
+ quot += 8;
}
/* If the quotient is zero refuse the change */
if (!quot && old_termios) {
-@@ -5552,8 +5595,10 @@
+@@ -5552,8 +5596,10 @@
state->irq = irq_cannonicalize(state->irq);
if (state->hub6)
state->io_type = SERIAL_IO_HUB6;
-+#ifdef CONFIG_AR7
- if (state->port && check_region(state->port,8))
- continue;
-+#endif
- #ifdef CONFIG_MCA
- if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
- continue;
-@@ -6009,7 +6054,15 @@
- info->io_type = state->io_type;
- info->iomem_base = state->iomem_base;
- info->iomem_reg_shift = state->iomem_reg_shift;
-+#ifdef CONFIG_AR7
-+ quot = get_avalanche_vbus_freq() / baud;
-+
-+ if ((quot%16)>7)
-+ quot += 8;
-+ quot /=16;
-+#else
- quot = state->baud_base / baud;
-+#endif
- cval = cflag & (CSIZE | CSTOPB);
- #if defined(__powerpc__) || defined(__alpha__)
- cval >>= 8;
-diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.dev/include/asm-mips/ar7/ar7.h
---- linux-2.4.30/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/ar7.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,137 @@
-+#ifndef _MIPS_AR7_H
-+#define _MIPS_AR7_H
-+
-+#include <linux/config.h>
-+#include <asm/addrspace.h>
-+
-+
-+#ifndef LITTLE_ENDIAN
-+#define LITTLE_ENDIAN
-+#endif
-+
-+#ifndef _LINK_KSEG0_
-+#define _LINK_KSEG0_
-+#endif
-+
-+#include <asm/ar7/tnetd73xx.h>
-+
-+#define AVALANCHE_UART0_INT 7
-+#define AVALANCHE_UART1_INT 8
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+
-+/*
-+ * AR7 board SDRAM base address. This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
-+#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
-+
-+
-+/*
-+ * AR7 board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * AR7 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
-+#define AVALANCHE_GORESET 0x1
-+#define AVALANCHE_GOSTBY 0x1
-+#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
-+
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+
-+/*
-+ * GPIO register map
-+ */
-+
-+/* to be obtained from avalanche_map.h */
-+#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
-+#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
-+#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
-+#define AVALANCHE_GPIO_PIN_COUNT 32
-+#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
-+
-+
-+// Let us define board specific information here.
-+
-+#if defined(CONFIG_AR7DB)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
-+
-+#endif
-+
-+
-+#if defined(CONFIG_AR7RD)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+#endif
-+
-+
-+#if defined(CONFIG_AR7WRD)
-+
-+#define AFECLK_FREQ 35328000
-+#define REFCLK_FREQ 25000000
-+#define OSC3_FREQ 24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
-+
-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
-+#endif
-+
-+#endif
-+
-+extern unsigned int tnetd73xx_vbus_freq;
-+#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
-+
-+static inline unsigned int get_avalanche_vbus_freq(void)
-+{
-+ return (tnetd73xx_vbus_freq);
-+}
-+
-+#endif /*_MIPS_AR7_H */
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,183 @@
-+/* $Id$
-+ *
-+ * avalanche.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
-+ *
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines of the AVALANCHE board specific address-MAP, registers, etc.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHE_H
-+#define _MIPS_AVALANCHE_H
-+
-+#include <asm/addrspace.h>
-+
-+/*
-+ * AVALANCHE board SDRAM base address. This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE 0x14000000UL
-+
-+/*
-+ * AVALANCHE board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+/*
-+ * Avalanche RTC-device indirect register access.
-+ */
-+
-+#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
-+#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
-+
-+/*
-+ * Evm3 interrupt controller register base (primary)
-+ */
-+
-+#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
-+
-+/*
-+ * Avalanche exception controller register base (secondary)
-+ */
-+#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
-+
-+
-+/*
-+ * Avalanche Interrupt Channel Control register base
-+ */
-+#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
-+
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+/*
-+ * AVALANCHE display register base.
-+ */
-+
-+#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
-+#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
-+
-+
-+#define EVM3_ASCIIPOS0 0x1D000038
-+#define EVM3_ASCIIPOS1 0x1D000039
-+#define EVM3_ASCIIPOS2 0x1D00003A
-+#define EVM3_ASCIIPOS3 0x1D00003B
-+#define EVM3_ASCIIPOS4 0x1D00003C
-+#define EVM3_ASCIIPOS5 0x1D00003D
-+#define EVM3_ASCIIPOS6 0x1D00003E
-+#define EVM3_ASCIIPOS7 0x1D00003F
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * Evm3 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
-+#define AVALANCHE_GORESET 0x1
-+#define AVALANCHE_GOSTBY 0x1
-+
-+/************************************************************************
-+ * PERIPHERAL BUS LEDs (P-LED):
-+*************************************************************************/
-+
-+/************************************************************************
-+ * P-LED Register Addresses
-+*************************************************************************/
-+
-+#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
-+
-+
-+/************************************************************************
-+ * Register field encodings
-+*************************************************************************/
-+
-+/******** reg: PLED ********/
-+/* bits 7:0: VAL */
-+#define EVM3_PLED_VAL_MSK 0xff
-+
-+/* bit 0: */
-+#define EVM3_PLED_BIT0_SHF 0
-+#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
-+#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
-+
-+/* bit 1: */
-+#define EVM3_PLED_BIT1_SHF 1
-+#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
-+#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
-+
-+/* bit 2: */
-+#define EVM3_PLED_BIT2_SHF 2
-+#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
-+#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
-+
-+/* bit 3: */
-+#define EVM3_PLED_BIT3_SHF 3
-+#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
-+#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
-+
-+/* bit 4: */
-+#define EVM3_PLED_BIT4_SHF 4
-+#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
-+#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
-+
-+/* bit 5: */
-+#define EVM3_PLED_BIT5_SHF 5
-+#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
-+#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
-+
-+/* bit 6: */
-+#define EVM3_PLED_BIT6_SHF 6
-+#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
-+#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
-+
-+/* bit 7: */
-+#define EVM3_PLED_BIT7_SHF 7
-+#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
-+#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
-+
-+#endif /* !(_MIPS_AVALANCHE_H) */
-+
-+
-+
-+
-+
-+
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_int.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,298 @@
-+/* $Id$
-+ *
-+ * avalancheint.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001 Texas Instruments , Inc.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines for the AVALANCHE interrupt controller.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHEINT_H
-+#define _MIPS_AVALANCHEINT_H
-+
-+#include <linux/config.h>
-+
-+/* Avalanche Interrupt number */
-+#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
-+/* Linux Interrupt number */
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+/* Number of IRQ supported on hw interrupt 0. */
-+
-+//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
-+//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
-+
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
-+#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
-+
-+#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
-+#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
-+
-+
-+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
-+ + MIPS_EXCEPTION_OFFSET - 1)
-+
-+struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
-+{
-+ volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */
-+ volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */
-+ volatile unsigned long unused1; /* 0x08 */
-+ volatile unsigned long unused2; /* 0x0C */
-+ volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */
-+ volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */
-+ volatile unsigned long unused3; /* 0x18 */
-+ volatile unsigned long unused4; /* 0x1C */
-+ volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
-+ volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
-+ volatile unsigned long unused5; /* 0x28 */
-+ volatile unsigned long unused6; /* 0x2C */
-+ volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */
-+ volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */
-+ volatile unsigned long unused7; /* 0x38 */
-+ volatile unsigned long unused8; /* 0x3c */
-+ volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */
-+ volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
-+ volatile unsigned long unused9; /* 0x48 */
-+ volatile unsigned long unused10; /* 0x4C */
-+ volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */
-+ volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */
-+};
-+
-+struct avalanche_exctrl_regs /* Avalanche Exception control registers */
-+{
-+ volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */
-+ volatile unsigned long reserved; /* 0x84 */
-+ volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */
-+ volatile unsigned long reserved1; /* 0x8c */
-+ volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */
-+ volatile unsigned long reserved2; /* 0x94 */
-+ volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
-+};
-+
-+struct avalanche_channel_int_number
-+{
-+ volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */
-+ volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */
-+ volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */
-+ volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */
-+ volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */
-+ volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */
-+ volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */
-+ volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */
-+ volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */
-+ volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */
-+ volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */
-+ volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */
-+ volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */
-+ volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */
-+ volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */
-+ volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */
-+ volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */
-+ volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */
-+ volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */
-+ volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */
-+ volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */
-+ volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */
-+ volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */
-+ volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */
-+ volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */
-+ volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */
-+ volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */
-+ volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */
-+ volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */
-+ volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */
-+ volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */
-+ volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */
-+ volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */
-+ volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */
-+ volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */
-+ volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */
-+ volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */
-+ volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */
-+ volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */
-+ volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */
-+};
-+
-+struct avalanche_interrupt_line_to_channel
-+{
-+ unsigned long int_line0; /* Start of primary interrupts */
-+ unsigned long int_line1;
-+ unsigned long int_line2;
-+ unsigned long int_line3;
-+ unsigned long int_line4;
-+ unsigned long int_line5;
-+ unsigned long int_line6;
-+ unsigned long int_line7;
-+ unsigned long int_line8;
-+ unsigned long int_line9;
-+ unsigned long int_line10;
-+ unsigned long int_line11;
-+ unsigned long int_line12;
-+ unsigned long int_line13;
-+ unsigned long int_line14;
-+ unsigned long int_line15;
-+ unsigned long int_line16;
-+ unsigned long int_line17;
-+ unsigned long int_line18;
-+ unsigned long int_line19;
-+ unsigned long int_line20;
-+ unsigned long int_line21;
-+ unsigned long int_line22;
-+ unsigned long int_line23;
-+ unsigned long int_line24;
-+ unsigned long int_line25;
-+ unsigned long int_line26;
-+ unsigned long int_line27;
-+ unsigned long int_line28;
-+ unsigned long int_line29;
-+ unsigned long int_line30;
-+ unsigned long int_line31;
-+ unsigned long int_line32;
-+ unsigned long int_line33;
-+ unsigned long int_line34;
-+ unsigned long int_line35;
-+ unsigned long int_line36;
-+ unsigned long int_line37;
-+ unsigned long int_line38;
-+ unsigned long int_line39;
-+};
-+
-+/* Interrupt Line #'s (Avalanche peripherals) */
-+
-+/*------------------------------*/
-+/* Avalanche primary interrupts */
-+/*------------------------------*/
-+#define UNIFIED_SECONDARY_INTERRUPT 0
-+#define AVALANCHE_EXT_INT_0 1
-+#define AVALANCHE_EXT_INT_1 2
-+#define AVALANCHE_EXT_INT_2 3
-+#define AVALANCHE_EXT_INT_3 4
-+#define AVALANCHE_TIMER_0_INT 5
-+#define AVALANCHE_TIMER_1_INT 6
-+#define AVALANCHE_UART0_INT 7
-+#define AVALANCHE_UART1_INT 8
-+#define AVALANCHE_PDMA_INT0 9
-+#define AVALANCHE_PDMA_INT1 10
-+#define AVALANCHE_HDLC_TXA 11
-+#define AVALANCHE_HDLC_TXB 12
-+#define AVALANCHE_HDLC_RXA 13
-+#define AVALANCHE_HDLC_RXB 14
-+#define AVALANCHE_ATM_SAR_TXA 15
-+#define AVALANCHE_ATM_SAR_TXB 16
-+#define AVALANCHE_ATM_SAR_RXA 17
-+#define AVALANCHE_ATM_SAR_RXB 18
-+#define AVALANCHE_MAC_TXA 19
-+#define AVALANCHE_MAC_RXA 20
-+#define AVALANCHE_DSP_SUB0 21
-+#define AVALANCHE_DSP_SUB1 22
-+#define AVALANCHE_DES_INT 23
-+#define AVALANCHE_USB_INT 24
-+#define AVALANCHE_PCI_INTA 25
-+#define AVALANCHE_PCI_INTB 26
-+#define AVALANCHE_PCI_INTC 27
-+/* Line #28 Reserved */
-+#define AVALANCHE_I2CM_INT 29
-+#define AVALANCHE_PDMA_INT2 30
-+#define AVALANCHE_PDMA_INT3 31
-+#define AVALANCHE_CODEC 32
-+#define AVALANCHE_MAC_TXB 33
-+#define AVALANCHE_MAC_RXB 34
-+/* Line #35 Reserved */
-+/* Line #36 Reserved */
-+/* Line #37 Reserved */
-+/* Line #38 Reserved */
-+/* Line #39 Reserved */
-+
-+#define DEBUG_MISSED_INTS 1
-+
-+#ifdef DEBUG_MISSED_INTS
-+struct debug_missed_int
-+{
-+ unsigned int atm_sar_txa;
-+ unsigned int atm_sar_txb;
-+ unsigned int atm_sar_rxa;
-+ unsigned int atm_sar_rxb;
-+ unsigned int mac_txa;
-+ unsigned int mac_rxa;
-+ unsigned int mac_txb;
-+ unsigned int mac_rxb;
-+};
-+#endif /* DEBUG_MISSED_INTS */
-+
-+/*-----------------------------------*/
-+/* Avalanche Secondary Interrupts */
-+/*-----------------------------------*/
-+#define PRIMARY_INTS 40
-+
-+#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS)
-+#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS)
-+/* Line #02 Reserved */
-+#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS)
-+#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS)
-+/* Line #06 Reserved */
-+#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS)
-+/* Line #10-#20 Reserved */
-+#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS)
-+#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS)
-+/* Line #24-#31 Reserved */
-+
-+#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT)
-+#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT)
-+#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
-+#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
-+
-+#ifdef JIMK_INT_CTRLR
-+/*-----------------------------------*/
-+/* Jim Kennedy's Interrupt Controller*/
-+/*-----------------------------------*/
-+
-+/* to clear the interrupt write the bit back to the status reg */
-+
-+#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
-+#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404))
-+#define JIMK_SAR_STATUS (1<<0)
-+#define JIMK_SAR_TX_A (1<<1)
-+#define JIMK_SAR_TX_B (1<<2)
-+#define JIMK_SAR_RX_A (1<<3)
-+#define JIMK_SAR_RX_B (1<<4)
-+#define JIMK_AAL2_STATUS (1<<5)
-+#define JIMK_UART0_INT (1<<11)
-+
-+#ifdef SEAD_USB_DEVELOPMENT
-+#define JIMK_USB_INT (1<<0)
-+#endif /* SEAD_USB_DEVELOPMENT */
-+
-+#endif /* JIMK_INT_CTRLR */
-+
-+extern void avalanche_int_set(int channel, int line);
-+extern void avalancheint_init(void);
++#ifndef CONFIG_AR7
+ if (state->port && check_region(state->port,8))
+ continue;
++#endif
+ #ifdef CONFIG_MCA
+ if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
+ continue;
+@@ -6009,7 +6055,16 @@
+ info->io_type = state->io_type;
+ info->iomem_base = state->iomem_base;
+ info->iomem_reg_shift = state->iomem_reg_shift;
++#ifdef CONFIG_AR7
++ //quot = get_avalanche_vbus_freq() / baud;
++ quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
+
++ if ((quot%16)>7)
++ quot += 8;
++ quot /=16;
++#else
+ quot = state->baud_base / baud;
++#endif
+ cval = cflag & (CSIZE | CSTOPB);
+ #if defined(__powerpc__) || defined(__alpha__)
+ cval >>= 8;
+diff -urN kernel-base/include/asm-mips/ar7/ar7.h kernel-current/include/asm-mips/ar7/ar7.h
+--- kernel-base/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/ar7.h 2005-07-10 06:40:39.622261088 +0200
+@@ -0,0 +1,33 @@
++/*
++ * $Id$
++ * Copyright (C) $Date$ $Author$
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ *
++ */
+
-+#endif /* !(_MIPS_AVALANCHEINT_H) */
++#ifndef _AR7_H
++#define _AR7_H
+
++#include <asm/addrspace.h>
++#include <linux/config.h>
+
++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
+
++#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
++#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610E00))
++#define AR7_BASE_BAUD ( 3686400 / 16 )
+
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,273 @@
++#endif
+diff -urN kernel-base/include/asm-mips/ar7/avalanche_intc.h kernel-current/include/asm-mips/ar7/avalanche_intc.h
+--- kernel-base/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/avalanche_intc.h 2005-07-10 06:40:39.622261088 +0200
+@@ -0,0 +1,278 @@
+ /*
+ * Nitin Dhingra, iamnd@ti.com
+ * Copyright (C) 2000 Texas Instruments Inc.
+/*
+ * Avalanche interrupt controller register base (primary)
+ */
-+#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
++#define KSEG1_BASE 0xA0000000
++#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
++#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
++#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
++
++#define AVALANCHE_ICTRL_REGS_BASE KSEG1ADDR(0x08612400)// AVALANCHE_INTC_BASE
+
+/******************************************************************************
+ * Avalanche exception controller register base (secondary)
+
+
+#endif /* _AVALANCHE_INTC_H */
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,54 @@
-+/* $Id$
-+ *
-+ * prom.h
-+ *
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999 MIPS Technologies, Inc.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Sead bootprom interface for the Linux kernel.
-+ *
-+ */
-+
-+#ifndef _MIPS_PROM_H
-+#define _MIPS_PROM_H
-+
-+extern char *prom_getcmdline(void);
-+extern char *prom_getenv(char *name);
-+extern void setup_prom_printf(void);
-+extern void prom_printf(char *fmt, ...);
-+extern void prom_init_cmdline(void);
-+extern void prom_meminit(void);
-+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-+extern void prom_free_prom_memory (void);
-+extern void sead_display_message(const char *str);
-+extern void sead_display_word(unsigned int num);
-+extern int get_ethernet_addr(char *ethernet_addr);
-+
-+/* Memory descriptor management. */
-+#define PROM_MAX_PMEMBLOCKS 32
-+struct prom_pmemblock {
-+ unsigned long base; /* Within KSEG0. */
-+ unsigned int size; /* In bytes. */
-+ unsigned int type; /* free or prom memory */
-+};
-+
-+
-+#endif /* !(_MIPS_PROM_H) */
-+
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/include/asm-mips/ar7/avalanche_regs.h kernel-current/include/asm-mips/ar7/avalanche_regs.h
+--- kernel-base/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/avalanche_regs.h 2005-07-10 09:27:48.638618856 +0200
@@ -0,0 +1,567 @@
+/*
+ * $Id$
+
+#define VMAC_STATS_BASE(X) (X + 0x00000400)
+
++#endif __AVALANCHE_REGS_H
++
++
++
++
++
++
+diff -urN kernel-base/include/asm-mips/ar7/if_port.h kernel-current/include/asm-mips/ar7/if_port.h
+--- kernel-base/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/if_port.h 2005-07-10 06:40:39.623260936 +0200
+@@ -0,0 +1,26 @@
++/*******************************************************************************
++ * FILE PURPOSE: Interface port id Header file
++ *******************************************************************************
++ * FILE NAME: if_port.h
++ *
++ * DESCRIPTION: Header file carrying information about port ids of interfaces
++ *
++ *
++ * (C) Copyright 2003, Texas Instruments, Inc
++ ******************************************************************************/
++#ifndef _IF_PORT_H_
++#define _IF_PORT_H_
++
++#define AVALANCHE_CPMAC_LOW_PORT_ID 0
++#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
++#define AVALANCHE_USB_PORT_ID 2
++#define AVALANCHE_WLAN_PORT_ID 3
++
++
++#define AVALANCHE_MARVELL_BASE_PORT_ID 4
++
++/* The marvell ports occupy port ids from 4 to 8 */
++/* so the next port id number should start at 9 */
++
++
++#endif /* _IF_PORT_H_ */
+diff -urN kernel-base/include/asm-mips/ar7/ledapp.h kernel-current/include/asm-mips/ar7/ledapp.h
+--- kernel-base/include/asm-mips/ar7/ledapp.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/ledapp.h 2005-07-10 08:26:11.663644480 +0200
+@@ -0,0 +1,59 @@
++#ifndef __LED_APP__
++#define __LED_APP__
++
++#define CONF_FILE "/etc/led.conf"
++#define LED_PROC_FILE "/proc/led_mod/led"
++
++#define CONFIG_LED_MODULE
++
++#define MAX_MOD_ID 25
++#define MAX_STATE_ID 25
++#define MAX_LED_ID 25
++
++#define MOD_ADSL 1
++#define DEF_ADSL_IDLE 1
++#define DEF_ADSL_TRAINING 2
++#define DEF_ADSL_SYNC 3
++#define DEF_ADSL_ACTIVITY 4
++
++#define MOD_WAN 2
++#define DEF_WAN_IDLE 1
++#define DEF_WAN_NEGOTIATE 2
++#define DEF_WAN_SESSION 3
++
++#define MOD_LAN 3
++#define DEF_LAN_IDLE 1
++#define DEF_LAN_LINK_UP 2
++#define DEF_LAN_ACTIVITY 3
++
++#define MOD_WLAN 4
++#define DEF_WLAN_IDLE 1
++#define DEF_WLAN_LINK_UP 2
++#define DEF_WLAN_ACTIVITY 3
++
++#define MOD_USB 5
++#define DEF_USB_IDLE 1
++#define DEF_USB_LINK_UP 2
++#define DEF_USB_ACTIVITY 3
++
++#define MOD_ETH 6
++#define DEF_ETH_IDLE 1
++#define DEF_ETH_LINK_UP 2
++#define DEF_ETH_ACTIVITY 3
++
++typedef struct config_elem{
++ unsigned char name;
++ unsigned char state;
++ unsigned char mode;
++ unsigned char led;
++ int param;
++}config_elem_t;
++
++typedef struct led_reg{
++ unsigned int param;
++ void (*init)(unsigned long param);
++ void (*onfunc)(unsigned long param);
++ void (*offfunc)(unsigned long param);
++}led_reg_t;
++
++#endif
+diff -urN kernel-base/include/asm-mips/ar7/sangam_boards.h kernel-current/include/asm-mips/ar7/sangam_boards.h
+--- kernel-base/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/sangam_boards.h 2005-07-10 06:40:39.623260936 +0200
+@@ -0,0 +1,77 @@
++#ifndef _SANGAM_BOARDS_H
++#define _SANGAM_BOARDS_H
++
++// Let us define board specific information here.
++
++
++#if defined(CONFIG_AR7DB)
++
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++
++#endif
++
++
++#if defined(CONFIG_AR7RD)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7WI)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7V)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7WRD)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7VWI)
++#define AFECLK_FREQ 35328000
++#define REFCLK_FREQ 25000000
++#define OSC3_FREQ 24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
++#endif
++
++
++#if defined CONFIG_SEAD2
++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
++#include <asm/mips-boards/sead.h>
++#endif
++
++
+#endif
+diff -urN kernel-base/include/asm-mips/ar7/sangam.h kernel-current/include/asm-mips/ar7/sangam.h
+--- kernel-base/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/sangam.h 2005-07-10 06:40:39.624260784 +0200
+@@ -0,0 +1,180 @@
++#ifndef _SANGAM_H_
++#define _SANGAM_H_
++
++#include <linux/config.h>
++#include <asm/addrspace.h>
++
++/*----------------------------------------------------
++ * Sangam's Module Base Addresses
++ *--------------------------------------------------*/
++#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
++#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
++#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
++#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
++#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
++#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
++#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
++#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
++#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
++#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
++#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
++#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
++#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
++#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
++#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
++#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
++#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
++#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
++#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
++#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
++#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
++#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
++#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
++#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
++#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
++#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
++#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
++
++#define AVALANCHE_SDRAM_BASE 0x14000000UL
++
++
++/*----------------------------------------------------
++ * Sangam Interrupt Map (Primary Interrupts)
++ *--------------------------------------------------*/
++
++#define AVALANCHE_UNIFIED_SECONDARY_INT 0
++#define AVALANCHE_EXT_INT_0 1
++#define AVALANCHE_EXT_INT_1 2
++/* Line# 3 to 4 are reserved */
++#define AVALANCHE_TIMER_0_INT 5
++#define AVALANCHE_TIMER_1_INT 6
++#define AVALANCHE_UART0_INT 7
++#define AVALANCHE_UART1_INT 8
++#define AVALANCHE_DMA_INT0 9
++#define AVALANCHE_DMA_INT1 10
++/* Line# 11 to 14 are reserved */
++#define AVALANCHE_ATM_SAR_INT 15
++/* Line# 16 to 18 are reserved */
++#define AVALANCHE_LOW_CPMAC_INT 19
++/* Line# 20 is reserved */
++#define AVALANCHE_LOW_VLYNQ_INT 21
++#define AVALANCHE_CODEC_WAKEUP_INT 22
++/* Line# 23 is reserved */
++#define AVALANCHE_USB_SLAVE_INT 24
++#define AVALANCHE_HIGH_VLYNQ_INT 25
++/* Line# 26 to 27 are reserved */
++#define AVALANCHE_UNIFIED_PHY_INT 28
++#define AVALANCHE_I2C_INT 29
++#define AVALANCHE_DMA_INT2 30
++#define AVALANCHE_DMA_INT3 31
++/* Line# 32 is reserved */
++#define AVALANCHE_HIGH_CPMAC_INT 33
++/* Line# 34 to 36 is reserved */
++#define AVALANCHE_VDMA_VT_RX_INT 37
++#define AVALANCHE_VDMA_VT_TX_INT 38
++#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
++
++
++#define AVALANCHE_EMIF_INT 47
++
++
++
++/*-----------------------------------------------------------
++ * Sangam's Reset Bits
++ *---------------------------------------------------------*/
++
++#define AVALANCHE_UART0_RESET_BIT 0
++#define AVALANCHE_UART1_RESET_BIT 1
++#define AVALANCHE_I2C_RESET_BIT 2
++#define AVALANCHE_TIMER0_RESET_BIT 3
++#define AVALANCHE_TIMER1_RESET_BIT 4
++/* Reset bit 5 is reserved. */
++#define AVALANCHE_GPIO_RESET_BIT 6
++#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
++#define AVALANCHE_USB_SLAVE_RESET_BIT 8
++#define AVALANCHE_ATM_SAR_RESET_BIT 9
++/* Reset bit 10 is reserved. */
++#define AVALANCHE_VDMA_VT_RESET_BIT 11
++#define AVALANCHE_FSER_RESET_BIT 12
++/* Reset bit 13 to 15 are reserved */
++#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
++#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
++#define AVALANCHE_MCDMA_RESET_BIT 18
++#define AVALANCHE_BIST_RESET_BIT 19
++#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
++#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
++#define AVALANCHE_MDIO_RESET_BIT 22
++#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
++/* Reset bit 24 to 25 are reserved */
++#define AVALANCHE_LOW_EPHY_RESET_BIT 26
++/* Reset bit 27 to 31 are reserved */
++
++
++#define AVALANCHE_POWER_MODULE_USBSP 0
++#define AVALANCHE_POWER_MODULE_WDTP 1
++#define AVALANCHE_POWER_MODULE_UT0P 2
++#define AVALANCHE_POWER_MODULE_UT1P 3
++#define AVALANCHE_POWER_MODULE_IICP 4
++#define AVALANCHE_POWER_MODULE_VDMAP 5
++#define AVALANCHE_POWER_MODULE_GPIOP 6
++#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
++#define AVALANCHE_POWER_MODULE_SARP 8
++#define AVALANCHE_POWER_MODULE_ADSLP 9
++#define AVALANCHE_POWER_MODULE_EMIFP 10
++#define AVALANCHE_POWER_MODULE_ADSPP 12
++#define AVALANCHE_POWER_MODULE_RAMP 13
++#define AVALANCHE_POWER_MODULE_ROMP 14
++#define AVALANCHE_POWER_MODULE_DMAP 15
++#define AVALANCHE_POWER_MODULE_BISTP 16
++#define AVALANCHE_POWER_MODULE_TIMER0P 18
++#define AVALANCHE_POWER_MODULE_TIMER1P 19
++#define AVALANCHE_POWER_MODULE_EMAC0P 20
++#define AVALANCHE_POWER_MODULE_EMAC1P 22
++#define AVALANCHE_POWER_MODULE_EPHYP 24
++#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
++
++
++
++
++
++/*
++ * Sangam board vectors
++ */
++
++#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
++
++/*-----------------------------------------------------------------------------
++ * Sangam's system register.
++ *
++ *---------------------------------------------------------------------------*/
++#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
++#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
++#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
++#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
++#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
++
++#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
++#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
++
++#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
++#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
++#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
++#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
++#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
++
++/*
++ * Yamon Prom print address.
++ */
++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
++#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
++
++#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
++
++#define AVALANCHE_GPIO_PIN_COUNT 32
++#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
++
++#include "sangam_boards.h"
+
++#endif /*_SANGAM_H_ */
+diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx_err.h kernel-current/include/asm-mips/ar7/tnetd73xx_err.h
+--- kernel-base/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-10 09:34:36.482617144 +0200
+@@ -0,0 +1,42 @@
++/******************************************************************************
++ * FILE PURPOSE: TNETD73xx Error Definations Header File
++ ******************************************************************************
++ * FILE NAME: tnetd73xx_err.h
++ *
++ * DESCRIPTION: Error definations for TNETD73XX
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++
++#ifndef __TNETD73XX_ERR_H__
++#define __TNETD73XX_ERR_H__
++
++typedef enum TNETD73XX_ERR_t
++{
++ TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
++ TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
++
++ /* Pointers and args */
++ TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
++ TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
++ TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
+
++ /* Memory issues */
++ TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
++ TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
++ TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
++ TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
+
++ /* Device issues */
++ TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
++ TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
+
++ TNETD73XX_ERR_INVID = -30 /* Invalid ID */
+
++} TNETD73XX_ERR;
+
-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,340 @@
++#endif /* __TNETD73XX_ERR_H__ */
+diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx.h kernel-current/include/asm-mips/ar7/tnetd73xx.h
+--- kernel-base/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/tnetd73xx.h 2005-07-10 09:51:18.910224984 +0200
+@@ -0,0 +1,338 @@
+/******************************************************************************
+ * FILE PURPOSE: TNETD73xx Common Header File
+ ******************************************************************************
+
+#ifndef _ASMLANGUAGE /* This part not for assembly language */
+
-+#include <linux/types.h>
-+
+extern unsigned int tnetd73xx_mips_freq;
+extern unsigned int tnetd73xx_vbus_freq;
+
+#endif
+
+#ifndef KSEG0
-+#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
++#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
+#endif
+
+#ifndef KSEG1
-+#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
++#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
+#endif
+
+#ifndef KUSEG
-+#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK)
++#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
+#endif
+
+#ifndef PHYS_ADDR
+#endif
+
+#ifndef REG8_ADDR
-+#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr))
-+#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr)))
++#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
++#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
+#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
-+#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr);
++#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
+#endif
+
+#ifndef REG16_ADDR
-+#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr))
-+#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr)))
++#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
++#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
+#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
-+#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr);
++#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
+#endif
+
+#ifndef REG32_ADDR
-+#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr))
-+#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr)))
++#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
++#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
+#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
-+#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr);
++#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
+#endif
+
+#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
+
+
+#endif /* __TNETD73XX_H_ */
-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,42 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Error Definations Header File
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx_err.h
-+ *
-+ * DESCRIPTION: Error definations for TNETD73XX
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+
-+#ifndef __TNETD73XX_ERR_H__
-+#define __TNETD73XX_ERR_H__
-+
-+typedef enum TNETD73XX_ERR_t
-+{
-+ TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
-+ TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
-+
-+ /* Pointers and args */
-+ TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
-+ TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
-+ TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
-+
-+ /* Memory issues */
-+ TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
-+ TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
-+ TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
-+ TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
-+
-+ /* Device issues */
-+ TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
-+ TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
-+
-+ TNETD73XX_ERR_INVID = -30 /* Invalid ID */
-+
-+} TNETD73XX_ERR;
-+
-+#endif /* __TNETD73XX_ERR_H__ */
-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,243 @@
+diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx_misc.h kernel-current/include/asm-mips/ar7/tnetd73xx_misc.h
+--- kernel-base/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-10 09:53:49.418344272 +0200
+@@ -0,0 +1,239 @@
+/******************************************************************************
+ * FILE PURPOSE: TNETD73xx Misc modules API Header
+ ******************************************************************************
+#ifndef __TNETD73XX_MISC_H__
+#define __TNETD73XX_MISC_H__
+
-+#include <linux/types.h>
-+
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
-+
+/*****************************************************************************
+ * Reset Control Module
+ *****************************************************************************/
+ CLKC_ADSLSS
+} TNETD73XX_CLKC_ID_T;
+
-+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
-+u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
++void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
++TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
++__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
+
+/*****************************************************************************
+ * GPIO Control
+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
+
+/* TNETD73XX Revision */
-+u32 tnetd73xx_get_revision(void);
++__u32 tnetd73xx_get_revision(void);
+
+#endif /* __TNETD73XX_MISC_H__ */
-diff -urN linux-2.4.30/include/asm-mips/io.h linux-2.4.30.dev/include/asm-mips/io.h
---- linux-2.4.30/include/asm-mips/io.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/io.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/include/asm-mips/io.h kernel-current/include/asm-mips/io.h
+--- kernel-base/include/asm-mips/io.h 2005-07-10 03:00:44.797179400 +0200
++++ kernel-current/include/asm-mips/io.h 2005-07-10 06:40:39.624260784 +0200
@@ -63,8 +63,12 @@
#ifdef CONFIG_64BIT_PHYS_ADDR
#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
#define IO_SPACE_LIMIT 0xffff
-diff -urN linux-2.4.30/include/asm-mips/irq.h linux-2.4.30.dev/include/asm-mips/irq.h
---- linux-2.4.30/include/asm-mips/irq.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/irq.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/include/asm-mips/irq.h kernel-current/include/asm-mips/irq.h
+--- kernel-base/include/asm-mips/irq.h 2005-07-10 03:00:44.798179248 +0200
++++ kernel-current/include/asm-mips/irq.h 2005-07-10 06:40:39.624260784 +0200
@@ -14,7 +14,12 @@
#include <linux/config.h>
#include <linux/linkage.h>
#ifdef CONFIG_I8259
static inline int irq_cannonicalize(int irq)
-diff -urN linux-2.4.30/include/asm-mips/page.h linux-2.4.30.dev/include/asm-mips/page.h
---- linux-2.4.30/include/asm-mips/page.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/page.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/include/asm-mips/page.h kernel-current/include/asm-mips/page.h
+--- kernel-base/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200
++++ kernel-current/include/asm-mips/page.h 2005-07-10 06:40:39.625260632 +0200
@@ -129,7 +129,11 @@
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
-diff -urN linux-2.4.30/include/asm-mips/pgtable-32.h linux-2.4.30.dev/include/asm-mips/pgtable-32.h
---- linux-2.4.30/include/asm-mips/pgtable-32.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/pgtable-32.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/include/asm-mips/pgtable-32.h kernel-current/include/asm-mips/pgtable-32.h
+--- kernel-base/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.798179248 +0200
++++ kernel-current/include/asm-mips/pgtable-32.h 2005-07-10 06:40:39.625260632 +0200
@@ -108,7 +108,18 @@
* and a page entry and page directory to the page they refer to.
*/
#define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
#define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
#else
-diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mips/serial.h
---- linux-2.4.30/include/asm-mips/serial.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/serial.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN kernel-base/include/asm-mips/serial.h kernel-current/include/asm-mips/serial.h
+--- kernel-base/include/asm-mips/serial.h 2005-07-10 03:00:44.799179096 +0200
++++ kernel-current/include/asm-mips/serial.h 2005-07-10 06:40:39.625260632 +0200
@@ -65,6 +65,15 @@
#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
+#ifdef CONFIG_AR7
+#include <asm/ar7/ar7.h>
+#define AR7_SERIAL_PORT_DEFNS \
-+ { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
-+ { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
++ { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
++ { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
+#else
+#define AR7_SERIAL_PORT_DEFNS
+#endif
ATLAS_SERIAL_PORT_DEFNS \
AU1000_SERIAL_PORT_DEFNS \
COBALT_SERIAL_PORT_DEFNS \
+diff -urN kernel-base/Makefile kernel-current/Makefile
+--- kernel-base/Makefile 2005-07-10 03:00:44.799179096 +0200
++++ kernel-current/Makefile 2005-07-10 06:40:39.626260480 +0200
+@@ -91,7 +91,7 @@
+
+ CPPFLAGS := -D__KERNEL__ -I$(HPATH)
+
+-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
++CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
+ -fno-strict-aliasing -fno-common
+ ifndef CONFIG_FRAME_POINTER
+ CFLAGS += -fomit-frame-pointer
projects / openwrt.git / blobdiff