add fixes for dsl code, clean up old hacks

[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch

diff --git a/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch b/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
index a6c8e05..86d4d35 100644 (file)
--- a/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
+++ b/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
@@ -1,462 +1,6 @@
-diff -urN linux-2.4.30/Makefile linux-2.4.30.dev/Makefile
---- linux-2.4.30/Makefile      2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/Makefile  2005-06-14 15:36:59.000000000 +0200
-@@ -91,7 +91,7 @@
- 
- CPPFLAGS := -D__KERNEL__ -I$(HPATH)
- 
--CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
-+CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
-         -fno-strict-aliasing -fno-common
- ifndef CONFIG_FRAME_POINTER
- CFLAGS += -fomit-frame-pointer
-diff -urN linux-2.4.30/arch/mips/Makefile linux-2.4.30.dev/arch/mips/Makefile
---- linux-2.4.30/arch/mips/Makefile    2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/Makefile        2005-06-14 15:36:59.000000000 +0200
-@@ -369,6 +369,16 @@
- endif
- 
- #
-+# Texas Instruments AR7
-+#
-+
-+ifdef CONFIG_AR7
-+LIBS          += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
-+SUBDIRS               += arch/mips/ar7 arch/mips/ar7/avalanche
-+LOADADDR      += 0x94020000
-+endif
-+
-+#
- # DECstation family
- #
- ifdef CONFIG_DECSTATION
-diff -urN linux-2.4.30/arch/mips/ar7/Makefile linux-2.4.30.dev/arch/mips/ar7/Makefile
---- linux-2.4.30/arch/mips/ar7/Makefile        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/Makefile    2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,12 @@
-+.S.s:
-+      $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+      $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+O_TARGET := ar7.o
-+
-+obj-y := tnetd73xx_misc.o
-+obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
-+
-+include $(TOPDIR)/Rules.make
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/Makefile linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile
---- linux-2.4.30/arch/mips/ar7/avalanche/Makefile      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile  2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,13 @@
-+.S.s:
-+      $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+      $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
-+
-+O_TARGET := avalanche.o
-+
-+obj-y += avalanche_paging.o avalanche_jump.o
-+
-+include $(TOPDIR)/Rules.make
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S
---- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S  2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,69 @@
-+#include <linux/config.h>
-+#include <linux/threads.h>
-+
-+#include <asm/asm.h>
-+#include <asm/cacheops.h>
-+#include <asm/current.h>
-+#include <asm/offset.h>
-+#include <asm/processor.h>
-+#include <asm/regdef.h>
-+#include <asm/cachectl.h>
-+#include <asm/mipsregs.h>
-+#include <asm/stackframe.h>
-+
-+.text
-+
-+.set noreorder
-+.set noat
-+
-+/* TLB Miss Vector */
-+
-+LEAF(jump_tlb_miss)
-+      .set mips2
-+      lui     k0,0x9400
-+      ori     k0,0
-+      jr      k0
-+      nop       
-+END(jump_tlb_miss)
-+
-+      /* Unused TLB Miss Vector */
-+
-+LEAF(jump_tlb_miss_unused)
-+      .set mips2
-+      lui     k0,0x9400
-+      ori     k0,0x80
-+      jr      k0
-+      nop       
-+END(jump_tlb_miss_unused)
-+
-+      /* Cache Error Vector */
-+
-+LEAF(jump_cache_error)
-+      .set mips2
-+      lui     k0,0x9400
-+      ori     k0,0x100
-+      jr      k0
-+      nop       
-+END(jump_cache_error)
-+
-+      /* General Exception */
-+
-+LEAF(jump_general_exception)
-+      .set mips2
-+      lui     k0,0x9400
-+      ori     k0,0x180
-+      jr      k0
-+      nop
-+END(jump_general_exception)
-+
-+      /* Dedicated Interrupt */
-+
-+LEAF(jump_dedicated_interrupt)
-+      .set mips2
-+      lui     k0,0x9400
-+      ori     k0,0x200
-+      jr      k0
-+      nop       
-+END(jump_dedicated_interrupt)
-+
-+      .set at
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c
---- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c    1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c        2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,314 @@
-+/*
-+ *  -*- linux-c -*-
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
-+ * Copyright (C) 2002 Texas Instruments, Inc.
-+ *
-+ */
-+
-+/*
-+ * This file takes care of the "memory hole" issue that exists with the standard
-+ * linux kernel and the TI Avalanche ASIC.  The Avalanche ASIC requires an offset
-+ * of 0x14000000 due to the ASIC's memory map constraints.  This file corrects the
-+ * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
-+ * 
-+ *  -JAH
-+ */
-+#include <linux/config.h>
-+#include <linux/signal.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+#include <linux/ptrace.h>
-+#include <linux/mman.h>
-+#include <linux/mm.h>
-+#include <linux/swap.h>
-+#include <linux/smp.h>
-+#include <linux/init.h>
-+#ifdef CONFIG_BLK_DEV_INITRD
-+#include <linux/blk.h>
-+#endif /* CONFIG_BLK_DEV_INITRD */
-+#include <linux/highmem.h>
-+#include <linux/bootmem.h>
-+
-+#include <asm/processor.h>
-+#include <asm/system.h>
-+#include <asm/uaccess.h>
-+#include <asm/pgtable.h>
-+#include <asm/pgalloc.h>
-+#include <asm/mmu_context.h>
-+#include <asm/io.h>
-+#include <asm/tlb.h>
-+#include <asm/cpu.h>
-+
-+#define __MEMORY_START CONFIG_AR7_MEMORY
-+
-+#ifdef CONFIG_DISCONTIGMEM
-+pg_data_t discontig_page_data[NR_NODES];
-+bootmem_data_t discontig_node_bdata[NR_NODES];
-+#endif
-+
-+static unsigned long totalram_pages;
-+/* static unsigned long totalhigh_pages; */
-+
-+#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
-+#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
-+
-+#define PFN_UP(x)  (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
-+#define PFN_DOWN(x)        ((x) >> PAGE_SHIFT)
-+#define PFN_PHYS(x)        ((x) << PAGE_SHIFT)
-+
-+unsigned long bootmap_size;
-+
-+extern char *prom_getenv(char *envname);
-+
-+/*
-+ * We have upto 8 empty zeroed pages so we can map one of the right colour
-+ * when needed.  This is necessary only on R4000 / R4400 SC and MC versions
-+ * where we have to avoid VCED / VECI exceptions for good performance at
-+ * any price.  Since page is never written to after the initialization we
-+ * don't have to care about aliases on other CPUs.
-+ */
-+
-+static inline unsigned long setup_zero_pages(void)
-+{
-+      unsigned long order, size;
-+      struct page *page;
-+      if(current_cpu_data.options & MIPS_CPU_VCE) 
-+              order = 3;
-+      else 
-+              order = 0;
-+
-+      empty_zero_page = __get_free_pages(GFP_KERNEL, order);
-+
-+      if (!empty_zero_page)
-+              panic("Oh boy, that early out of memory?");
-+
-+      page = virt_to_page(empty_zero_page);
-+
-+      while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
-+              set_bit(PG_reserved, &page->flags);
-+              set_page_count(page, 0);
-+              page++;
-+      }
-+
-+      size = PAGE_SIZE << order;
-+      zero_page_mask = (size - 1) & PAGE_MASK;
-+      memset((void *)empty_zero_page, 0, size);
-+
-+      return 1UL << order;
-+}
-+
-+/*
-+ * paging_init() sets up the page tables
-+ *
-+ * This routines also unmaps the page at virtual kernel address 0, so
-+ * that we can trap those pesky NULL-reference errors in the kernel.
-+ */
-+void __init paging_init(void)
-+{
-+      unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
-+      unsigned long low, start_pfn;
-+
-+      /* Initialize the entire pgd.  */
-+      pgd_init((unsigned long)swapper_pg_dir);
-+      pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
-+
-+
-+      start_pfn = START_PFN;
-+      // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-+      low = MAX_LOW_PFN;
-+
-+      /* Avalanche DMA-able memory 0x14000000+memsize */
-+
-+      zones_size[ZONE_DMA] = low - start_pfn;
-+
-+      free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
-+
-+#ifdef CONFIG_DISCONTIGMEM
-+      zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
-+      zones_size[ZONE_NORMAL] = 0;
-+      free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
-+#endif /* CONFIG_DISCONTIGMEM */
-+
-+}
-+
-+extern char _ftext, _etext, _fdata, _edata, _end;
-+extern char __init_begin, __init_end;
-+
-+void __init mem_init(void)
-+{
-+      int codesize, reservedpages, datasize, initsize;
-+      int tmp;
-+      
-+      max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
-+      high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
-+
-+      /* free up the memory associated with Adam2 -
-+       * that is the, after the first page that is 
-+       * reserved all the way up to the start of the kernel
-+       */
-+      free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
-+                      (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
-+
-+      /* this will put all low memory onto the freelists */
-+      totalram_pages += free_all_bootmem_node(NODE_DATA(0));
-+
-+      /* Setup zeroed pages */
-+      totalram_pages -= setup_zero_pages();   
-+
-+
-+#ifdef CONFIG_DISCONTIGMEM
-+      totalram_pages += free_all_bootmem_node(NODE_DATA(1));
-+#endif
-+      reservedpages = 0;
-+      for (tmp = 0; tmp < num_physpages; tmp++)
-+              /*
-+               * Only count reserved RAM pages
-+               */
-+              if (PageReserved(mem_map+tmp))
-+                      reservedpages++;
-+
-+      codesize =  (unsigned long) &_etext - (unsigned long) &_ftext;
-+      datasize =  (unsigned long) &_edata - (unsigned long) &_fdata;
-+      initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-+
-+      printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
-+                      (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
-+                      max_mapnr << (PAGE_SHIFT-10),
-+                      codesize >> 10,
-+                      reservedpages << (PAGE_SHIFT-10),
-+                      datasize >> 10,
-+                      initsize >> 10);
-+
-+}
-+
-+/* fixes paging routines for avalanche  (utilized in /arch/mips/kernel/setup.c) */
-+
-+void avalanche_bootmem_init(void)
-+{
-+      unsigned long start_pfn, max_pfn;
-+      unsigned long max_low_pfn;
-+      unsigned int memsize,memory_end,memory_start;
-+      char *memsize_str;
-+
-+      memsize_str = prom_getenv("memsize");
-+      if (!memsize_str) {
-+              memsize = 0x02000000;
-+      } else {
-+              memsize = simple_strtol(memsize_str, NULL, 0);
-+      }
-+
-+
-+      memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
-+      memory_end = memory_start + memsize;
-+
-+      /*
-+       * Find the highest memory page fram number we have available 
-+       */
-+
-+      max_pfn = PFN_DOWN(__pa(memory_end));
-+
-+      /*
-+       * Determine the low and high memory ranges 
-+       */
-+
-+      max_low_pfn = max_pfn;
-+
-+      /*
-+       * Partially used pages are not usable - thus we are
-+       * rounding upwards:
-+       */
-+
-+      start_pfn = PFN_UP(__pa(&_end));
-+
-+      /*
-+       * Find a proper area for the bootmem bitmap. After this
-+       * bootstrap step all allocations (until the page allocator is
-+       * intact)  must be done via bootmem_alloc().
-+       */
-+
-+      bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
-+                      __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
-+
-+
-+      /* 
-+       * Register fully available low RAM pages with the bootmem allocator.
-+       */
-+
-+      {
-+              unsigned long curr_pfn, last_pfn, pages;
-+
-+              /*
-+               * We are rounding up the start address of usable memory:
-+               */
-+              curr_pfn = PFN_UP(__MEMORY_START);
-+
-+              /*
-+               * ... and at the end of the usable range downwards:
-+               */
-+              last_pfn = PFN_DOWN(__pa(memory_end));
-+
-+              if (last_pfn > max_low_pfn)
-+                      last_pfn = max_low_pfn;
-+
-+              pages = last_pfn - curr_pfn;
-+
-+
-+              free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
-+                              PFN_PHYS(pages));
-+      }
-+
-+      /*
-+       * Reserve the kernel text and
-+       * Reserve the bootmem bitmap. We do this in two steps (first step
-+       * was init_bootmem()), because this catches the (definitely buggy)
-+       * case of us accidentally initializing the bootmem allocator with
-+       * an invalid RAM area.
-+       */
-+      reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
-+                      (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
-+
-+      /*
-+       * reserve physical page 0 - it's a special BIOS page on many boxes,
-+       * enabling clean reboots, SMP operation, laptop functions.
-+       */
-+      reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
-+}
-+
-+extern char __init_begin, __init_end;
-+
-+void free_initmem(void)
-+{
-+      unsigned long addr;
-+      //      prom_free_prom_memory ();
-+
-+      addr = (unsigned long) &__init_begin;
-+      while (addr < (unsigned long) &__init_end) {
-+              ClearPageReserved(virt_to_page(addr));
-+              set_page_count(virt_to_page(addr), 1);
-+              free_page(addr);
-+              totalram_pages++;
-+              addr += PAGE_SIZE;
-+      }
-+      printk("Freeing unused kernel memory: %dk freed\n",
-+                      (&__init_end - &__init_begin) >> 10);
-+}
-+
-+void si_meminfo(struct sysinfo *val)
-+{
-+      val->totalram = totalram_pages;
-+      val->sharedram = 0;
-+      val->freeram = nr_free_pages();
-+      val->bufferram = atomic_read(&buffermem_pages);
-+      val->totalhigh = 0;
-+      val->freehigh = nr_free_highpages();
-+      val->mem_unit = PAGE_SIZE;
-+
-+      return;
-+}
-diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.dev/arch/mips/ar7/cmdline.c
---- linux-2.4.30/arch/mips/ar7/cmdline.c       1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/cmdline.c   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
+--- linux.old/arch/mips/ar7/cmdline.c  1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/cmdline.c  2005-08-12 19:32:05.137225512 +0200

 @@ -0,0 +1,64 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,64 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -522,10 +66,10 @@ diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.dev/arch/mips/ar7/cm
 +              --cp;
 +      *cp = '\0';
 +}
 +              --cp;
 +      *cp = '\0';
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.c
---- linux-2.4.30/arch/mips/ar7/init.c  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/init.c      2005-06-14 19:15:15.000000000 +0200
-@@ -0,0 +1,144 @@
+diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
+--- linux.old/arch/mips/ar7/init.c     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/init.c     2005-08-12 19:34:07.215666768 +0200
+@@ -0,0 +1,182 @@

 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.


@@ -549,6 +93,7 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +#include <linux/init.h>
 +#include <linux/string.h>
 +#include <linux/kernel.h>
 +#include <linux/init.h>
 +#include <linux/string.h>
 +#include <linux/kernel.h>

++#include <linux/module.h>

 +
 +#include <asm/io.h>
 +#include <asm/mips-boards/prom.h>
 +
 +#include <asm/io.h>
 +#include <asm/mips-boards/prom.h>


@@ -567,10 +112,14 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +#define MAX_ENV_ENTRY 80
 +
 +static t_env_var local_envp[MAX_ENV_ENTRY];
 +#define MAX_ENV_ENTRY 80
 +
 +static t_env_var local_envp[MAX_ENV_ENTRY];

-+
++static int env_type = 0;

 +int init_debug = 0;
 +
 +int init_debug = 0;
 +

-+char *prom_getenv(char *envname)
++unsigned int max_env_entry;
++
++extern char *prom_psp_getenv(char *envname);
++
++static inline char *prom_adam2_getenv(char *envname)

 +{
 +      /*
 +       * Return a pointer to the given environment variable.
 +{
 +      /*
 +       * Return a pointer to the given environment variable.


@@ -578,9 +127,12 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +       * in the PROM structures are only 32-bit, so we need some
 +       * workarounds, if we are running in 64-bit mode.
 +       */
 +       * in the PROM structures are only 32-bit, so we need some
 +       * workarounds, if we are running in 64-bit mode.
 +       */

-+      int i, index=0;
++      int i;

 +      t_env_var *env = (t_env_var *) local_envp;
 +
 +      t_env_var *env = (t_env_var *) local_envp;
 +

++      if (strcmp("bootloader", envname) == 0)
++              return "Adam2";
++

 +      i = strlen(envname);
 +      while (env->name) {
 +              if(strncmp(envname, env->name, i) == 0) {
 +      i = strlen(envname);
 +      while (env->name) {
 +              if(strncmp(envname, env->name, i) == 0) {


@@ -592,6 +144,14 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +      return NULL;
 +}
 +
 +      return NULL;
 +}
 +

++char *prom_getenv(char *envname)
++{
++      if (env_type == 1)
++              return prom_psp_getenv(envname);
++      else
++              return prom_adam2_getenv(envname);
++}
++

 +static inline unsigned char str2hexnum(unsigned char c)
 +{
 +      if (c >= '0' && c <= '9')
 +static inline unsigned char str2hexnum(unsigned char c)
 +{
 +      if (c >= '0' && c <= '9')


@@ -638,27 +198,49 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +      return 0;
 +}
 +
 +      return 0;
 +}
 +

++struct psbl_rec {
++    unsigned int psbl_size;
++    unsigned int env_base;
++    unsigned int env_size;
++    unsigned int ffs_base;
++    unsigned int ffs_size;
++};
++
++static const char psp_env_version[] = "TIENV0.8";
++

 +int __init prom_init(int argc, char **argv, char **envp)
 +{
 +      int i;
 +int __init prom_init(int argc, char **argv, char **envp)
 +{
 +      int i;

++

 +      t_env_var *env = (t_env_var *) envp;
 +      t_env_var *env = (t_env_var *) envp;

++      struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
++      void *psp_env = (void *)KSEG1ADDR(psbl->env_base);

 +
 +      prom_argc = argc;
 +      _prom_argv = (int *)argv;
 +      _prom_envp = (int *)envp;
 +
 +
 +      prom_argc = argc;
 +      _prom_argv = (int *)argv;
 +      _prom_envp = (int *)envp;
 +

-+      /* Copy what we need locally so we are not dependent on
-+       * bootloader RAM.  In Adam2, the environment parameters
-+       * are in flash but the table that references them is in
-+       * RAM
-+       */
-+      for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
-+              if (env->name) {
-+                      local_envp[i].name = env->name;
-+                      local_envp[i].val = env->val;
-+              } else {
-+                      local_envp[i].name = NULL;
-+                      local_envp[i].val = NULL;
++      if(strcmp(psp_env, psp_env_version) == 0) {
++              /* PSPBOOT */
++
++              env_type = 1;
++              _prom_envp = psp_env;
++              max_env_entry = (psbl->env_size / 16) - 1;
++      } else {
++              /* Copy what we need locally so we are not dependent on
++               * bootloader RAM.  In Adam2, the environment parameters
++               * are in flash but the table that references them is in
++               * RAM
++               */
++
++              for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
++                      if (env->name) {
++                              local_envp[i].name = env->name;
++                              local_envp[i].val = env->val;
++                      } else {
++                              local_envp[i].name = NULL;
++                              local_envp[i].val = NULL;
++                      }

 +              }
 +      }
 +
 +              }
 +      }
 +


@@ -670,10 +252,10 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +
 +      return 0;
 +}
 +
 +      return 0;
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
---- linux-2.4.30/arch/mips/ar7/irq.c   1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/irq.c       2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,669 @@
+diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
+--- linux.old/arch/mips/ar7/irq.c      1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/irq.c      2005-08-12 23:42:18.679820112 +0200
+@@ -0,0 +1,709 @@

 +/*
 + * Nitin Dhingra, iamnd@ti.com
 + * Copyright (C) 2002 Texas Instruments, Inc.  All rights reserved.
 +/*
 + * Nitin Dhingra, iamnd@ti.com
 + * Copyright (C) 2002 Texas Instruments, Inc.  All rights reserved.


@@ -1061,6 +643,7 @@ diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
 +extern int remote_debug;
 +#endif
 +
 +extern int remote_debug;
 +#endif
 +

++

 +//void init_IRQ(void) __init;
 +void __init init_IRQ(void)
 +{
 +//void init_IRQ(void) __init;
 +void __init init_IRQ(void)
 +{


@@ -1119,7 +702,6 @@ diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
 +#endif
 +}
 +
 +#endif
 +}
 +

-+

 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
 +{
 +      struct irqaction *action;
 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
 +{
 +      struct irqaction *action;


@@ -1343,10 +925,68 @@ diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
 +
 +}
 +
 +
 +}
 +

-diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/memory.c
---- linux-2.4.30/arch/mips/ar7/memory.c        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/memory.c    2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,130 @@
++
++#define AVALANCHE_MAX_PACING_BLK   3
++#define AVALANCHE_PACING_LOW_VAL   2
++#define AVALANCHE_PACING_HIGH_VAL 63
++
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
++                            unsigned int pace_value)
++{
++    unsigned int  blk_offset;
++    unsigned long flags;
++
++    if(irq_nr < MIPS_EXCEPTION_OFFSET &&
++       irq_nr >= AVALANCHE_INT_END_PRIMARY)
++        return (0);
++
++    if(blk_num > AVALANCHE_MAX_PACING_BLK)
++        return(-1);
++
++    if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
++       pace_value < AVALANCHE_PACING_LOW_VAL)
++       return(-1);
++
++    blk_offset = blk_num*8;
++
++    save_and_cli(flags);
++
++    /* disable the interrupt pacing, if enabled previously */
++    avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
++
++    /* clear the pacing map */
++    avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
++
++    /* setup the new values */
++    avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr))   << blk_offset);
++    avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value)  << blk_offset);
++
++    restore_flags(flags);
++
++    return(0);
++}
+diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
+--- linux.old/arch/mips/ar7/Makefile   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/Makefile   2005-08-12 21:21:30.425150040 +0200
+@@ -0,0 +1,14 @@
++.S.s:
++      $(CPP) $(AFLAGS) $< -o $*.s
++
++.S.o:
++      $(CC) $(AFLAGS) -c $< -o $*.o
++
++EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
++O_TARGET := ar7.o
++
++obj-y := tnetd73xx_misc.o misc.o
++export-objs := misc.o
++obj-y += setup.o irq.o mipsIRQ.o reset.o init.o psp_env.o memory.o printf.o cmdline.o time.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
+--- linux.old/arch/mips/ar7/memory.c   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/memory.c   2005-08-12 19:52:25.301732312 +0200
+@@ -0,0 +1,131 @@

 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.


@@ -1380,7 +1020,6 @@ diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/mem
 +#include <asm/bootinfo.h>
 +#include <asm/page.h>
 +#include <asm/mips-boards/prom.h>
 +#include <asm/bootinfo.h>
 +#include <asm/page.h>
 +#include <asm/mips-boards/prom.h>

-+#include <asm/ar7/ar7.h>

 +
 +enum yamon_memtypes {
 +      yamon_dontuse,
 +
 +enum yamon_memtypes {
 +      yamon_dontuse,


@@ -1411,15 +1050,15 @@ diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/mem
 +
 +      mdesc[0].type = yamon_dontuse;
 +      mdesc[0].base = 0x00000000;
 +
 +      mdesc[0].type = yamon_dontuse;
 +      mdesc[0].base = 0x00000000;

-+      mdesc[0].size = AVALANCHE_SDRAM_BASE;
++      mdesc[0].size = CONFIG_AR7_MEMORY;

 +
 +      mdesc[1].type = yamon_prom;
 +
 +      mdesc[1].type = yamon_prom;

-+      mdesc[1].base = AVALANCHE_SDRAM_BASE;
++      mdesc[1].base = CONFIG_AR7_MEMORY;

 +      mdesc[1].size = 0x00020000;
 +
 +      mdesc[2].type = yamon_free;
 +      mdesc[1].size = 0x00020000;
 +
 +      mdesc[2].type = yamon_free;

-+      mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
-+      mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
++      mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
++      mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;

 +
 +      return &mdesc[0];
 +}
 +
 +      return &mdesc[0];
 +}


@@ -1457,6 +1096,7 @@ diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/mem
 +
 +void __init prom_free_prom_memory (void)
 +{
 +
 +void __init prom_free_prom_memory (void)
 +{

++#if 0

 +      int i;
 +      unsigned long freed = 0;
 +      unsigned long addr;
 +      int i;
 +      unsigned long freed = 0;
 +      unsigned long addr;


@@ -1476,10 +1116,11 @@ diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/mem
 +              }
 +      }
 +      printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
 +              }
 +      }
 +      printk("Freeing prom memory: %ldkb freed\n", freed >> 10);

++#endif

 +}
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S
---- linux-2.4.30/arch/mips/ar7/mipsIRQ.S       1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
+--- linux.old/arch/mips/ar7/mipsIRQ.S  1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/mipsIRQ.S  2005-08-12 19:32:05.138225360 +0200

 @@ -0,0 +1,120 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,120 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -1601,283 +1242,406 @@ diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.dev/arch/mips/ar7/mi
 +      j       ret_from_irq
 +      nop
 +END(mipsIRQ)
 +      j       ret_from_irq
 +      nop
 +END(mipsIRQ)

-diff -urN linux-2.4.30/arch/mips/ar7/printf.c linux-2.4.30.dev/arch/mips/ar7/printf.c
---- linux-2.4.30/arch/mips/ar7/printf.c        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/printf.c    2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,51 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Putting things on the screen/serial line using Adam2 facilities.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/serial_reg.h>
+diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
+--- linux.old/arch/mips/ar7/misc.c     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/misc.c     2005-08-12 19:32:05.136225664 +0200
+@@ -0,0 +1,319 @@
++#include <asm/ar7/sangam.h>
++#include <asm/ar7/avalanche_misc.h>
++#include <linux/module.h>

 +#include <linux/spinlock.h>
 +#include <linux/spinlock.h>

-+#include <asm/io.h>
-+#include <asm/serial.h>
-+#include <asm/addrspace.h>
-+#include <asm/ar7/ar7.h>

 +
 +

-+static char ppbuf[1024];
++#define TRUE 1

 +
 +

-+void (*prom_print_str)(unsigned int out, char *s, int len);
++static unsigned int avalanche_vbus_freq;

 +
 +

-+void prom_printf(char *fmt, ...) __init;
-+void prom_printf(char *fmt, ...)
++REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
++
++/*****************************************************************************
++ * Reset Control Module.
++ *****************************************************************************/
++void avalanche_reset_ctrl(unsigned int module_reset_bit, 
++                          AVALANCHE_RESET_CTRL_T reset_ctrl)

 +{
 +{

-+      va_list args;
-+      int len;
-+      prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
++    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++   
++    if(module_reset_bit >= 32 && module_reset_bit < 64)
++        return;
++
++    if(module_reset_bit >= 64)
++    {
++        if(p_remote_vlynq_dev_reset_ctrl)
++            return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
++        else
++            return;
++    }
++    
++    if(reset_ctrl == OUT_OF_RESET)
++        *reset_reg |= 1 << module_reset_bit;
++    else
++        *reset_reg &= ~(1 << module_reset_bit);
++}

 +
 +

-+      va_start(args, fmt);
-+      vsprintf(ppbuf, fmt, args);
-+      len = strlen(ppbuf);
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
++{
++    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;

 +
 +

-+      prom_print_str(1, ppbuf, len);
++    return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
++}

 +
 +

-+      va_end(args);
-+      return;
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
++{
++    volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
++    *sw_reset_reg =  mode;
++}

 +
 +

++#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
++
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
++{
++    volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
++
++    return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );

 +}
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/reset.c linux-2.4.30.dev/arch/mips/ar7/reset.c
---- linux-2.4.30/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/reset.c     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,54 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
-+ *
-+ * ########################################################################
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Reset the MIPS boards.
-+ *
-+ */
-+#include <linux/config.h>

 +
 +

-+#include <asm/reboot.h>
-+#include <asm/mips-boards/generic.h>

 +
 +

-+static void ar7_machine_restart(char *command);
-+static void ar7_machine_halt(void);
-+static void ar7_machine_power_off(void);
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define AVALANCHE_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
++#define AVALANCHE_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */

 +
 +

-+static void ar7_machine_restart(char *command)
-+{

 +
 +

++void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
++{
++    volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++    if (power_ctrl == POWER_CTRL_POWER_DOWN)
++        /* power down the module */
++        *power_reg |= (1 << module_power_bit);
++    else
++        /* power on the module */
++        *power_reg &= (~(1 << module_power_bit));

 +}
 +
 +}
 +

-+static void ar7_machine_halt(void)
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)

 +{
 +{

++    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;

 +
 +

++    return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);

 +}
 +
 +}
 +

-+static void ar7_machine_power_off(void)
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)

 +{
 +{

++    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;

 +
 +

++    *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
++    *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);

 +}
 +
 +}
 +

-+void ar7_reboot_setup(void)
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)

 +{
 +{

-+      _machine_restart = ar7_machine_restart;
-+      _machine_halt = ar7_machine_halt;
-+      _machine_power_off = ar7_machine_power_off;
++    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++    return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK)) 
++                                           >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));

 +}
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.dev/arch/mips/ar7/setup.c
---- linux-2.4.30/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/setup.c     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,150 @@
-+/*
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/mc146818rtc.h>
-+#include <linux/ioport.h>

 +
 +

-+#include <asm/cpu.h>
-+#include <asm/bootinfo.h>
-+#include <asm/irq.h>
-+#include <asm/mips-boards/generic.h>
-+#include <asm/mips-boards/prom.h>
++/*****************************************************************************
++ * GPIO  Control
++ *****************************************************************************/

 +
 +

-+#include <asm/dma.h>
-+#include <asm/time.h>
-+#include <asm/traps.h>
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_init
++ ***************************************************************************/
++void avalanche_gpio_init(void)
++{
++    spinlock_t closeLock;
++    unsigned int closeFlag;
++    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++    spin_lock_irqsave(&closeLock, closeFlag);
++    *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
++    spin_unlock_irqrestore(&closeLock, closeFlag);  
++}

 +
 +

++/****************************************************************************
++ * FUNCTION: avalanche_gpio_ctrl
++ ***************************************************************************/
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++                        AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++                        AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
++{
++    spinlock_t closeLock;
++    unsigned int closeFlag;
++    volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
++
++    if(gpio_pin >= 32)
++        return(-1);
++
++    spin_lock_irqsave(&closeLock, closeFlag);
++
++    if(pin_mode == GPIO_PIN)
++    {
++        *gpio_ctrl |= (1 << gpio_pin);
++
++      gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
++        
++        if(pin_direction == GPIO_INPUT_PIN)
++            *gpio_ctrl |=  (1 << gpio_pin);
++        else
++            *gpio_ctrl &= ~(1 << gpio_pin);
++    }
++    else /* FUNCTIONAL PIN */
++    {
++        *gpio_ctrl &= ~(1 << gpio_pin);
++    }
++  
++    spin_unlock_irqrestore(&closeLock, closeFlag);  
++
++    return (0);
++}

 +
 +

-+#define _LINK_KSEG0_
-+#define LITTLE_ENDIAN
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out
++ ***************************************************************************/
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
++{
++    spinlock_t closeLock;
++    unsigned int closeFlag;
++    volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++ 
++    if(gpio_pin >= 32)
++        return(-1);
++    
++    spin_lock_irqsave(&closeLock, closeFlag);
++    if(value == TRUE)
++        *gpio_out |= 1 << gpio_pin;
++    else
++      *gpio_out &= ~(1 << gpio_pin);
++    spin_unlock_irqrestore(&closeLock, closeFlag);
++
++    return(0);
++}

 +
 +

-+// Specific for ar7wrd
-+unsigned int tnetd73xx_vbus_freq;
-+#define BOOTCR_MIPS_ASYNC_MODE  (1 << 25)
-+#define AFECLK_FREQ                                 35328000
-+#define REFCLK_FREQ                                 25000000
-+#define OSC3_FREQ                                   24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK           0x80000000
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in
++ ***************************************************************************/
++int avalanche_gpio_in_bit(unsigned int gpio_pin)
++{
++    spinlock_t closeLock;
++    unsigned int closeFlag;
++    volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++    int ret_val = 0;
++    
++    if(gpio_pin >= 32)
++        return(-1);
++
++    spin_lock_irqsave(&closeLock, closeFlag); 
++    ret_val = ((*gpio_in) & (1 << gpio_pin));
++    spin_unlock_irqrestore(&closeLock, closeFlag);
++ 
++    return (ret_val);
++}

 +
 +

-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x2
-+#endif
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out_val
++ ***************************************************************************/
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask, 
++                           unsigned int reg_index)
++{
++    spinlock_t closeLock;
++    unsigned int closeFlag;
++    volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;

 +
 +

++    if(reg_index > 0)
++        return(-1);

 +
 +

-+#ifdef CONFIG_KGDB
-+extern void rs_kgdb_hook(int);
-+int remote_debug = 0;
-+#endif
++    spin_lock_irqsave(&closeLock, closeFlag);
++    *gpio_out &= ~out_mask;
++    *gpio_out |= out_val;
++    spin_unlock_irqrestore(&closeLock, closeFlag);

 +
 +

-+extern struct rtc_ops no_rtc_ops;
++    return(0);
++}

 +
 +

-+extern void ar7_reboot_setup(void);
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in_value
++ ***************************************************************************/
++int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
++{
++    spinlock_t closeLock;
++    unsigned int closeFlag;
++    volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++ 
++    if(reg_index > 0)
++        return(-1);

 +
 +

-+extern void ar7_time_init(void);
-+extern void ar7_timer_setup(struct irqaction *irq);
++    spin_lock_irqsave(&closeLock, closeFlag);
++    *in_val = *gpio_in;
++    spin_unlock_irqrestore(&closeLock, closeFlag);

 +
 +

-+/* maybe some of this is not needed? */
-+static void ar7_platform_init(void)
-+{
-+      //tnetd73xx_gpio_init();
++    return (0);
++}

 +
 +

-+      tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
-+      //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+      //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
++/***********************************************************************
++ *
++ *    Wakeup Control Module for TNETV1050 Communication Processor
++ *
++ ***********************************************************************/

 +
 +

-+      //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
-+      //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
++#define AVALANCHE_WAKEUP_POLARITY_BIT   16

 +
 +

-+      tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++                           AVALANCHE_WAKEUP_CTRL_T      wakeup_ctrl,
++                           AVALANCHE_WAKEUP_POLARITY_T  wakeup_polarity)
++{
++    volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
++
++    /* enable/disable */
++    if (wakeup_ctrl == WAKEUP_ENABLED)
++        /* enable wakeup */
++        *wakeup_status_reg |= wakeup_int;
++    else
++        /* disable wakeup */
++        *wakeup_status_reg &= (~wakeup_int);
++
++    /* set polarity */
++    if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
++        *wakeup_status_reg |=  (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++    else
++        *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++}

 +
 +

-+      tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
++void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
++{
++    avalanche_vbus_freq = new_vbus_freq;
++}

 +
 +

-+#if defined(CONFIG_AR7WRD)
-+      if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
-+              tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
-+      }
-+#endif
++unsigned int avalanche_get_vbus_freq()
++{
++    return(avalanche_vbus_freq);
++}

 +
 +

++unsigned int avalanche_get_chip_version_info()
++{
++    return(*(volatile unsigned int*)AVALANCHE_CVR);

 +}
 +
 +}
 +

-+const char *get_system_type(void)
++SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
++
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)

 +{
 +{

-+      return "Texas Instruments AR7";
++    if(p_set_mdix_on_chip_fn)
++        return (p_set_mdix_on_chip_fn(base_addr, operation));
++    else
++        return(-1);

 +}
 +
 +}
 +

-+void __init ar7_setup(void)
++unsigned int avalanche_is_mdix_on_chip(void)

 +{
 +{

-+#ifdef CONFIG_KGDB
-+      int rs_putDebugChar(char);
-+      char rs_getDebugChar(void);
-+      extern int (*generic_putDebugChar)(char);
-+      extern char (*generic_getDebugChar)(void);
++    return(p_set_mdix_on_chip_fn ? 1:0);
++}
++
++EXPORT_SYMBOL(avalanche_reset_ctrl);
++EXPORT_SYMBOL(avalanche_get_reset_status);
++EXPORT_SYMBOL(avalanche_sys_reset);
++EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
++EXPORT_SYMBOL(avalanche_power_ctrl);
++EXPORT_SYMBOL(avalanche_get_power_status);
++EXPORT_SYMBOL(avalanche_set_global_power_mode);
++EXPORT_SYMBOL(avalanche_get_global_power_mode);
++EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
++EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
++
++EXPORT_SYMBOL(avalanche_gpio_init);
++EXPORT_SYMBOL(avalanche_gpio_ctrl);
++EXPORT_SYMBOL(avalanche_gpio_out_bit);
++EXPORT_SYMBOL(avalanche_gpio_in_bit);
++EXPORT_SYMBOL(avalanche_gpio_out_value);
++EXPORT_SYMBOL(avalanche_gpio_in_value);
++
++EXPORT_SYMBOL(avalanche_set_vbus_freq);
++EXPORT_SYMBOL(avalanche_get_vbus_freq);
++
++EXPORT_SYMBOL(avalanche_get_chip_version_info);
++
+diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
+--- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/platform.h 2005-08-12 19:34:07.216666616 +0200
+@@ -0,0 +1,65 @@
++#ifndef _PLATFORM_H_
++#define _PLATFORM_H_
++
++#include <linux/config.h>
++
++
++/* Important: The definition of ENV_SPACE_SIZE should match with that in
++ * PSPBoot. (/psp_boot/inc/psbl/env.h)
++ */
++#ifdef CONFIG_MIPS_AVALANCHE_TICFG
++#define ENV_SPACE_SIZE      (10 * 1024)

 +#endif
 +#endif

-+      char *argptr;

 +
 +

-+#ifdef CONFIG_SERIAL_CONSOLE
-+      argptr = prom_getcmdline();
-+      if ((argptr = strstr(argptr, "console=")) == NULL) {
-+              argptr = prom_getcmdline();
-+              strcat(argptr, " console=ttyS0,38400");
-+      }
++#ifdef CONFIG_MIPS_TNETV1050SDB
++#define TNETV1050SDB
++#define DUAL_FLASH

 +#endif
 +
 +#endif
 +

-+#ifdef CONFIG_KGDB
-+      argptr = prom_getcmdline();
-+      if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
-+              int line;
-+              argptr += strlen("kgdb=ttyS");
-+              if (*argptr != '0' && *argptr != '1')
-+                      printk("KGDB: Uknown serial line /dev/ttyS%c, "
-+                                      "falling back to /dev/ttyS1\n", *argptr);
-+              line = *argptr == '0' ? 0 : 1;
-+              printk("KGDB: Using serial line /dev/ttyS%d for session\n",
-+                              line ? 1 : 0);
++#ifdef CONFIG_MIPS_AR7DB
++#define TNETD73XX_BOARD
++#define AR7DB
++#endif

 +
 +

-+              rs_kgdb_hook(line);
-+              generic_putDebugChar = rs_putDebugChar;
-+              generic_getDebugChar = rs_getDebugChar;
++#ifdef CONFIG_MIPS_AR7RD
++#define TNETD73XX_BOARD
++#define AR7RD
++#endif

 +
 +

-+              prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
-+                              "please connect your debugger\n", line ? 1 : 0);
++#ifdef CONFIG_AR7WRD
++#define TNETD73XX_BOARD
++#define AR7WRD
++#endif

 +
 +

-+              remote_debug = 1;
-+              /* Breakpoints are in init_IRQ() */
-+      }
++#ifdef CONFIG_MIPS_AR7VWI
++#define TNETD73XX_BOARD
++#define AR7VWi

 +#endif
 +
 +#endif
 +

-+      argptr = prom_getcmdline();
-+      if ((argptr = strstr(argptr, "nofpu")) != NULL)
-+              cpu_data[0].options &= ~MIPS_CPU_FPU;
++/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
++#ifdef CONFIG_MIPS_AR7VW
++#define TNETD73XX_BOARD
++#define AR7WRD
++#endif

 +
 +

-+      rtc_ops = &no_rtc_ops;
++#ifdef CONFIG_MIPS_AR7WI
++#define TNETD73XX_BOARD
++#define AR7Wi
++#endif

 +
 +

-+      ar7_platform_init();
++#ifdef CONFIG_MIPS_AR7V
++#define TNETD73XX_BOARD
++#define AR7V
++#endif

 +
 +

-+      ar7_reboot_setup();
++#ifdef CONFIG_MIPS_AR7V
++#define TNETD73XX_BOARD
++#define AR7V
++#endif

 +
 +

-+      board_time_init = ar7_time_init;
-+      board_timer_setup = ar7_timer_setup;
-+}
-diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.dev/arch/mips/ar7/time.c
---- linux-2.4.30/arch/mips/ar7/time.c  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/time.c      2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,125 @@
++#ifdef CONFIG_MIPS_WA1130
++#define AVALANCHE
++#define WLAN
++#endif
++
++#endif
+diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
+--- linux.old/arch/mips/ar7/printf.c   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/printf.c   2005-08-12 19:32:05.139225208 +0200
+@@ -0,0 +1,53 @@

 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 + *
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 + *

-+ * ########################################################################
-+ *

 + *  This program is free software; you can distribute it and/or modify it
 + *  under the terms of the GNU General Public License (Version 2) as
 + *  published by the Free Software Foundation.
 + *  This program is free software; you can distribute it and/or modify it
 + *  under the terms of the GNU General Public License (Version 2) as
 + *  published by the Free Software Foundation.


@@ -1891,2150 +1655,2096 @@ diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.dev/arch/mips/ar7/time.
 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 + *
 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 + *

-+ * ########################################################################
-+ *
-+ * Setting up the clock on the MIPS boards.
-+ *
++ * Putting things on the screen/serial line using Adam2 facilities.

 + */
 +
 + */
 +

-+#include <linux/types.h>

 +#include <linux/config.h>
 +#include <linux/init.h>
 +#include <linux/config.h>
 +#include <linux/init.h>

-+#include <linux/kernel_stat.h>
-+#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/serial_reg.h>

 +#include <linux/spinlock.h>
 +#include <linux/spinlock.h>

++#include <asm/io.h>
++#include <asm/serial.h>
++#include <asm/addrspace.h>

 +
 +

-+#include <asm/mipsregs.h>
-+#include <asm/ptrace.h>
-+#include <asm/hardirq.h>
-+#include <asm/div64.h>
-+
-+#include <linux/interrupt.h>
-+#include <linux/mc146818rtc.h>
-+#include <linux/timex.h>
++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)

 +
 +

-+#include <asm/mips-boards/generic.h>
-+#include <asm/mips-boards/prom.h>
-+#include <asm/ar7/ar7.h>
++static char ppbuf[1024];

 +
 +

-+extern asmlinkage void mipsIRQ(void);
++void (*prom_print_str)(unsigned int out, char *s, int len);

 +
 +

-+static unsigned long r4k_offset; /* Amount to increment compare reg each time */
-+static unsigned long r4k_cur;    /* What counter should be at next timer irq */
-+
-+#define MIPS_CPU_TIMER_IRQ 7
-+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-+
-+static inline void ack_r4ktimer(unsigned long newval)
-+{
-+      write_c0_compare(newval);
-+}
-+
-+void ar7_timer_interrupt(struct pt_regs *regs)
++void prom_printf(char *fmt, ...) __init;
++void prom_printf(char *fmt, ...)

 +{
 +{

-+      int cpu = smp_processor_id();
-+
-+      irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
-+
-+      if (r4k_offset == 0)
-+              goto null;
-+
-+      do {
-+              kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
-+              do_timer(regs);
-+              r4k_cur += r4k_offset;
-+              ack_r4ktimer(r4k_cur);
-+
-+      } while (((unsigned long)read_c0_count()
-+                              - r4k_cur) < 0x7fffffff);
++      va_list args;
++      int len;
++      prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;

 +
 +

-+      irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
++      va_start(args, fmt);
++      vsprintf(ppbuf, fmt, args);
++      len = strlen(ppbuf);

 +
 +

-+      if (softirq_pending(cpu))
-+              do_softirq();
++      prom_print_str(1, ppbuf, len);

 +
 +

++      va_end(args);

 +      return;
 +
 +      return;
 +

-+null:
-+      ack_r4ktimer(0);
-+}
-+
-+/*
-+ * Figure out the r4k offset, the amount to increment the compare
-+ * register for each time tick.
-+ */
-+static unsigned long __init cal_r4koff(void)
-+{
-+      return ((CONFIG_AR7_FREQUENCY*500000)/HZ);

 +}
 +}

+diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
+--- linux.old/arch/mips/ar7/psp_env.c  1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/psp_env.c  2005-08-12 19:34:07.216666616 +0200
+@@ -0,0 +1,350 @@
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <asm/io.h>

 +
 +

-+void __init ar7_time_init(void)
-+{
-+      unsigned long flags;
-+      unsigned int est_freq; 
++#include "platform.h"

 +
 +

-+      set_except_vector(0, mipsIRQ);
-+      write_c0_count(0);
++#define ENV_CELL_SIZE           16

 +
 +

-+      printk("calculating r4koff... ");
-+      r4k_offset = cal_r4koff();
-+      printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
++/* control field decode */
++#define ENV_GARBAGE_BIT                 0x01    /* Env is garbage if this bit is off */
++#define ENV_DYNAMIC_BIT                 0x02    /* Env is dynamic if this bit is off */

 +
 +

-+      est_freq = 2*r4k_offset*HZ;
-+      est_freq += 5000;    /* round */
-+      est_freq -= est_freq%10000;
-+      printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
-+                      (est_freq%1000000)*100/1000000);
-+}
++#define ENV_CTRL_MASK                   0x03
++#define ENV_PREFINED                    (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
++#define ENV_DYNAMIC                     (ENV_GARBAGE_BIT)

 +
 +

-+void __init ar7_timer_setup(struct irqaction *irq)
-+{
-+      /* we are using the cpu counter for timer interrupts */
-+      irq->handler = no_action;     /* we use our own handler */
-+      setup_irq(MIPS_CPU_TIMER_IRQ, irq);
++struct env_variable {
++    unsigned char   varNum;
++    unsigned char   ctrl;
++    unsigned short  chksum;
++    unsigned char   numCells;
++    unsigned char   data[ENV_CELL_SIZE - 5];    /* The data section starts
++                                                 * here, continues for
++                                                 * numCells.
++                                                 */
++};

 +
 +

-+      r4k_cur = (read_c0_count() + r4k_offset);
-+      write_c0_compare(r4k_cur);
-+      set_c0_status(ALLINTS);
-+}
-diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c
---- linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c    2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,924 @@
-+/******************************************************************************
-+ * FILE PURPOSE:    TNETD73xx Misc modules API Source
-+ ******************************************************************************
-+ * FILE NAME:       tnetd73xx_misc.c
-+ *
-+ * DESCRIPTION:     Clock Control, Reset Control, Power Management, GPIO
-+ *                  FSER Modules API
-+ *                  As per TNETD73xx specifications
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - Sharath Kumar     PSP TII  
-+ * 14 Feb 03 - Anant Gole        PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
++extern unsigned int max_env_entry;
++
++/* Internal macros */
++#define get_next_block(var)    ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
++
++typedef enum ENV_VARS {
++        env_vars_start = 0,
++        CPUFREQ,
++        MEMSZ,
++        FLASHSZ,
++        MODETTY0,
++        MODETTY1,
++        PROMPT,
++        BOOTCFG,
++        HWA_0,
++#if !defined (AVALANCHE) || defined(TNETC401B)
++        HWA_1,
++#endif
++#if !defined(TNETV1020_BOARD)
++        HWA_RNDIS,
++#endif
++#if defined (TNETD73XX_BOARD)
++        HWA_3,
++#endif
++        IPA,
++        IPA_SVR,
++        BLINE_MAC0,
++#if !defined (AVALANCHE) || defined(TNETC401B)
++        BLINE_MAC1,
++#endif
++#if !defined(TNETV1020_BOARD)
++        BLINE_RNDIS,
++#endif
++#if defined (TNETD73XX_BOARD)
++        BLINE_ATM,
++#endif
++#if !defined(TNETV1020_BOARD)
++        USB_PID,
++        USB_VID,
++        USB_EPPOLLI,
++#endif
++        IPA_GATEWAY,
++        SUBNET_MASK,
++#if defined (TNETV1050_BOARD)
++      BLINE_ESWITCH,
++#endif
++#if !defined(TNETV1020_BOARD)
++      USB_SERIAL,
++      HWA_HRNDIS,      /* Host (PC) side RNDIS address */
++#endif
++      REMOTE_USER,
++      REMOTE_PASS,
++      REMOTE_DIR,
++      SYSFREQ,
++      LINK_TIMEOUT,
++#ifndef AVALANCHE     /* Avalanche boards use only one mac port */
++      MAC_PORT,
++#endif
++      PATH,
++      HOSTNAME,
++#ifdef WLAN
++      HW_REV_MAJOR,
++      HW_REV_MINOR,
++      HW_PATCH,
++      SW_PATCH,
++      SERIAL_NUMBER,
++#endif
++      TFTPCFG,
++#if defined (TNETV1050_BOARD)
++      HWA_ESWITCH,
++#endif
++        /*
++         * Add new env variables here.
++         * NOTE: New environment variables should always be placed at the end, ie
++         *       just before env_vars_end.
++         */

 +
 +

-+#define LITTLE_ENDIAN
-+#define _LINK_KSEG0_
++        env_vars_end
++} ENV_VARS;

 +
 +

-+#include <linux/types.h>
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>

 +
 +

-+/* TNETD73XX Revision */
-+u32 tnetd73xx_get_revision(void)
-+{
-+      /* Read Chip revision register - This register is from GPIO module */
-+      return ( (u32) REG32_DATA(TNETD73XX_CVR));
-+}
++struct env_description {
++        ENV_VARS   idx;
++        char      *nm;
++      char      *alias;
++};

 +
 +

-+/*****************************************************************************
-+ * Reset Control Module
-+ *****************************************************************************/
++#define ENVSTR(x)         #x
++#define _ENV_ENTRY(x)     {.idx = x, .nm = ENVSTR(x), .alias = NULL}
++
++struct env_description env_ns[] = {
++        _ENV_ENTRY(env_vars_start), /* start. */
++        _ENV_ENTRY(CPUFREQ),
++        _ENV_ENTRY(MEMSZ),
++        _ENV_ENTRY(FLASHSZ),
++        _ENV_ENTRY(MODETTY0),
++        _ENV_ENTRY(MODETTY1),
++        _ENV_ENTRY(PROMPT),
++        _ENV_ENTRY(BOOTCFG),
++        _ENV_ENTRY(HWA_0),
++#if !defined (AVALANCHE) || defined(TNETC401B)
++        _ENV_ENTRY(HWA_1),
++#endif
++#if !defined(TNETV1020_BOARD)
++        _ENV_ENTRY(HWA_RNDIS),
++#endif
++#if defined (TNETD73XX_BOARD)
++        _ENV_ENTRY(HWA_3),
++#endif
++        _ENV_ENTRY(IPA),
++        _ENV_ENTRY(IPA_SVR),
++        _ENV_ENTRY(IPA_GATEWAY),
++        _ENV_ENTRY(SUBNET_MASK),
++        _ENV_ENTRY(BLINE_MAC0),
++#if !defined (AVALANCHE) || defined(TNETC401B)
++        _ENV_ENTRY(BLINE_MAC1),
++#endif
++#if !defined(TNETV1020_BOARD)
++        _ENV_ENTRY(BLINE_RNDIS),
++#endif
++#if defined (TNETD73XX_BOARD)
++        _ENV_ENTRY(BLINE_ATM),
++#endif
++#if !defined(TNETV1020_BOARD)
++        _ENV_ENTRY(USB_PID),
++        _ENV_ENTRY(USB_VID),
++        _ENV_ENTRY(USB_EPPOLLI),
++#endif
++#if defined (TNETV1050_BOARD)
++        _ENV_ENTRY(BLINE_ESWITCH),
++#endif
++#if !defined(TNETV1020_BOARD)
++        _ENV_ENTRY(USB_SERIAL),
++        _ENV_ENTRY(HWA_HRNDIS),
++#endif
++      _ENV_ENTRY(REMOTE_USER),
++      _ENV_ENTRY(REMOTE_PASS),
++      _ENV_ENTRY(REMOTE_DIR),
++      _ENV_ENTRY(SYSFREQ),
++      _ENV_ENTRY(LINK_TIMEOUT),
++#ifndef AVALANCHE       /* Avalanche boards use only one mac port */
++      _ENV_ENTRY(MAC_PORT),
++#endif
++      _ENV_ENTRY(PATH),
++      _ENV_ENTRY(HOSTNAME),
++#ifdef WLAN
++      _ENV_ENTRY(HW_REV_MAJOR),
++      _ENV_ENTRY(HW_REV_MINOR),
++      _ENV_ENTRY(HW_PATCH),
++      _ENV_ENTRY(SW_PATCH),
++      _ENV_ENTRY(SERIAL_NUMBER),
++#endif
++      _ENV_ENTRY(TFTPCFG),
++#if defined (TNETV1050_BOARD)
++      _ENV_ENTRY(HWA_ESWITCH),
++#endif
++        /*
++         * Add new entries below this.
++         */
++      /* Adam2 environment name alias. */
++      { .idx = IPA,      .nm = "my_ipaddress" },
++      { .idx = CPUFREQ,  .nm = "cpufrequency" },
++      { .idx = SYSFREQ,  .nm = "sysfrequency" },
++      { .idx = HWA_0,    .nm = "maca" },
++#ifndef AVALANCHE
++      { .idx = HWA_1,    .nm = "macb" },
++#endif
++        { .idx = MODETTY0, .nm = "modetty0" },
++        { .idx = MODETTY1, .nm = "modetty1" },
++      { .idx = MEMSZ,    .nm = "memsize" },

 +
 +

++        _ENV_ENTRY(env_vars_end) /* delimiter. */
++};

 +
 +

-+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
++static inline int var_to_idx(const char* var)

 +{
 +{

-+      u32 reset_status;
++      int ii;

 +
 +

-+      /* read current reset register */
-+      REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++      /* go over the list of pre-defined environment variables */
++        for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
++              /* check if the env variable is listed */
++                if (strcmp(env_ns[ii].nm, var) == 0) {
++                              return env_ns[ii].idx;
++              }

 +
 +

-+      if (reset_ctrl == OUT_OF_RESET)
-+      {
-+              /* bring module out of reset */
-+              reset_status |= (1 << reset_module);
-+      }
-+      else
-+      {
-+              /* put module in reset */
-+              reset_status &= (~(1 << reset_module));
++              /* if an alias is present, check if the alias matches
++               * the description
++               */
++              if (env_ns[ii].alias != NULL) {
++                      if (strcmp(env_ns[ii].alias, var) == 0) {
++                              return env_ns[ii].idx;
++                      }
++              }

 +      }
 +      }

-+
-+      /* write to the reset register */
-+      REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
++      return 0;

 +}
 +
 +}
 +

++extern int *_prom_envp;

 +
 +

-+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
-+{
-+      u32 reset_status;
-+
-+      REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+      return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
-+}
++/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
++ *        the next read some seconds later is ok. It looks like something is hidding or
++ *        overlay the flash address at 0xb0000000. Is this possible?
++ *
++ *        The readb() and while() usage below is a attempt of a workarround - with limited success.
++ */

 +
 +

-+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
++static inline struct env_variable* get_var_by_number(int index)

 +{
 +{

-+      REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
-+}
++      struct env_variable *env_var = (struct env_variable *)_prom_envp;
++      volatile unsigned char nr;
++      int i;

 +
 +

-+#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
++      env_var++;              /* skip signature */

 +
 +

-+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
-+{
-+      u32 sys_reset_status;
++      i = 0;
++      nr = readb(&(env_var->varNum));

 +
 +

-+      REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
++      while (i < max_env_entry && nr != 0xFF) {
++              if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
++                      if (nr == index) {
++                              return env_var;
++                      }
++              }
++              i++;
++              env_var = get_next_block(env_var);
++              nr = readb(&(env_var->varNum));
++        }

 +
 +

-+      return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
++      return NULL;

 +}
 +
 +}
 +

-+
-+/*****************************************************************************
-+ * Power Control Module
-+ *****************************************************************************/
-+#define TNETD73XX_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
-+#define TNETD73XX_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */
-+
-+
-+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
++static inline struct env_variable* get_var_by_name(char *var)

 +{
 +{

-+      u32 power_status;
++      struct env_variable *env_var = (struct env_variable *)_prom_envp;
++      volatile unsigned char nr;
++      int i;

 +
 +

-+      /* read current power down control register */
-+      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++      env_var++;              /* skip signature */

 +
 +

-+      if (power_ctrl == POWER_CTRL_POWER_DOWN)
-+      {
-+              /* power down the module */
-+              power_status |= (1 << power_module);
-+      }
-+      else
-+      {
-+              /* power on the module */
-+              power_status &= (~(1 << power_module));
-+      }
++      nr = readb(&(env_var->varNum));
++      i = 0;

 +
 +

-+      /* write to the reset register */
-+      REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
++      while (i < max_env_entry && nr != 0xFF) {
++              if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
++                      if (strcmp(var, env_var->data) == 0)
++                              return env_var;
++              }
++              i++;
++              env_var = get_next_block(env_var);
++              nr = readb(&(env_var->varNum));
++        }
++      return NULL;

 +}
 +
 +}
 +

-+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
++static inline struct env_variable* get_var(char *var)

 +{
 +{

-+      u32 power_status;
++      int index = var_to_idx(var);

 +
 +

-+      /* read current power down control register */
-+      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++      if (index)
++              return get_var_by_number(index);
++      else
++              return get_var_by_name(var);

 +
 +

-+      return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
++      return NULL;

 +}
 +
 +}
 +

-+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
++static inline char *get_value(struct env_variable* env_var)

 +{
 +{

-+      u32 power_status;
++      unsigned char *name;
++      unsigned char *value;
++      unsigned short chksum;
++      int i;

 +
 +

-+      /* read current power down control register */
-+      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++      chksum = env_var->varNum + env_var->ctrl + env_var->numCells;

 +
 +

-+      power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
-+      power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
++      if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
++              name  = env_var->data;
++              value = env_var->data + strlen(name) + 1;

 +
 +

-+      /* write to power down control register */
-+      REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
++              for(i = 0; i < strlen(name); i++)
++                      chksum += name[i];
++      } else
++              value = env_var->data;

 +
 +

-+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
-+{
-+      u32 power_status;
++      for (i = 0; i < strlen(value); i++)
++              chksum += value[i];

 +
 +

-+      /* read current power down control register */
-+      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++      chksum += env_var->chksum;
++      chksum = ~(chksum);

 +
 +

-+      power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
-+      power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
++      if(chksum != 0) {
++              return NULL;
++      }

 +
 +

-+      return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
++      return value;

 +}
 +
 +}
 +

++struct psbl_rec {
++    unsigned int psbl_size;
++    unsigned int env_base;
++    unsigned int env_size;
++    unsigned int ffs_base;
++    unsigned int ffs_size;
++};

 +
 +

-+/*****************************************************************************
-+ * Wakeup Control
-+ *****************************************************************************/
++char *prom_psp_getenv(char *envname)
++{
++    struct env_variable* env_var;
++    char *value;

 +
 +

-+#define TNETD73XX_WAKEUP_POLARITY_BIT   16
++    if (strcmp("bootloader", envname) == 0)
++          return "PSPBoot";

 +
 +

-+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
-+              TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
-+              TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
-+{
-+      u32 wakeup_status;
++    if (!(env_var = get_var(envname)))
++          return NULL;

 +
 +

-+      /* read the wakeup control register */
-+      REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++    value = get_value(env_var);

 +
 +

-+      /* enable/disable */
-+      if (wakeup_ctrl == WAKEUP_ENABLED)
-+      {
-+              /* enable wakeup */
-+              wakeup_status |= wakeup_int;
-+      }
-+      else
-+      {
-+              /* disable wakeup */
-+              wakeup_status &= (~wakeup_int);
-+      }
++    return value;
++}
+diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
+--- linux.old/arch/mips/ar7/reset.c    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/reset.c    2005-08-12 19:32:05.139225208 +0200
+@@ -0,0 +1,56 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
++ *
++ * ########################################################################
++ *
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Reset the MIPS boards.
++ *
++ */
++#include <linux/config.h>

 +
 +

-+      /* set polarity */
-+      if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
-+      {
-+              wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+      }
-+      else
-+      {
-+              wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+      }
++#include <asm/reboot.h>
++#include <asm/mips-boards/generic.h>

 +
 +

-+      /* write  the wakeup control register */
-+      REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
-+}
++static void ar7_machine_restart(char *command);
++static void ar7_machine_halt(void);
++static void ar7_machine_power_off(void);

 +
 +

++static void ar7_machine_restart(char *command)
++{
++      volatile unsigned int *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));

 +
 +

-+/*****************************************************************************
-+ * FSER  Control
-+ *****************************************************************************/
++      *softres_reg = 1;
++}

 +
 +

-+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
++static void ar7_machine_halt(void)

 +{
 +{

-+      REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
++

 +}
 +
 +}
 +

-+/*****************************************************************************
-+ * Clock Control
-+ *****************************************************************************/
++static void ar7_machine_power_off(void)
++{

 +
 +

-+#define MIN(x,y)               ( ((x) <  (y)) ? (x) : (y) )
-+#define MAX(x,y)               ( ((x) >  (y)) ? (x) : (y) )
-+#define ABS(x)                 ( ((signed)(x) > 0) ? (x) : (-(x)) )
-+#define CEIL(x,y)              ( ((x) + (y) / 2) / (y) )
++}

 +
 +

-+#define CLKC_CLKCR(x)          (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
-+#define CLKC_CLKPLLCR(x)       (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
++void ar7_reboot_setup(void)
++{
++      _machine_restart = ar7_machine_restart;
++      _machine_halt = ar7_machine_halt;
++      _machine_power_off = ar7_machine_power_off;
++}
+diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
+--- linux.old/arch/mips/ar7/setup.c    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/setup.c    2005-08-12 19:32:05.139225208 +0200
+@@ -0,0 +1,120 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
++ *
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/mc146818rtc.h>
++#include <linux/ioport.h>

 +
 +

-+#define CLKC_PRE_DIVIDER        0x0000001F
-+#define CLKC_POST_DIVIDER       0x001F0000
++#include <asm/cpu.h>
++#include <asm/bootinfo.h>
++#include <asm/irq.h>
++#include <asm/mips-boards/generic.h>
++#include <asm/mips-boards/prom.h>

 +
 +

-+#define CLKC_PLL_STATUS         0x1
-+#define CLKC_PLL_FACTOR         0x0000F000
++#include <asm/dma.h>
++#include <asm/time.h>
++#include <asm/traps.h>

 +
 +

-+#define BOOTCR_PLL_BYPASS       (1 << 5)
-+#define BOOTCR_MIPS_ASYNC_MODE  (1 << 25)
++#ifdef CONFIG_KGDB
++extern void rs_kgdb_hook(int);
++int remote_debug = 0;
++#endif

 +
 +

-+#define MIPS_PLL_SELECT         0x00030000
-+#define SYSTEM_PLL_SELECT       0x0000C000
-+#define USB_PLL_SELECT          0x000C0000
-+#define ADSLSS_PLL_SELECT       0x00C00000
++extern struct rtc_ops no_rtc_ops;

 +
 +

-+#define MIPS_AFECLKI_SELECT     0x00000000
-+#define MIPS_REFCLKI_SELECT     0x00010000
-+#define MIPS_XTAL3IN_SELECT     0x00020000
++extern void ar7_reboot_setup(void);

 +
 +

-+#define SYSTEM_AFECLKI_SELECT   0x00000000
-+#define SYSTEM_REFCLKI_SELECT   0x00004000
-+#define SYSTEM_XTAL3IN_SELECT   0x00008000
-+#define SYSTEM_MIPSPLL_SELECT   0x0000C000
++extern void ar7_time_init(void);
++extern void ar7_timer_setup(struct irqaction *irq);

 +
 +

-+#define USB_SYSPLL_SELECT       0x00000000
-+#define USB_REFCLKI_SELECT      0x00040000
-+#define USB_XTAL3IN_SELECT      0x00080000
-+#define USB_MIPSPLL_SELECT      0x000C0000
++const char *get_system_type(void)
++{
++      return "Texas Instruments AR7";
++}

 +
 +

-+#define ADSLSS_AFECLKI_SELECT   0x00000000
-+#define ADSLSS_REFCLKI_SELECT   0x00400000
-+#define ADSLSS_XTAL3IN_SELECT   0x00800000
-+#define ADSLSS_MIPSPLL_SELECT   0x00C00000
++void __init ar7_setup(void)
++{
++#ifdef CONFIG_KGDB
++      int rs_putDebugChar(char);
++      char rs_getDebugChar(void);
++      extern int (*generic_putDebugChar)(char);
++      extern char (*generic_getDebugChar)(void);
++#endif
++      char *argptr;
++#ifdef CONFIG_SERIAL_CONSOLE
++      argptr = prom_getcmdline();
++      if ((argptr = strstr(argptr, "console=")) == NULL) {
++              char console[20];
++              char *s;
++              int i = 0;
++              
++              s = prom_getenv("modetty0");
++              strcpy(console, "38400");
++              
++              if (s != NULL) {
++                      while (s[i] >= '0' && s[i] <= '9')
++                              i++;
++              
++                      if (i > 0) {
++                              strncpy(console, s, i);
++                              console[i] = 0;
++                      }
++              }
++              
++              argptr = prom_getcmdline();
++              strcat(argptr, " console=ttyS0,");
++              strcat(argptr, console);
++      }
++#endif

 +
 +

-+#define  SYS_MAX                CLK_MHZ(150)
-+#define  SYS_MIN                CLK_MHZ(1)
++#ifdef CONFIG_KGDB
++      argptr = prom_getcmdline();
++      if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
++              int line;
++              argptr += strlen("kgdb=ttyS");
++              if (*argptr != '0' && *argptr != '1')
++                      printk("KGDB: Uknown serial line /dev/ttyS%c, "
++                                      "falling back to /dev/ttyS1\n", *argptr);
++              line = *argptr == '0' ? 0 : 1;
++              printk("KGDB: Using serial line /dev/ttyS%d for session\n",
++                              line ? 1 : 0);

 +
 +

-+#define  MIPS_SYNC_MAX          SYS_MAX
-+#define  MIPS_ASYNC_MAX         CLK_MHZ(160)
-+#define  MIPS_MIN               CLK_MHZ(1)
++              rs_kgdb_hook(line);
++              generic_putDebugChar = rs_putDebugChar;
++              generic_getDebugChar = rs_getDebugChar;

 +
 +

-+#define  USB_MAX                CLK_MHZ(100)
-+#define  USB_MIN                CLK_MHZ(1)
++              prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
++                              "please connect your debugger\n", line ? 1 : 0);

 +
 +

-+#define  ADSL_MAX               CLK_MHZ(180)
-+#define  ADSL_MIN               CLK_MHZ(1)
++              remote_debug = 1;
++              /* Breakpoints are in init_IRQ() */
++      }
++#endif

 +
 +

-+#define  PLL_MUL_MAXFACTOR      15
-+#define  MAX_DIV_VALUE          32
-+#define  MIN_DIV_VALUE          1
++      argptr = prom_getcmdline();
++      if ((argptr = strstr(argptr, "nofpu")) != NULL)
++              cpu_data[0].options &= ~MIPS_CPU_FPU;

 +
 +

-+#define  MIN_PLL_INP_FREQ       CLK_MHZ(8)
-+#define  MAX_PLL_INP_FREQ       CLK_MHZ(100)
++      rtc_ops = &no_rtc_ops;

 +
 +

-+#define  DIVIDER_LOCK_TIME      10100
-+#define  PLL_LOCK_TIME          10100 * 75
++      ar7_reboot_setup();

 +
 +

++      board_time_init = ar7_time_init;
++      board_timer_setup = ar7_timer_setup;
++}
+diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
+--- linux.old/arch/mips/ar7/time.c     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/time.c     2005-08-12 23:34:00.272589528 +0200
+@@ -0,0 +1,124 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
++ *
++ * ########################################################################
++ *
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Setting up the clock on the MIPS boards.
++ *
++ */

 +
 +

++#include <linux/types.h>
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel_stat.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>

 +
 +

-+                                                            /****************************************************************************
-+                                                             * DATA PURPOSE:    PRIVATE Variables
-+                                                             **************************************************************************/
-+                                                            static u32 *clk_src[4];
-+                                                            static u32 mips_pll_out;
-+                                                            static u32 sys_pll_out;
-+                                                            static u32 afeclk_inp;
-+                                                            static u32 refclk_inp;
-+                                                            static u32 xtal_inp;
-+                                                            static u32 present_min;
-+                                                            static u32 present_max;
++#include <asm/mipsregs.h>
++#include <asm/ptrace.h>
++#include <asm/hardirq.h>
++#include <asm/div64.h>

 +
 +

-+                                                            /* Forward References */
-+                                                            static u32 find_gcd(u32 min, u32 max);
-+                                                            static u32 compute_prediv( u32 divider, u32 min, u32 max);
-+                                                            static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
-+                                                            static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
-+                                                            static void find_approx(u32 *,u32 *,u32);
++#include <linux/interrupt.h>
++#include <linux/mc146818rtc.h>
++#include <linux/timex.h>

 +
 +

-+                                                            /****************************************************************************
-+                                                             * FUNCTION: tnetd73xx_clkc_init
-+                                                             ****************************************************************************
-+                                                             * Description: The routine initializes the internal variables depending on
-+                                                             *              on the sources selected for different clocks.
-+                                                             ***************************************************************************/
-+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
++#include <asm/mips-boards/generic.h>
++#include <asm/mips-boards/prom.h>
++
++extern asmlinkage void mipsIRQ(void);
++
++static unsigned long r4k_offset; /* Amount to increment compare reg each time */
++static unsigned long r4k_cur;    /* What counter should be at next timer irq */
++
++#define MIPS_CPU_TIMER_IRQ 7
++#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
++
++static inline void ack_r4ktimer(unsigned long newval)

 +{
 +{

++      write_c0_compare(newval);
++}

 +
 +

-+      u32 choice;
++void ar7_timer_interrupt(struct pt_regs *regs)
++{
++      int cpu = smp_processor_id();

 +
 +

-+      afeclk_inp = afeclk;
-+      refclk_inp = refclk;
-+      xtal_inp = xtal3in;
++      irq_enter(cpu, MIPS_CPU_TIMER_IRQ);

 +
 +

-+      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
-+      switch(choice)
-+      {
-+              case MIPS_AFECLKI_SELECT:
-+                      clk_src[CLKC_MIPS] = &afeclk_inp;
-+                      break;
++      if (r4k_offset == 0)
++              goto null;

 +
 +

-+              case MIPS_REFCLKI_SELECT:
-+                      clk_src[CLKC_MIPS] = &refclk_inp;
-+                      break;
++      do {
++              kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
++              do_timer(regs);
++              r4k_cur += r4k_offset;
++              ack_r4ktimer(r4k_cur);

 +
 +

-+              case MIPS_XTAL3IN_SELECT:
-+                      clk_src[CLKC_MIPS] = &xtal_inp;
-+                      break;
++      } while (((unsigned long)read_c0_count()
++                              - r4k_cur) < 0x7fffffff);

 +
 +

-+              default :
-+                      clk_src[CLKC_MIPS] = 0;
++      irq_exit(cpu, MIPS_CPU_TIMER_IRQ);

 +
 +

-+      }
++      if (softirq_pending(cpu))
++              do_softirq();

 +
 +

-+      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
-+      switch(choice)
-+      {
-+              case SYSTEM_AFECLKI_SELECT:
-+                      clk_src[CLKC_SYS] = &afeclk_inp;
-+                      break;
++      return;

 +
 +

-+              case SYSTEM_REFCLKI_SELECT:
-+                      clk_src[CLKC_SYS] = &refclk_inp;
-+                      break;
++null:
++      ack_r4ktimer(0);
++}

 +
 +

-+              case SYSTEM_XTAL3IN_SELECT:
-+                      clk_src[CLKC_SYS] = &xtal_inp;
-+                      break;
++/*
++ * Figure out the r4k offset, the amount to increment the compare
++ * register for each time tick.
++ */
++static unsigned long __init cal_r4koff(void)
++{
++      return ((CONFIG_AR7_CPU*500000)/HZ);
++}

 +
 +

-+              case SYSTEM_MIPSPLL_SELECT:
-+                      clk_src[CLKC_SYS] = &mips_pll_out;
-+                      break;
++void __init ar7_time_init(void)
++{
++      unsigned long flags;
++      unsigned int est_freq; 

 +
 +

-+              default :
-+                      clk_src[CLKC_SYS] = 0;
++      set_except_vector(0, mipsIRQ);
++      write_c0_count(0);

 +
 +

-+      }
++      printk("calculating r4koff... ");
++      r4k_offset = cal_r4koff();
++      printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);

 +
 +

++      est_freq = 2*r4k_offset*HZ;
++      est_freq += 5000;    /* round */
++      est_freq -= est_freq%10000;
++      printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
++                      (est_freq%1000000)*100/1000000);
++}

 +
 +

-+      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
-+      switch(choice)
-+      {
-+              case ADSLSS_AFECLKI_SELECT:
-+                      clk_src[CLKC_ADSLSS] = &afeclk_inp;
-+                      break;
++void __init ar7_timer_setup(struct irqaction *irq)
++{
++      /* we are using the cpu counter for timer interrupts */
++      irq->handler = no_action;     /* we use our own handler */
++      setup_irq(MIPS_CPU_TIMER_IRQ, irq);

 +
 +

-+              case ADSLSS_REFCLKI_SELECT:
-+                      clk_src[CLKC_ADSLSS] = &refclk_inp;
-+                      break;
++      r4k_cur = (read_c0_count() + r4k_offset);
++      write_c0_compare(r4k_cur);
++      set_c0_status(ALLINTS);
++}
+diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
+--- linux.old/arch/mips/ar7/tnetd73xx_misc.c   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c   2005-08-12 19:32:05.140225056 +0200
+@@ -0,0 +1,924 @@
++/******************************************************************************
++ * FILE PURPOSE:    TNETD73xx Misc modules API Source
++ ******************************************************************************
++ * FILE NAME:       tnetd73xx_misc.c
++ *
++ * DESCRIPTION:     Clock Control, Reset Control, Power Management, GPIO
++ *                  FSER Modules API
++ *                  As per TNETD73xx specifications
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - Sharath Kumar     PSP TII  
++ * 14 Feb 03 - Anant Gole        PSP TII
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/

 +
 +

-+              case ADSLSS_XTAL3IN_SELECT:
-+                      clk_src[CLKC_ADSLSS] = &xtal_inp;
-+                      break;
++#define LITTLE_ENDIAN
++#define _LINK_KSEG0_

 +
 +

-+              case ADSLSS_MIPSPLL_SELECT:
-+                      clk_src[CLKC_ADSLSS] = &mips_pll_out;
-+                      break;
++#include <linux/types.h>
++#include <asm/ar7/tnetd73xx.h>
++#include <asm/ar7/tnetd73xx_misc.h>

 +
 +

-+              default :
-+                      clk_src[CLKC_ADSLSS] = 0;
++/* TNETD73XX Revision */
++u32 tnetd73xx_get_revision(void)
++{
++      /* Read Chip revision register - This register is from GPIO module */
++      return ( (u32) REG32_DATA(TNETD73XX_CVR));
++}

 +
 +

-+      }
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/

 +
 +
 +
 +

-+      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
-+      switch(choice)
++void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
++{
++      u32 reset_status;
++
++      /* read current reset register */
++      REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++
++      if (reset_ctrl == OUT_OF_RESET)

 +      {
 +      {

-+              case USB_SYSPLL_SELECT:
-+                      clk_src[CLKC_USB] = &sys_pll_out ;
-+                      break;
++              /* bring module out of reset */
++              reset_status |= (1 << reset_module);
++      }
++      else
++      {
++              /* put module in reset */
++              reset_status &= (~(1 << reset_module));
++      }

 +
 +

-+              case USB_REFCLKI_SELECT:
-+                      clk_src[CLKC_USB] = &refclk_inp;
-+                      break;
++      /* write to the reset register */
++      REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
++}

 +
 +

-+              case USB_XTAL3IN_SELECT:
-+                      clk_src[CLKC_USB] = &xtal_inp;
-+                      break;

 +
 +

-+              case USB_MIPSPLL_SELECT:
-+                      clk_src[CLKC_USB] = &mips_pll_out;
-+                      break;
++TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
++{
++      u32 reset_status;

 +
 +

-+              default :
-+                      clk_src[CLKC_USB] = 0;
++      REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
++      return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
++}

 +
 +

-+      }
++void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
++{
++      REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);

 +}
 +
 +}
 +

++#define TNETD73XX_RST_CTRL_RSR_MASK 0x3

 +
 +

++TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
++{
++      u32 sys_reset_status;

 +
 +

-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_set_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to set the output_frequency of the
-+ *              selected clock(using clk_id) to the  required value given
-+ *              by the variable output_freq.
-+ ***************************************************************************/
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id,
-+ u32              output_freq
-+ )
++      REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
++
++      return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
++}
++
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define TNETD73XX_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
++#define TNETD73XX_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */
++
++
++void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)

 +{
 +{

-+      u32 base_freq;
-+      u32 multiplier;
-+      u32 divider;
-+      u32 min_prediv;
-+      u32 max_prediv;
-+      u32 prediv;
-+      u32 postdiv;
-+      u32 temp;
++      u32 power_status;

 +
 +

-+      /* check if PLLs are bypassed*/
-+      if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
++      /* read current power down control register */
++      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
++
++      if (power_ctrl == POWER_CTRL_POWER_DOWN)

 +      {
 +      {

-+              return TNETD73XX_ERR_ERROR;
++              /* power down the module */
++              power_status |= (1 << power_module);

 +      }
 +      }

-+
-+      /*check if the requested output_frequency is in valid range*/
-+      switch( clk_id )
++      else

 +      {
 +      {

-+              case CLKC_SYS:
-+                      if( output_freq < SYS_MIN || output_freq > SYS_MAX)
-+                      {
-+                              return TNETD73XX_ERR_ERROR;
-+                      }
-+                      present_min = SYS_MIN;
-+                      present_max = SYS_MAX;
-+                      break;
-+
-+              case CLKC_MIPS:
-+                      if((output_freq < MIPS_MIN) ||
-+                                      (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
-+                      {
-+                              return TNETD73XX_ERR_ERROR;
-+                      }
-+                      present_min = MIPS_MIN;
-+                      present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
-+                      break;
++              /* power on the module */
++              power_status &= (~(1 << power_module));
++      }

 +
 +

-+              case CLKC_USB:
-+                      if( output_freq < USB_MIN || output_freq > USB_MAX)
-+                      {
-+                              return TNETD73XX_ERR_ERROR;
-+                      }
-+                      present_min = USB_MIN;
-+                      present_max = USB_MAX;
-+                      break;
++      /* write to the reset register */
++      REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
++}

 +
 +

-+              case CLKC_ADSLSS:
-+                      if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
-+                      {
-+                              return TNETD73XX_ERR_ERROR;
-+                      }
-+                      present_min = ADSL_MIN;
-+                      present_max = ADSL_MAX;
-+                      break;
-+      }
++TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
++{
++      u32 power_status;

 +
 +

++      /* read current power down control register */
++      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);

 +
 +

-+      base_freq = get_base_frequency(clk_id);
++      return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
++}

 +
 +

++void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
++{
++      u32 power_status;

 +
 +

-+      /* check for minimum base frequency value */
-+      if( base_freq < MIN_PLL_INP_FREQ)
-+      {
-+              return TNETD73XX_ERR_ERROR;
-+      }
++      /* read current power down control register */
++      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);

 +
 +

-+      get_val(output_freq, base_freq, &multiplier, &divider);
++      power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
++      power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);

 +
 +

-+      /* check multiplier range  */
-+      if( (multiplier  > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
-+      {
-+              return TNETD73XX_ERR_ERROR;
-+      }
++      /* write to power down control register */
++      REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
++}

 +
 +

-+      /* check divider value */
-+      if( divider == 0 )
-+      {
-+              return TNETD73XX_ERR_ERROR;
-+      }
++TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
++{
++      u32 power_status;

 +
 +

-+      /*compute minimum and maximum predivider values */
-+      min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
-+      max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
++      /* read current power down control register */
++      REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);

 +
 +

-+      /*adjust  the value of divider so that it not less than minimum predivider value*/
-+      if (divider < min_prediv)
-+      {
-+              temp = CEIL(min_prediv, divider);
-+              if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
-+              {
-+                      return TNETD73XX_ERR_ERROR  ;
-+              }
-+              else
-+              {
-+                      multiplier = temp * multiplier;
-+                      divider = min_prediv;
-+              }
++      power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
++      power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);

 +
 +

-+      }
++      return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
++}

 +
 +

-+      /* compute predivider  and postdivider values */
-+      prediv = compute_prediv (divider, min_prediv, max_prediv);
-+      postdiv = CEIL(divider,prediv);

 +
 +

-+      /*return fail if postdivider value falls out of range */
-+      if(postdiv > MAX_DIV_VALUE)
-+      {
-+              return TNETD73XX_ERR_ERROR;
-+      }
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/

 +
 +

++#define TNETD73XX_WAKEUP_POLARITY_BIT   16

 +
 +

-+      /*write predivider and postdivider values*/
-+      /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+      REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
++void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
++              TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
++              TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
++{
++      u32 wakeup_status;

 +
 +

-+      /*wait for divider output to stabilise*/
-+      for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
++      /* read the wakeup control register */
++      REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);

 +
 +

-+      /*write to PLL clock register*/
++      /* enable/disable */
++      if (wakeup_ctrl == WAKEUP_ENABLED)
++      {
++              /* enable wakeup */
++              wakeup_status |= wakeup_int;
++      }
++      else
++      {
++              /* disable wakeup */
++              wakeup_status &= (~wakeup_int);
++      }

 +
 +

-+      if(clk_id == CLKC_SYS)
++      /* set polarity */
++      if (wakeup_polarity == WAKEUP_ACTIVE_LOW)

 +      {
 +      {

-+              /* but before writing put DRAM to hold mode */
-+              REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
++              wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
++      }
++      else
++      {
++              wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);

 +      }
 +      }

-+      /*Bring PLL into div mode */
-+      REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);

 +
 +

-+      /*compute the word to be written to PLLCR
-+       *corresponding to multiplier value
-+       */
-+      multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
++      /* write  the wakeup control register */
++      REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
++}

 +
 +

-+      /* wait till PLL enters div mode */
-+      while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+              /*nothing*/;

 +
 +

-+      REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
++/*****************************************************************************
++ * FSER  Control
++ *****************************************************************************/

 +
 +

-+      while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+              /*nothing*/;
++void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
++{
++      REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
++}

 +
 +

++/*****************************************************************************
++ * Clock Control
++ *****************************************************************************/

 +
 +

-+      /*wait for External pll to lock*/
-+      for(temp =0; temp < PLL_LOCK_TIME; temp++);
++#define MIN(x,y)               ( ((x) <  (y)) ? (x) : (y) )
++#define MAX(x,y)               ( ((x) >  (y)) ? (x) : (y) )
++#define ABS(x)                 ( ((signed)(x) > 0) ? (x) : (-(x)) )
++#define CEIL(x,y)              ( ((x) + (y) / 2) / (y) )

 +
 +

-+      if(clk_id == CLKC_SYS)
-+      {
-+              /* Bring DRAM out of hold */
-+              REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
-+      }
++#define CLKC_CLKCR(x)          (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
++#define CLKC_CLKPLLCR(x)       (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))

 +
 +

-+      return TNETD73XX_ERR_OK ;
-+}
++#define CLKC_PRE_DIVIDER        0x0000001F
++#define CLKC_POST_DIVIDER       0x001F0000

 +
 +

-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_get_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to get the output_frequency of the
-+ *              selected clock( clk_id)
-+ ***************************************************************************/
-+u32 tnetd73xx_clkc_get_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id
-+ )
-+{
++#define CLKC_PLL_STATUS         0x1
++#define CLKC_PLL_FACTOR         0x0000F000

 +
 +

-+      u32  clk_ctrl_register;
-+      u32  clk_pll_setting;
-+      u32  clk_predivider;
-+      u32  clk_postdivider;
-+      u16  pll_factor;
-+      u32  base_freq;
-+      u32  divider;
++#define BOOTCR_PLL_BYPASS       (1 << 5)
++#define BOOTCR_MIPS_ASYNC_MODE  (1 << 25)

 +
 +

-+      base_freq = get_base_frequency(clk_id);
++#define MIPS_PLL_SELECT         0x00030000
++#define SYSTEM_PLL_SELECT       0x0000C000
++#define USB_PLL_SELECT          0x000C0000
++#define ADSLSS_PLL_SELECT       0x00C00000

 +
 +

-+      clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
++#define MIPS_AFECLKI_SELECT     0x00000000
++#define MIPS_REFCLKI_SELECT     0x00010000
++#define MIPS_XTAL3IN_SELECT     0x00020000

 +
 +

-+      /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+      clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
-+      clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
++#define SYSTEM_AFECLKI_SELECT   0x00000000
++#define SYSTEM_REFCLKI_SELECT   0x00004000
++#define SYSTEM_XTAL3IN_SELECT   0x00008000
++#define SYSTEM_MIPSPLL_SELECT   0x0000C000

 +
 +

-+      divider =  clk_predivider * clk_postdivider;
++#define USB_SYSPLL_SELECT       0x00000000
++#define USB_REFCLKI_SELECT      0x00040000
++#define USB_XTAL3IN_SELECT      0x00080000
++#define USB_MIPSPLL_SELECT      0x000C0000

 +
 +

++#define ADSLSS_AFECLKI_SELECT   0x00000000
++#define ADSLSS_REFCLKI_SELECT   0x00400000
++#define ADSLSS_XTAL3IN_SELECT   0x00800000
++#define ADSLSS_MIPSPLL_SELECT   0x00C00000

 +
 +

-+      if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
-+      {
-+              return (CEIL(base_freq, divider));  /* PLLs bypassed.*/
-+      }
++#define  SYS_MAX                CLK_MHZ(150)
++#define  SYS_MIN                CLK_MHZ(1)

 +
 +

++#define  MIPS_SYNC_MAX          SYS_MAX
++#define  MIPS_ASYNC_MAX         CLK_MHZ(160)
++#define  MIPS_MIN               CLK_MHZ(1)

 +
 +

-+      else
-+      {
-+              /*  return the current clock speed based upon the PLL setting */
-+              clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
++#define  USB_MAX                CLK_MHZ(100)
++#define  USB_MIN                CLK_MHZ(1)

 +
 +

-+              /* Get the PLL multiplication factor */
-+              pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
++#define  ADSL_MAX               CLK_MHZ(180)
++#define  ADSL_MIN               CLK_MHZ(1)

 +
 +

-+              /* Check if we're in divide mode or multiply mode */
-+              if((clk_pll_setting & 0x1)   == 0)
-+              {
-+                      /* We're in divide mode */
-+                      if(pll_factor <  0x10)
-+                              return (CEIL(base_freq >> 1, divider));
-+                      else
-+                              return (CEIL(base_freq >> 2, divider));
-+              }
-+
-+              else     /* We're in PLL mode */
-+              {
-+                      /* See if PLLNDIV & PLLDIV are set */
-+                      if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
-+                      {
-+                              if(clk_pll_setting & 0x1000)
-+                              {
-+                                      /* clk = base_freq * k/2  */
-+                                      return(CEIL((base_freq * pll_factor) >> 1, divider));
-+                              }
-+                              else
-+                              {
-+                                      /* clk = base_freq * (k-1) / 4)*/
-+                                      return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
-+                              }
-+                      }
-+                      else
-+                      {
-+                              if(pll_factor < 0x10)
-+                              {
-+                                      /* clk = base_freq * k */
-+                                      return(CEIL(base_freq * pll_factor, divider));
-+                              }
++#define  PLL_MUL_MAXFACTOR      15
++#define  MAX_DIV_VALUE          32
++#define  MIN_DIV_VALUE          1

 +
 +

-+                              else
-+                              {
-+                                      /* clk = base_freq  */
-+                                      return(CEIL(base_freq, divider));
-+                              }
-+                      }
-+              }
-+              return(0); /* Should never reach here */
++#define  MIN_PLL_INP_FREQ       CLK_MHZ(8)
++#define  MAX_PLL_INP_FREQ       CLK_MHZ(100)

 +
 +

-+      }
++#define  DIVIDER_LOCK_TIME      10100
++#define  PLL_LOCK_TIME          10100 * 75

 +
 +

-+}

 +
 +
 +
 +

-+/* local helper functions */
++                                                            /****************************************************************************
++                                                             * DATA PURPOSE:    PRIVATE Variables
++                                                             **************************************************************************/
++                                                            static u32 *clk_src[4];
++                                                            static u32 mips_pll_out;
++                                                            static u32 sys_pll_out;
++                                                            static u32 afeclk_inp;
++                                                            static u32 refclk_inp;
++                                                            static u32 xtal_inp;
++                                                            static u32 present_min;
++                                                            static u32 present_max;

 +
 +

-+/****************************************************************************
-+ * FUNCTION: get_base_frequency
-+ ****************************************************************************
-+ * Description: The above routine is called to get base frequency of the clocks.
-+ ***************************************************************************/
++                                                            /* Forward References */
++                                                            static u32 find_gcd(u32 min, u32 max);
++                                                            static u32 compute_prediv( u32 divider, u32 min, u32 max);
++                                                            static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
++                                                            static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
++                                                            static void find_approx(u32 *,u32 *,u32);

 +
 +

-+static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
++                                                            /****************************************************************************
++                                                             * FUNCTION: tnetd73xx_clkc_init
++                                                             ****************************************************************************
++                                                             * Description: The routine initializes the internal variables depending on
++                                                             *              on the sources selected for different clocks.
++                                                             ***************************************************************************/
++void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)

 +{
 +{

-+      /* update the current MIPs PLL output value, if the required
-+       * source is MIPS PLL
-+       */
-+      if ( clk_src[clk_id] == &mips_pll_out)
-+      {
-+              *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
-+      }

 +
 +

++      u32 choice;

 +
 +

-+      /* update the current System PLL output value, if the required
-+       * source is system PLL
-+       */
-+      if ( clk_src[clk_id] == &sys_pll_out)
-+      {
-+              *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
-+      }
++      afeclk_inp = afeclk;
++      refclk_inp = refclk;
++      xtal_inp = xtal3in;

 +
 +

-+      return (*clk_src[clk_id]);
++      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
++      switch(choice)
++      {
++              case MIPS_AFECLKI_SELECT:
++                      clk_src[CLKC_MIPS] = &afeclk_inp;
++                      break;

 +
 +

-+}
++              case MIPS_REFCLKI_SELECT:
++                      clk_src[CLKC_MIPS] = &refclk_inp;
++                      break;

 +
 +

++              case MIPS_XTAL3IN_SELECT:
++                      clk_src[CLKC_MIPS] = &xtal_inp;
++                      break;

 +
 +

++              default :
++                      clk_src[CLKC_MIPS] = 0;

 +
 +

-+/****************************************************************************
-+ * FUNCTION: find_gcd
-+ ****************************************************************************
-+ * Description: The above routine is called to find gcd of 2 numbers.
-+ ***************************************************************************/
-+static u32 find_gcd
-+(
-+ u32 min,
-+ u32 max
-+ )
-+{
-+      if (max % min == 0)
-+      {
-+              return min;

 +      }
 +      }

-+      else
++
++      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
++      switch(choice)

 +      {
 +      {

-+              return find_gcd(max % min, min);
-+      }
-+}
++              case SYSTEM_AFECLKI_SELECT:
++                      clk_src[CLKC_SYS] = &afeclk_inp;
++                      break;

 +
 +

-+/****************************************************************************
-+ * FUNCTION: compute_prediv
-+ ****************************************************************************
-+ * Description: The above routine is called to compute predivider value
-+ ***************************************************************************/
-+static u32 compute_prediv(u32 divider, u32 min, u32 max)
-+{
-+      u16 prediv;
++              case SYSTEM_REFCLKI_SELECT:
++                      clk_src[CLKC_SYS] = &refclk_inp;
++                      break;

 +
 +

-+      /* return the divider itself it it falls within the range of predivider*/
-+      if (min <= divider && divider <= max)
-+      {
-+              return divider;
-+      }
++              case SYSTEM_XTAL3IN_SELECT:
++                      clk_src[CLKC_SYS] = &xtal_inp;
++                      break;
++
++              case SYSTEM_MIPSPLL_SELECT:
++                      clk_src[CLKC_SYS] = &mips_pll_out;
++                      break;
++
++              default :
++                      clk_src[CLKC_SYS] = 0;

 +
 +

-+      /* find a value for prediv such that it is a factor of divider */
-+      for (prediv = max; prediv >= min ; prediv--)
-+      {
-+              if ( (divider % prediv) == 0 )
-+              {
-+                      return prediv;
-+              }

 +      }
 +
 +      }
 +

-+      /* No such factor exists,  return min as prediv */
-+      return min;
-+}

 +
 +

-+/****************************************************************************
-+ * FUNCTION: get_val
-+ ****************************************************************************
-+ * Description: This routine is called to get values of divider and multiplier.
-+ ***************************************************************************/
++      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
++      switch(choice)
++      {
++              case ADSLSS_AFECLKI_SELECT:
++                      clk_src[CLKC_ADSLSS] = &afeclk_inp;
++                      break;

 +
 +

-+static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
-+{
-+      u32 temp_mul;
-+      u32 temp_div;
-+      u32 gcd;
-+      u32 min_freq;
-+      u32 max_freq;
++              case ADSLSS_REFCLKI_SELECT:
++                      clk_src[CLKC_ADSLSS] = &refclk_inp;
++                      break;

 +
 +

-+      /* find gcd of base_freq, output_freq */
-+      min_freq = (base_freq < output_freq) ? base_freq : output_freq;
-+      max_freq = (base_freq > output_freq) ? base_freq : output_freq;
-+      gcd = find_gcd(min_freq , max_freq);
++              case ADSLSS_XTAL3IN_SELECT:
++                      clk_src[CLKC_ADSLSS] = &xtal_inp;
++                      break;

 +
 +

-+      if(gcd == 0)
-+              return;  /* ERROR */
++              case ADSLSS_MIPSPLL_SELECT:
++                      clk_src[CLKC_ADSLSS] = &mips_pll_out;
++                      break;

 +
 +

-+      /* compute values of multiplier and divider */
-+      temp_mul = output_freq / gcd;
-+      temp_div = base_freq / gcd;
++              default :
++                      clk_src[CLKC_ADSLSS] = 0;

 +
 +

++      }

 +
 +

-+      /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
-+      if( temp_mul > PLL_MUL_MAXFACTOR )
++
++      choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
++      switch(choice)

 +      {
 +      {

-+              if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
-+                      return;
++              case USB_SYSPLL_SELECT:
++                      clk_src[CLKC_USB] = &sys_pll_out ;
++                      break;

 +
 +

-+              find_approx(&temp_mul,&temp_div,base_freq);
-+      }
++              case USB_REFCLKI_SELECT:
++                      clk_src[CLKC_USB] = &refclk_inp;
++                      break;

 +
 +

-+      *multiplier = temp_mul;
-+      *divider    = temp_div;
++              case USB_XTAL3IN_SELECT:
++                      clk_src[CLKC_USB] = &xtal_inp;
++                      break;
++
++              case USB_MIPSPLL_SELECT:
++                      clk_src[CLKC_USB] = &mips_pll_out;
++                      break;
++
++              default :
++                      clk_src[CLKC_USB] = 0;
++
++      }

 +}
 +
 +}
 +

++
++

 +/****************************************************************************
 +/****************************************************************************

-+ * FUNCTION: find_approx
++ * FUNCTION: tnetd73xx_clkc_set_freq

 + ****************************************************************************
 + ****************************************************************************

-+ * Description: This function gets the approx value of num/denom.
++ * Description: The above routine is called to set the output_frequency of the
++ *              selected clock(using clk_id) to the  required value given
++ *              by the variable output_freq.

 + ***************************************************************************/
 + ***************************************************************************/

-+
-+static void find_approx(u32 *num,u32 *denom,u32 base_freq)
++TNETD73XX_ERR tnetd73xx_clkc_set_freq
++(
++ TNETD73XX_CLKC_ID_T clk_id,
++ u32              output_freq
++ )

 +{
 +{

-+      u32 num1;
-+      u32 denom1;
-+      u32 num2;
-+      u32 denom2;
-+      int32_t closest;
-+      int32_t prev_closest;
-+      u32 temp_num;
-+      u32 temp_denom;
-+      u32 normalize;
-+      u32 gcd;
-+      u32 output_freq;
-+
-+      num1 = *num;
-+      denom1 = *denom;
-+
-+      prev_closest = 0x7fffffff; /* maximum possible value */
-+      num2 = num1;
-+      denom2 = denom1;
++      u32 base_freq;
++      u32 multiplier;
++      u32 divider;
++      u32 min_prediv;
++      u32 max_prediv;
++      u32 prediv;
++      u32 postdiv;
++      u32 temp;

 +
 +

-+      /* start with  max */
-+      for(temp_num = 15; temp_num >=1; temp_num--)
++      /* check if PLLs are bypassed*/
++      if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)

 +      {
 +      {

++              return TNETD73XX_ERR_ERROR;
++      }

 +
 +

-+              temp_denom = CEIL(temp_num * denom1, num1);
-+              output_freq = (temp_num * base_freq) / temp_denom;
-+
-+              if(temp_denom < 1)
-+              {
++      /*check if the requested output_frequency is in valid range*/
++      switch( clk_id )
++      {
++              case CLKC_SYS:
++                      if( output_freq < SYS_MIN || output_freq > SYS_MAX)
++                      {
++                              return TNETD73XX_ERR_ERROR;
++                      }
++                      present_min = SYS_MIN;
++                      present_max = SYS_MAX;

 +                      break;
 +                      break;

-+              }
-+              else
-+              {
-+                      normalize = CEIL(num1,temp_num);
-+                      closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1)))  * normalize;
-+                      if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
++
++              case CLKC_MIPS:
++                      if((output_freq < MIPS_MIN) ||
++                                      (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))

 +                      {
 +                      {

-+                              prev_closest = closest;
-+                              num2 = temp_num;
-+                              denom2 = temp_denom;
++                              return TNETD73XX_ERR_ERROR;

 +                      }
 +                      }

++                      present_min = MIPS_MIN;
++                      present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
++                      break;

 +
 +

-+              }
++              case CLKC_USB:
++                      if( output_freq < USB_MIN || output_freq > USB_MAX)
++                      {
++                              return TNETD73XX_ERR_ERROR;
++                      }
++                      present_min = USB_MIN;
++                      present_max = USB_MAX;
++                      break;

 +
 +

++              case CLKC_ADSLSS:
++                      if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
++                      {
++                              return TNETD73XX_ERR_ERROR;
++                      }
++                      present_min = ADSL_MIN;
++                      present_max = ADSL_MAX;
++                      break;

 +      }
 +
 +      }
 +

-+      gcd = find_gcd(num2,denom2);
-+      num2 = num2 / gcd;
-+      denom2 = denom2 /gcd;

 +
 +

-+      *num      = num2;
-+      *denom    = denom2;
-+}
++      base_freq = get_base_frequency(clk_id);

 +
 +
 +
 +

-+/*****************************************************************************
-+ * GPIO  Control
-+ *****************************************************************************/
++      /* check for minimum base frequency value */
++      if( base_freq < MIN_PLL_INP_FREQ)
++      {
++              return TNETD73XX_ERR_ERROR;
++      }

 +
 +

-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_init
-+ ***************************************************************************/
-+void tnetd73xx_gpio_init()
-+{
-+      /* Bring module out of reset */
-+      tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+      REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);    
-+}
++      get_val(output_freq, base_freq, &multiplier, &divider);

 +
 +

-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_ctrl
-+ ***************************************************************************/
-+void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin, 
-+              TNETD73XX_GPIO_PIN_MODE_T pin_mode,
-+              TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
-+{
-+      u32 pin_status;
-+      REG32_READ(TNETD73XX_GPIOENR, pin_status);
-+      if (pin_mode == GPIO_PIN)
++      /* check multiplier range  */
++      if( (multiplier  > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )

 +      {
 +      {

-+              pin_status |= (1 << gpio_pin);
-+              REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++              return TNETD73XX_ERR_ERROR;
++      }

 +
 +

-+              /* Set pin direction */
-+              REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
-+              if (pin_direction == GPIO_INPUT_PIN)
++      /* check divider value */
++      if( divider == 0 )
++      {
++              return TNETD73XX_ERR_ERROR;
++      }
++
++      /*compute minimum and maximum predivider values */
++      min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
++      max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
++
++      /*adjust  the value of divider so that it not less than minimum predivider value*/
++      if (divider < min_prediv)
++      {
++              temp = CEIL(min_prediv, divider);
++              if ((temp * multiplier) > PLL_MUL_MAXFACTOR)

 +              {
 +              {

-+                      pin_status |= (1 << gpio_pin);
++                      return TNETD73XX_ERR_ERROR  ;

 +              }
 +              }

-+              else /* GPIO_OUTPUT_PIN */
++              else

 +              {
 +              {

-+                      pin_status &= (~(1 << gpio_pin));
++                      multiplier = temp * multiplier;
++                      divider = min_prediv;

 +              }
 +              }

-+              REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
++

 +      }
 +      }

-+      else /* FUNCTIONAL PIN */
++
++      /* compute predivider  and postdivider values */
++      prediv = compute_prediv (divider, min_prediv, max_prediv);
++      postdiv = CEIL(divider,prediv);
++
++      /*return fail if postdivider value falls out of range */
++      if(postdiv > MAX_DIV_VALUE)

 +      {
 +      {

-+              pin_status &= (~(1 << gpio_pin));
-+              REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++              return TNETD73XX_ERR_ERROR;

 +      }
 +
 +      }
 +

-+}

 +
 +

-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_out
-+ ***************************************************************************/
-+void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
-+{
-+      u32 pin_value;
++      /*write predivider and postdivider values*/
++      /* pre-Divider and post-divider are 5 bit N+1 dividers */
++      REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );

 +
 +

-+      REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
-+      if (value == 1)
++      /*wait for divider output to stabilise*/
++      for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
++
++      /*write to PLL clock register*/
++
++      if(clk_id == CLKC_SYS)

 +      {
 +      {

-+              pin_value |= (1 << gpio_pin);
++              /* but before writing put DRAM to hold mode */
++              REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;

 +      }
 +      }

-+      else
++      /*Bring PLL into div mode */
++      REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
++
++      /*compute the word to be written to PLLCR
++       *corresponding to multiplier value
++       */
++      multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
++
++      /* wait till PLL enters div mode */
++      while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
++              /*nothing*/;
++
++      REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
++
++      while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
++              /*nothing*/;
++
++
++      /*wait for External pll to lock*/
++      for(temp =0; temp < PLL_LOCK_TIME; temp++);
++
++      if(clk_id == CLKC_SYS)

 +      {
 +      {

-+              pin_value &= (~(1 << gpio_pin));
++              /* Bring DRAM out of hold */
++              REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;

 +      }
 +      }

-+      REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
++
++      return TNETD73XX_ERR_OK ;

 +}
 +
 +/****************************************************************************
 +}
 +
 +/****************************************************************************

-+ * FUNCTION: tnetd73xx_gpio_in
++ * FUNCTION: tnetd73xx_clkc_get_freq
++ ****************************************************************************
++ * Description: The above routine is called to get the output_frequency of the
++ *              selected clock( clk_id)

 + ***************************************************************************/
 + ***************************************************************************/

-+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
++u32 tnetd73xx_clkc_get_freq
++(
++ TNETD73XX_CLKC_ID_T clk_id
++ )

 +{
 +{

-+      u32 pin_value;
-+      REG32_READ(TNETD73XX_GPIODINR, pin_value);
-+      return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
-+}

 +
 +

-diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.dev/arch/mips/config-shared.in
---- linux-2.4.30/arch/mips/config-shared.in    2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/config-shared.in        2005-06-14 15:36:59.000000000 +0200
-@@ -20,6 +20,15 @@
- mainmenu_option next_comment
- comment 'Machine selection'
- dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
-+dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
-+if [ "$CONFIG_AR7" = "y" ]; then
-+   choice 'Texas Instruments Reference Platform' \
-+      "AR7DB CONFIG_AR7DB \
-+      AR7RD CONFIG_AR7RD \
-+      AR7WRD CONFIG_AR7WRD" AR7DB
-+   int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
-+   hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
-+fi
- dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
- dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
- dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
-@@ -239,6 +248,11 @@
-    define_bool CONFIG_NONCOHERENT_IO y
-    define_bool CONFIG_PC_KEYB y
- fi
-+if [ "$CONFIG_AR7" = "y" ]; then
-+   define_bool CONFIG_NONCOHERENT_IO y
-+   define_bool CONFIG_SWAP_IO_SPACE y
-+   define_bool CONFIG_AR7_PAGING y
-+fi
- if [ "$CONFIG_CASIO_E55" = "y" ]; then
-    define_bool CONFIG_IRQ_CPU y
-    define_bool CONFIG_NONCOHERENT_IO y
-@@ -736,6 +750,7 @@
- mainmenu_option next_comment
- comment 'General setup'
- if [ "$CONFIG_ACER_PICA_61" = "y" -o \
-+     "$CONFIG_AR7" = "y" -o \
-      "$CONFIG_CASIO_E55" = "y" -o \
-      "$CONFIG_DDB5074" = "y" -o \
-      "$CONFIG_DDB5476" = "y" -o \
-@@ -797,6 +812,7 @@
- bool 'Networking support' CONFIG_NET
- 
- if [ "$CONFIG_ACER_PICA_61" = "y" -o \
-+     "$CONFIG_AR7" = "y" -o \
-      "$CONFIG_CASIO_E55" = "y" -o \
-      "$CONFIG_DECSTATION" = "y" -o \
-      "$CONFIG_IBM_WORKPAD" = "y" -o \
-diff -urN linux-2.4.30/arch/mips/kernel/irq.c linux-2.4.30.dev/arch/mips/kernel/irq.c
---- linux-2.4.30/arch/mips/kernel/irq.c        2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/irq.c    2005-06-14 15:36:59.000000000 +0200
-@@ -76,6 +76,7 @@
-  * Generic, controller-independent functions:
-  */
- 
-+#ifndef CONFIG_AR7
- int get_irq_list(char *buf)
- {
-       int i, j;
-@@ -110,6 +111,7 @@
-       p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
-       return p - buf;
- }
-+#endif
- 
- #ifdef CONFIG_SMP
- int global_irq_holder = NO_PROC_ID;
-@@ -525,6 +527,7 @@
-  *
-  */
- 
-+#ifndef CONFIG_AR7
- int request_irq(unsigned int irq,
-               void (*handler)(int, void *, struct pt_regs *),
-               unsigned long irqflags,
-@@ -569,6 +572,7 @@
-               kfree(action);
-       return retval;
- }
-+#endif
- 
- /**
-  *    free_irq - free an interrupt
-@@ -588,6 +592,7 @@
-  *          the machine.
-  */
- 
-+#ifndef CONFIG_AR7
- void free_irq(unsigned int irq, void *dev_id)
- {
-       irq_desc_t *desc;
-@@ -629,6 +634,7 @@
-               return;
-       }
- }
-+#endif
- 
- /*
-  * IRQ autodetection code..
-diff -urN linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30.dev/arch/mips/kernel/setup.c
---- linux-2.4.30/arch/mips/kernel/setup.c      2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/setup.c  2005-06-14 15:36:59.000000000 +0200
-@@ -109,6 +109,7 @@
- unsigned long isa_slot_offset;
- EXPORT_SYMBOL(isa_slot_offset);
- 
-+extern void avalanche_bootmem_init(void);
- extern void SetUpBootInfo(void);
- extern void load_mmu(void);
- extern asmlinkage void start_kernel(void);
-@@ -267,6 +268,9 @@
- #endif        /* CONFIG_BLK_DEV_INITRD */
- 
-       /* Find the highest page frame number we have available.  */
-+#ifdef CONFIG_AR7_PAGING
-+      avalanche_bootmem_init();
-+#else
-       max_pfn = 0;
-       first_usable_pfn = -1UL;
-       for (i = 0; i < boot_mem_map.nr_map; i++) {
-@@ -376,7 +380,7 @@
- 
-       /* Reserve the bootmap memory.  */
-       reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
--
-+#endif
- #ifdef CONFIG_BLK_DEV_INITRD
-       /* Board specific code should have set up initrd_start and initrd_end */
-       ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
-@@ -494,6 +498,7 @@
-       void hp_setup(void);
-       void au1x00_setup(void);
-       void frame_info_init(void);
-+      void ar7_setup(void);
- 
-       frame_info_init();
- #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
-@@ -691,6 +696,11 @@
-                 pmc_yosemite_setup();
-                 break;
- #endif
-+#ifdef CONFIG_AR7
-+      case MACH_GROUP_UNKNOWN:
-+              ar7_setup();
-+              break;
-+#endif
-       default:
-               panic("Unsupported architecture");
-       }
-diff -urN linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30.dev/arch/mips/kernel/traps.c
---- linux-2.4.30/arch/mips/kernel/traps.c      2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/traps.c  2005-06-14 15:36:59.000000000 +0200
-@@ -40,6 +40,10 @@
- #include <asm/uaccess.h>
- #include <asm/mmu_context.h>
- 
-+#ifdef CONFIG_AR7
-+#include <asm/ar7/ar7.h>
-+#endif
-+
- extern asmlinkage void handle_mod(void);
- extern asmlinkage void handle_tlbl(void);
- extern asmlinkage void handle_tlbs(void);
-@@ -869,9 +873,15 @@
- 
-       exception_handlers[n] = handler;
-       if (n == 0 && cpu_has_divec) {
-+#ifdef CONFIG_AR7
-+              *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
-+                      (0x03ffffff & (handler >> 2));
-+              flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
-+#else
-               *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
-                                                (0x03ffffff & (handler >> 2));
-               flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
-+#endif
-       }
-       return (void *)old_handler;
- }
-@@ -920,14 +930,46 @@
- void __init trap_init(void)
- {
-       extern char except_vec1_generic;
-+      extern char except_vec2_generic;
-       extern char except_vec3_generic, except_vec3_r4000;
-       extern char except_vec_ejtag_debug;
-       extern char except_vec4;
-       unsigned long i;
- 
-+#ifdef CONFIG_AR7
-+      extern char jump_tlb_miss, jump_tlb_miss_unused;
-+      extern char jump_cache_error,jump_general_exception;
-+      extern char jump_dedicated_interrupt;
-+      clear_c0_status(ST0_BEV);
-+#endif
-+
-       /* Copy the generic exception handler code to it's final destination. */
-       memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
-+      memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
-+      memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
- 
-+      memcpy((void *)(KSEG0 + 0x0),   &jump_tlb_miss, 0x80);
-+      memcpy((void *)(KSEG0 + 0x80),  &jump_tlb_miss_unused, 0x80);
-+      memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
-+      memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
-+      memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
-+
-+#ifdef CONFIG_AR7
-+      memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
-+      memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
-+      memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
-+      flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
-+
-+      memcpy((void *)(KSEG0 + 0x0),   &jump_tlb_miss, 0x80);
-+      memcpy((void *)(KSEG0 + 0x80),  &jump_tlb_miss_unused, 0x80);
-+      memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
-+      memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
-+      memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
-+#else
-+      memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
-+#endif
-+      flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
-+      
-       /*
-        * Setup default vectors
-        */
-@@ -951,8 +993,12 @@
-        * Some MIPS CPUs have a dedicated interrupt vector which reduces the
-        * interrupt processing overhead.  Use it where available.
-        */
-+#ifdef CONFIG_AR7
-+      memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
-+#else
-       if (cpu_has_divec)
-               memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
-+#endif
- 
-       /*
-        * Some CPUs can enable/disable for cache parity detection, but does
-@@ -991,12 +1037,17 @@
-       if (cpu_has_mcheck)
-               set_except_vector(24, handle_mcheck);
- 
-+memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
-+#ifdef CONFIG_AR7
-+      memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
-+#else
-       if (cpu_has_vce)
-               memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
-       else if (cpu_has_4kex)
-               memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
-       else
-               memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
-+#endif
- 
-       if (current_cpu_data.cputype == CPU_R6000 ||
-           current_cpu_data.cputype == CPU_R6000A) {
-@@ -1023,7 +1074,11 @@
-       if (board_nmi_handler_setup)
-               board_nmi_handler_setup();
- 
-+#ifdef CONFIG_AR7
-+      flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
-+#else
-       flush_icache_range(KSEG0, KSEG0 + 0x400);
-+#endif
- 
-       per_cpu_trap_init();
- }
-diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.dev/arch/mips/lib/promlib.c
---- linux-2.4.30/arch/mips/lib/promlib.c       2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/lib/promlib.c   2005-06-14 15:36:59.000000000 +0200
-@@ -1,3 +1,4 @@
-+#ifndef CONFIG_AR7
- #include <stdarg.h>
- #include <linux/kernel.h>
- 
-@@ -22,3 +23,4 @@
-       }
-       va_end(args);
- }
-+#endif
-diff -urN linux-2.4.30/arch/mips/mm/init.c linux-2.4.30.dev/arch/mips/mm/init.c
---- linux-2.4.30/arch/mips/mm/init.c   2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/mm/init.c       2005-06-14 15:36:59.000000000 +0200
-@@ -40,8 +40,10 @@
- 
- mmu_gather_t mmu_gathers[NR_CPUS];
- unsigned long highstart_pfn, highend_pfn;
-+#ifndef CONFIG_AR7_PAGING
- static unsigned long totalram_pages;
- static unsigned long totalhigh_pages;
-+#endif
- 
- void pgd_init(unsigned long page)
- {
-@@ -235,6 +237,7 @@
- #endif
- }
- 
-+#ifndef CONFIG_AR7_PAGING
- void __init paging_init(void)
- {
-       unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
-@@ -272,6 +275,7 @@
- 
-       free_area_init(zones_size);
- }
-+#endif
- 
- #define PFN_UP(x)     (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
- #define PFN_DOWN(x)   ((x) >> PAGE_SHIFT)
-@@ -298,6 +302,7 @@
-       return 0;
- }
- 
-+#ifndef CONFIG_AR7_PAGING
- void __init mem_init(void)
- {
-       unsigned long codesize, reservedpages, datasize, initsize;
-@@ -359,6 +364,7 @@
-              initsize >> 10,
-              (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
- }
-+#endif
- 
- #ifdef CONFIG_BLK_DEV_INITRD
- void free_initrd_mem(unsigned long start, unsigned long end)
-@@ -376,6 +382,7 @@
- }
- #endif
- 
-+#ifndef CONFIG_AR7_PAGING
- extern char __init_begin, __init_end;
- extern void prom_free_prom_memory(void) __init;
- 
-@@ -383,7 +390,9 @@
- {
-       unsigned long addr;
- 
-+#ifndef CONFIG_AR7
-       prom_free_prom_memory ();
-+#endif
- 
-       addr = (unsigned long) &__init_begin;
-       while (addr < (unsigned long) &__init_end) {
-@@ -409,3 +418,4 @@
- 
-       return;
- }
-+#endif
-diff -urN linux-2.4.30/arch/mips/mm/tlb-r4k.c linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c
---- linux-2.4.30/arch/mips/mm/tlb-r4k.c        2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c    2005-06-14 15:36:59.000000000 +0200
-@@ -20,6 +20,10 @@
- #include <asm/pgtable.h>
- #include <asm/system.h>
- 
-+#ifdef CONFIG_AR7
-+#include <asm/ar7/ar7.h>
-+#endif
-+
- extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
- 
- /* CP0 hazard avoidance. */
-@@ -375,7 +379,12 @@
-               else if (current_cpu_data.cputype == CPU_R4600)
-                       memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
-               else
-+#ifdef CONFIG_AR7
-+                      memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
-+              flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
-+#else
-                       memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
-               flush_icache_range(KSEG0, KSEG0 + 0x80);
-+#endif
-       }
- }
-diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.dev/drivers/char/serial.c
---- linux-2.4.30/drivers/char/serial.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/drivers/char/serial.c     2005-06-14 15:36:59.000000000 +0200
-@@ -419,7 +419,40 @@
-       return 0;
- }
- 
--#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
-+#if defined(CONFIG_AR7)
-+
-+static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
-+{
-+      return (inb(info->port + (offset * 4)) & 0xff);  
-+}
-+
-+
-+static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
-+{
-+#ifdef CONFIG_SERIAL_NOPAUSE_IO
-+      return (inb(info->port + (offset * 4)) & 0xff);
-+#else
-+      return (inb_p(info->port + (offset * 4)) & 0xff);
-+#endif
-+}
-+
-+static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
-+{
-+      outb(value, info->port + (offset * 4));      
-+}
-+
-+
-+static _INLINE_ void serial_outp(struct async_struct *info, int offset,
-+              int value)
-+{
-+#ifdef CONFIG_SERIAL_NOPAUSE_IO
-+      outb(value, info->port + (offset * 4));
-+#else
-+      outb_p(value, info->port + (offset * 4));
-+#endif
-+}
-+
-+#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
- 
- #include <asm/mips-boards/atlas.h>
- 
-@@ -478,8 +511,10 @@
-  * needed for certain old 386 machines, I've left these #define's
-  * in....
-  */
-+#ifdef CONFIG_AR7
- #define serial_inp(info, offset)              serial_in(info, offset)
- #define serial_outp(info, offset, value)      serial_out(info, offset, value)
-+#endif
- 
- 
- /*
-@@ -1728,7 +1763,15 @@
-                       /* Special case since 134 is really 134.5 */
-                       quot = (2*baud_base / 269);
-               else if (baud)
-+#ifdef CONFIG_AR7
-+                      quot = get_avalanche_vbus_freq() / baud;
-+
-+              if ((quot%16)>7)
-+                      quot += 8;
-+              quot /=16;
-+#else
-                       quot = baud_base / baud;
-+#endif
-       }
-       /* If the quotient is zero refuse the change */
-       if (!quot && old_termios) {
-@@ -5552,8 +5595,10 @@
-               state->irq = irq_cannonicalize(state->irq);
-               if (state->hub6)
-                       state->io_type = SERIAL_IO_HUB6;
-+#ifdef CONFIG_AR7
-               if (state->port && check_region(state->port,8))
-                       continue;
-+#endif
- #ifdef CONFIG_MCA                     
-               if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
-                       continue;
-@@ -6009,7 +6054,15 @@
-       info->io_type = state->io_type;
-       info->iomem_base = state->iomem_base;
-       info->iomem_reg_shift = state->iomem_reg_shift;
-+#ifdef CONFIG_AR7
-+      quot = get_avalanche_vbus_freq() / baud;
-+
-+      if ((quot%16)>7)
-+              quot += 8;
-+      quot /=16;
-+#else
-       quot = state->baud_base / baud;
-+#endif
-       cval = cflag & (CSIZE | CSTOPB);
- #if defined(__powerpc__) || defined(__alpha__)
-       cval >>= 8;
-diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.dev/include/asm-mips/ar7/ar7.h
---- linux-2.4.30/include/asm-mips/ar7/ar7.h    1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/ar7.h        2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,137 @@
-+#ifndef _MIPS_AR7_H
-+#define _MIPS_AR7_H
-+
-+#include <linux/config.h>
-+#include <asm/addrspace.h>
-+
-+
-+#ifndef LITTLE_ENDIAN
-+#define LITTLE_ENDIAN
-+#endif
-+
-+#ifndef _LINK_KSEG0_
-+#define _LINK_KSEG0_
-+#endif
-+
-+#include <asm/ar7/tnetd73xx.h>
-+
-+#define AVALANCHE_UART0_INT          7
-+#define AVALANCHE_UART1_INT          8
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+
-+/*
-+ * AR7 board SDRAM base address.  This is used to setup the
-+ * bootmem tables
-+ */
-+
-+#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
-+#define AVALANCHE_INTC_BASE  TNETD73XX_INTC_BASE
-+
-+
-+/*
-+ * AR7 board vectors
-+ */
-+
-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+
-+
-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR           (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
-+
-+/*
-+ * AR7 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG         (KSEG1ADDR(0x08611600))    /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG         (KSEG1ADDR(0x08611600))    /* Turns off power supply unit */
-+#define AVALANCHE_GORESET             0x1
-+#define AVALANCHE_GOSTBY              0x1
-+#define AVALANCHE_SWRCR              (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
-+
-+/*
-+ * Avalanche UART register base.
-+ */
-+
-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD       ( 3686400 / 16 )
-+
-+/*
-+ * AVALANCHE DMA controller base
-+ */
-+
-+#define AVALANCHE_DMA0_CTRL_BASE       (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
-+
-+
-+
-+/*
-+ * GPIO register map
-+ */
++      u32  clk_ctrl_register;
++      u32  clk_pll_setting;
++      u32  clk_predivider;
++      u32  clk_postdivider;
++      u16  pll_factor;
++      u32  base_freq;
++      u32  divider;

 +
 +

-+/* to be obtained from avalanche_map.h */
-+#define  AVALANCHE_GPIO_WRITE_REG         (KSEG1ADDR(0xa8610904))
-+#define  AVALANCHE_GPIO_DIRECTION_REG     (KSEG1ADDR(0xa8610908))
-+#define  AVALANCHE_GPIO_MODE_REG          (KSEG1ADDR(0xa861090C))
-+#define  AVALANCHE_GPIO_PIN_COUNT         32
-+#define  AVALANCHE_GPIO_OFF_MAP           {0xF34FFFC0,0}
++      base_freq = get_base_frequency(clk_id);

 +
 +

++      clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));

 +
 +

-+// Let us define board specific information here. 
++      /* pre-Divider and post-divider are 5 bit N+1 dividers */
++      clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
++      clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;

 +
 +

-+#if defined(CONFIG_AR7DB)
++      divider =  clk_predivider * clk_postdivider;

 +
 +

-+#define AFECLK_FREQ                                 35328000
-+#define REFCLK_FREQ                                 25000000
-+#define OSC3_FREQ                                   24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK           0x80000000
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x55555555  

 +
 +

-+#endif
++      if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
++      {
++              return (CEIL(base_freq, divider));  /* PLLs bypassed.*/
++      }

 +
 +
 +
 +

-+#if defined(CONFIG_AR7RD)
++      else
++      {
++              /*  return the current clock speed based upon the PLL setting */
++              clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));

 +
 +

-+#define AFECLK_FREQ                                 35328000
-+#define REFCLK_FREQ                                 25000000
-+#define OSC3_FREQ                                   24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK           0x80000000
++              /* Get the PLL multiplication factor */
++              pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;

 +
 +

-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x2
-+#endif
++              /* Check if we're in divide mode or multiply mode */
++              if((clk_pll_setting & 0x1)   == 0)
++              {
++                      /* We're in divide mode */
++                      if(pll_factor <  0x10)
++                              return (CEIL(base_freq >> 1, divider));
++                      else
++                              return (CEIL(base_freq >> 2, divider));
++              }

 +
 +

-+#endif
++              else     /* We're in PLL mode */
++              {
++                      /* See if PLLNDIV & PLLDIV are set */
++                      if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
++                      {
++                              if(clk_pll_setting & 0x1000)
++                              {
++                                      /* clk = base_freq * k/2  */
++                                      return(CEIL((base_freq * pll_factor) >> 1, divider));
++                              }
++                              else
++                              {
++                                      /* clk = base_freq * (k-1) / 4)*/
++                                      return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
++                              }
++                      }
++                      else
++                      {
++                              if(pll_factor < 0x10)
++                              {
++                                      /* clk = base_freq * k */
++                                      return(CEIL(base_freq * pll_factor, divider));
++                              }

 +
 +

++                              else
++                              {
++                                      /* clk = base_freq  */
++                                      return(CEIL(base_freq, divider));
++                              }
++                      }
++              }
++              return(0); /* Should never reach here */

 +
 +

-+#if defined(CONFIG_AR7WRD)
++      }

 +
 +

-+#define AFECLK_FREQ                                 35328000
-+#define REFCLK_FREQ                                 25000000
-+#define OSC3_FREQ                                   24000000
-+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK           0x80000000
++}

 +
 +

-+#if defined(CONFIG_AR7_MARVELL)
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x00010000
-+#else
-+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK           0x2
-+#endif

 +
 +

-+#endif
++/* local helper functions */

 +
 +

-+extern unsigned int tnetd73xx_vbus_freq;
-+#define AVALANCHE_VBUS_FREQ            tnetd73xx_vbus_freq
++/****************************************************************************
++ * FUNCTION: get_base_frequency
++ ****************************************************************************
++ * Description: The above routine is called to get base frequency of the clocks.
++ ***************************************************************************/

 +
 +

-+static inline unsigned int get_avalanche_vbus_freq(void)
++static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)

 +{
 +{

-+    return (tnetd73xx_vbus_freq);
-+}
++      /* update the current MIPs PLL output value, if the required
++       * source is MIPS PLL
++       */
++      if ( clk_src[clk_id] == &mips_pll_out)
++      {
++              *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
++      }

 +
 +

-+#endif /*_MIPS_AR7_H */
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche.h      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h  2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,183 @@
-+/* $Id$
-+ *
-+ * avalanche.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
-+ *
-+ *
-+ * ########################################################################
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines of the AVALANCHE board specific address-MAP, registers, etc.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHE_H
-+#define _MIPS_AVALANCHE_H

 +
 +

-+#include <asm/addrspace.h>
++      /* update the current System PLL output value, if the required
++       * source is system PLL
++       */
++      if ( clk_src[clk_id] == &sys_pll_out)
++      {
++              *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
++      }

 +
 +

-+/*
-+ * AVALANCHE board SDRAM base address.  This is used to setup the 
-+ * bootmem tables
-+ */
++      return (*clk_src[clk_id]);

 +
 +

-+#define AVALANCHE_SDRAM_BASE 0x14000000UL
++}

 +
 +

-+/*
-+ * AVALANCHE board vectors
-+ */

 +
 +

-+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
-+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
-+/* 
-+ * Avalanche RTC-device indirect register access.
-+ */

 +
 +

-+#define EVM3_RTC_ADR_REG       (KSEG1ADDR(0x1f000800))
-+#define EVM3_RTC_DAT_REG       (KSEG1ADDR(0x1f000808))
++/****************************************************************************
++ * FUNCTION: find_gcd
++ ****************************************************************************
++ * Description: The above routine is called to find gcd of 2 numbers.
++ ***************************************************************************/
++static u32 find_gcd
++(
++ u32 min,
++ u32 max
++ )
++{
++      if (max % min == 0)
++      {
++              return min;
++      }
++      else
++      {
++              return find_gcd(max % min, min);
++      }
++}

 +
 +

-+/*
-+ * Evm3 interrupt controller register base (primary) 
-+ */
++/****************************************************************************
++ * FUNCTION: compute_prediv
++ ****************************************************************************
++ * Description: The above routine is called to compute predivider value
++ ***************************************************************************/
++static u32 compute_prediv(u32 divider, u32 min, u32 max)
++{
++      u16 prediv;

 +
 +

-+#define AVALANCHE_ICTRL_REGS_BASE  (KSEG1ADDR(0x08612400))
++      /* return the divider itself it it falls within the range of predivider*/
++      if (min <= divider && divider <= max)
++      {
++              return divider;
++      }

 +
 +

-+/*
-+ * Avalanche exception controller register base (secondary) 
-+ */
-+#define AVALANCHE_ECTRL_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE+0x80)
++      /* find a value for prediv such that it is a factor of divider */
++      for (prediv = max; prediv >= min ; prediv--)
++      {
++              if ( (divider % prediv) == 0 )
++              {
++                      return prediv;
++              }
++      }

 +
 +

++      /* No such factor exists,  return min as prediv */
++      return min;
++}

 +
 +

-+/*
-+ * Avalanche Interrupt Channel Control register base
-+ */
-+#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
++/****************************************************************************
++ * FUNCTION: get_val
++ ****************************************************************************
++ * Description: This routine is called to get values of divider and multiplier.
++ ***************************************************************************/

 +
 +

++static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
++{
++      u32 temp_mul;
++      u32 temp_div;
++      u32 gcd;
++      u32 min_freq;
++      u32 max_freq;

 +
 +

-+/*
-+ * Avalanche UART register base.
-+ */
++      /* find gcd of base_freq, output_freq */
++      min_freq = (base_freq < output_freq) ? base_freq : output_freq;
++      max_freq = (base_freq > output_freq) ? base_freq : output_freq;
++      gcd = find_gcd(min_freq , max_freq);

 +
 +

-+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))  /* AVALANCHE UART 0 */
-+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))  /* AVALANCHE UART 1 */
-+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 ) 
-+/* 
-+ * AVALANCHE DMA controller base
-+ */
++      if(gcd == 0)
++              return;  /* ERROR */

 +
 +

-+#define AVALANCHE_DMA0_CTRL_BASE       (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
++      /* compute values of multiplier and divider */
++      temp_mul = output_freq / gcd;
++      temp_div = base_freq / gcd;

 +
 +
 +
 +

-+/*
-+ * AVALANCHE display register base.
-+ */
++      /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
++      if( temp_mul > PLL_MUL_MAXFACTOR )
++      {
++              if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
++                      return;

 +
 +

-+#define EVM3_ASCII_DISPLAY_POS_BASE     (KSEG1ADDR(0x1D000038))
-+#define EVM3_ASCII_DISPLAY_WORD_BASE    (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
++              find_approx(&temp_mul,&temp_div,base_freq);
++      }

 +
 +

++      *multiplier = temp_mul;
++      *divider    = temp_div;
++}

 +
 +

-+#define EVM3_ASCIIPOS0                0x1D000038
-+#define EVM3_ASCIIPOS1                0x1D000039
-+#define EVM3_ASCIIPOS2                0x1D00003A
-+#define EVM3_ASCIIPOS3                0x1D00003B
-+#define EVM3_ASCIIPOS4                0x1D00003C
-+#define EVM3_ASCIIPOS5                0x1D00003D
-+#define EVM3_ASCIIPOS6                0x1D00003E
-+#define EVM3_ASCIIPOS7                0x1D00003F
++/****************************************************************************
++ * FUNCTION: find_approx
++ ****************************************************************************
++ * Description: This function gets the approx value of num/denom.
++ ***************************************************************************/

 +
 +

-+/*
-+ * Yamon Prom print address.
-+ */
-+#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
-+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
-+#define AVALANCHE_YAMON_PROM_PRINT_ADDR           (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
++static void find_approx(u32 *num,u32 *denom,u32 base_freq)
++{
++      u32 num1;
++      u32 denom1;
++      u32 num2;
++      u32 denom2;
++      int32_t closest;
++      int32_t prev_closest;
++      u32 temp_num;
++      u32 temp_denom;
++      u32 normalize;
++      u32 gcd;
++      u32 output_freq;

 +
 +

-+/*
-+ * Evm3 Reset and PSU standby register.
-+ */
-+#define AVALANCHE_SOFTRES_REG         (KSEG1ADDR(0x08611600))    /* Resets machine */
-+#define AVALANCHE_PSUSTBY_REG         (KSEG1ADDR(0x08611600))    /* Turns off power supply unit */
-+#define AVALANCHE_GORESET             0x1
-+#define AVALANCHE_GOSTBY              0x1
++      num1 = *num;
++      denom1 = *denom;

 +
 +

-+/************************************************************************
-+ *  PERIPHERAL BUS LEDs (P-LED):
-+*************************************************************************/
++      prev_closest = 0x7fffffff; /* maximum possible value */
++      num2 = num1;
++      denom2 = denom1;

 +
 +

-+/************************************************************************
-+ *      P-LED Register Addresses
-+*************************************************************************/
++      /* start with  max */
++      for(temp_num = 15; temp_num >=1; temp_num--)
++      {

 +
 +

-+#define EVM3_PLED               (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED          */
++              temp_denom = CEIL(temp_num * denom1, num1);
++              output_freq = (temp_num * base_freq) / temp_denom;

 +
 +

++              if(temp_denom < 1)
++              {
++                      break;
++              }
++              else
++              {
++                      normalize = CEIL(num1,temp_num);
++                      closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1)))  * normalize;
++                      if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
++                      {
++                              prev_closest = closest;
++                              num2 = temp_num;
++                              denom2 = temp_denom;
++                      }

 +
 +

-+/************************************************************************
-+ *      Register field encodings
-+*************************************************************************/
++              }

 +
 +

-+/******** reg: PLED ********/
-+/* bits 7:0: VAL */
-+#define EVM3_PLED_VAL_MSK             0xff
++      }

 +
 +

-+/* bit 0:  */
-+#define EVM3_PLED_BIT0_SHF            0
-+#define EVM3_PLED_BIT0_MSK            (1 << EVM3_PLED_BIT0_SHF)
-+#define EVM3_PLED_BIT0_ON             EVM3_PLED_BIT0_MSK
++      gcd = find_gcd(num2,denom2);
++      num2 = num2 / gcd;
++      denom2 = denom2 /gcd;

 +
 +

-+/* bit 1:  */
-+#define EVM3_PLED_BIT1_SHF            1
-+#define EVM3_PLED_BIT1_MSK            (1 << EVM3_PLED_BIT1_SHF)
-+#define EVM3_PLED_BIT1_ON             EVM3_PLED_BIT1_MSK
++      *num      = num2;
++      *denom    = denom2;
++}

 +
 +

-+/* bit 2:  */
-+#define EVM3_PLED_BIT2_SHF            2
-+#define EVM3_PLED_BIT2_MSK            (1 << EVM3_PLED_BIT2_SHF)
-+#define EVM3_PLED_BIT2_ON             EVM3_PLED_BIT2_MSK

 +
 +

-+/* bit 3:  */
-+#define EVM3_PLED_BIT3_SHF            3
-+#define EVM3_PLED_BIT3_MSK            (1 << EVM3_PLED_BIT3_SHF)
-+#define EVM3_PLED_BIT3_ON             EVM3_PLED_BIT3_MSK
++/*****************************************************************************
++ * GPIO  Control
++ *****************************************************************************/

 +
 +

-+/* bit 4:  */
-+#define EVM3_PLED_BIT4_SHF            4
-+#define EVM3_PLED_BIT4_MSK            (1 << EVM3_PLED_BIT4_SHF)
-+#define EVM3_PLED_BIT4_ON             EVM3_PLED_BIT4_MSK
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_init
++ ***************************************************************************/
++void tnetd73xx_gpio_init()
++{
++      /* Bring module out of reset */
++      tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
++      REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);    
++}

 +
 +

-+/* bit 5:  */
-+#define EVM3_PLED_BIT5_SHF            5
-+#define EVM3_PLED_BIT5_MSK            (1 << EVM3_PLED_BIT5_SHF)
-+#define EVM3_PLED_BIT5_ON             EVM3_PLED_BIT5_MSK
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_ctrl
++ ***************************************************************************/
++void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin, 
++              TNETD73XX_GPIO_PIN_MODE_T pin_mode,
++              TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
++{
++      u32 pin_status;
++      REG32_READ(TNETD73XX_GPIOENR, pin_status);
++      if (pin_mode == GPIO_PIN)
++      {
++              pin_status |= (1 << gpio_pin);
++              REG32_WRITE(TNETD73XX_GPIOENR, pin_status);

 +
 +

-+/* bit 6:  */
-+#define EVM3_PLED_BIT6_SHF            6
-+#define EVM3_PLED_BIT6_MSK            (1 << EVM3_PLED_BIT6_SHF)
-+#define EVM3_PLED_BIT6_ON             EVM3_PLED_BIT6_MSK
++              /* Set pin direction */
++              REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
++              if (pin_direction == GPIO_INPUT_PIN)
++              {
++                      pin_status |= (1 << gpio_pin);
++              }
++              else /* GPIO_OUTPUT_PIN */
++              {
++                      pin_status &= (~(1 << gpio_pin));
++              }
++              REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
++      }
++      else /* FUNCTIONAL PIN */
++      {
++              pin_status &= (~(1 << gpio_pin));
++              REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
++      }

 +
 +

-+/* bit 7:  */
-+#define EVM3_PLED_BIT7_SHF            7
-+#define EVM3_PLED_BIT7_MSK            (1 << EVM3_PLED_BIT7_SHF)
-+#define EVM3_PLED_BIT7_ON             EVM3_PLED_BIT7_MSK
++}

 +
 +

-+#endif /* !(_MIPS_AVALANCHE_H) */
++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_out
++ ***************************************************************************/
++void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
++{
++      u32 pin_value;

 +
 +

++      REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
++      if (value == 1)
++      {
++              pin_value |= (1 << gpio_pin);
++      }
++      else
++      {
++              pin_value &= (~(1 << gpio_pin));
++      }
++      REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
++}

 +
 +

++/****************************************************************************
++ * FUNCTION: tnetd73xx_gpio_in
++ ***************************************************************************/
++int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
++{
++      u32 pin_value;
++      REG32_READ(TNETD73XX_GPIODINR, pin_value);
++      return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
++}

 +
 +

+diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
+--- linux.old/arch/mips/config-shared.in       2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/config-shared.in       2005-08-12 19:53:15.060167880 +0200
+@@ -20,6 +20,16 @@
+ mainmenu_option next_comment
+ comment 'Machine selection'
+ dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
++dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
++if [ "$CONFIG_AR7" = "y" ]; then
++   choice 'Texas Instruments Reference Platform' \
++      "AR7DB CONFIG_AR7DB \
++      AR7RD CONFIG_AR7RD \
++      AR7WRD CONFIG_AR7WRD" AR7DB
++   int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
++   int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
++   hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
++fi
+ dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
+ dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
+ dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
+@@ -239,6 +249,10 @@
+    define_bool CONFIG_NONCOHERENT_IO y
+    define_bool CONFIG_PC_KEYB y
+ fi
++if [ "$CONFIG_AR7" = "y" ]; then
++   define_bool CONFIG_NONCOHERENT_IO y
++   define_bool CONFIG_SWAP_IO_SPACE y
++fi
+ if [ "$CONFIG_CASIO_E55" = "y" ]; then
+    define_bool CONFIG_IRQ_CPU y
+    define_bool CONFIG_NONCOHERENT_IO y
+@@ -736,6 +750,7 @@
+ mainmenu_option next_comment
+ comment 'General setup'
+ if [ "$CONFIG_ACER_PICA_61" = "y" -o \
++     "$CONFIG_AR7" = "y" -o \
+      "$CONFIG_CASIO_E55" = "y" -o \
+      "$CONFIG_DDB5074" = "y" -o \
+      "$CONFIG_DDB5476" = "y" -o \
+@@ -797,6 +812,7 @@
+ bool 'Networking support' CONFIG_NET
+ 
+ if [ "$CONFIG_ACER_PICA_61" = "y" -o \
++     "$CONFIG_AR7" = "y" -o \
+      "$CONFIG_CASIO_E55" = "y" -o \
+      "$CONFIG_DECSTATION" = "y" -o \
+      "$CONFIG_IBM_WORKPAD" = "y" -o \
+diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
+--- linux.old/arch/mips/kernel/head.S  2005-07-10 02:55:18.000000000 +0200
++++ linux.dev/arch/mips/kernel/head.S  2005-08-12 23:05:36.954533232 +0200
+@@ -75,11 +75,11 @@
+                * size!
+                */
+               NESTED(except_vec4, 0, sp)
+-              .set    push
+-              .set    noreorder
+-1:            j       1b                      /* Dummy, will be replaced */
+-               nop
+-              .set    pop
++              .set    mips2
++              lui     k0, 0x9400
++              ori     k0, 0x200
++              jr      k0
++              nop
+               END(except_vec4)
+ 
+               /*
+diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
+--- linux.old/arch/mips/kernel/irq.c   2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/kernel/irq.c   2005-08-12 19:32:05.142224752 +0200
+@@ -76,6 +76,7 @@
+  * Generic, controller-independent functions:
+  */
+ 
++#ifndef CONFIG_AR7
+ int get_irq_list(char *buf)
+ {
+       int i, j;
+@@ -110,6 +111,7 @@
+       p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
+       return p - buf;
+ }
++#endif
+ 
+ #ifdef CONFIG_SMP
+ int global_irq_holder = NO_PROC_ID;
+@@ -525,6 +527,7 @@
+  *
+  */
+ 
++#ifndef CONFIG_AR7
+ int request_irq(unsigned int irq,
+               void (*handler)(int, void *, struct pt_regs *),
+               unsigned long irqflags,
+@@ -569,6 +572,7 @@
+               kfree(action);
+       return retval;
+ }
++#endif
+ 
+ /**
+  *    free_irq - free an interrupt
+@@ -588,6 +592,7 @@
+  *          the machine.
+  */
+ 
++#ifndef CONFIG_AR7
+ void free_irq(unsigned int irq, void *dev_id)
+ {
+       irq_desc_t *desc;
+@@ -629,6 +634,7 @@
+               return;
+       }
+ }
++#endif
+ 
+ /*
+  * IRQ autodetection code..
+diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
+--- linux.old/arch/mips/kernel/mips_ksyms.c    2004-02-18 14:36:30.000000000 +0100
++++ linux.dev/arch/mips/kernel/mips_ksyms.c    2005-08-12 19:32:05.142224752 +0200
+@@ -40,6 +40,12 @@
+ extern long __strnlen_user_nocheck_asm(const char *s);
+ extern long __strnlen_user_asm(const char *s);
+ 
++#ifdef CONFIG_AR7
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
++char *prom_getenv(char *envname);
++#endif

 +
 +
 +
 +

+ EXPORT_SYMBOL(mips_machtype);
+ #ifdef CONFIG_EISA
+ EXPORT_SYMBOL(EISA_bus);
+@@ -103,3 +109,9 @@
+ #endif
+ 
+ EXPORT_SYMBOL(get_wchan);

 +
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_int.h  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h      2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,298 @@
-+/* $Id$
-+ *
-+ * avalancheint.h
-+ *
-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001 Texas Instruments , Inc.
-+ *
-+ * ########################################################################
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Defines for the AVALANCHE interrupt controller.
-+ *
-+ */
-+#ifndef _MIPS_AVALANCHEINT_H
-+#define _MIPS_AVALANCHEINT_H
++#ifdef CONFIG_AR7
++EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
++EXPORT_SYMBOL_NOVERS(prom_getenv);
++#endif

 +
 +

+diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
+--- linux.old/arch/mips/kernel/setup.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/kernel/setup.c 2005-08-12 19:56:27.917849056 +0200
+@@ -235,7 +235,11 @@
+ #define PFN_DOWN(x)   ((x) >> PAGE_SHIFT)
+ #define PFN_PHYS(x)   ((x) << PAGE_SHIFT)
+ 
++#ifdef CONFIG_AR7
++#define MAXMEM                HIGHMEM_START + CONFIG_AR7_MEMORY
++#else
+ #define MAXMEM                HIGHMEM_START
++#endif
+ #define MAXMEM_PFN    PFN_DOWN(MAXMEM)
+ 
+ static inline void bootmem_init(void)
+@@ -320,7 +324,12 @@
+ #endif
+ 
+       /* Initialize the boot-time allocator with low memory only.  */
++#ifdef CONFIG_AR7
++      bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
++                      CONFIG_AR7_MEMORY >> PAGE_SHIFT, max_low_pfn);
++#else
+       bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
++#endif
+ 
+       /*
+        * Register fully available low RAM pages with the bootmem allocator.
+@@ -494,6 +503,7 @@
+       void hp_setup(void);
+       void au1x00_setup(void);
+       void frame_info_init(void);
++      void ar7_setup(void);
+ 
+       frame_info_init();
+ #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
+@@ -691,6 +701,11 @@
+                 pmc_yosemite_setup();
+                 break;
+ #endif
++#ifdef CONFIG_AR7
++      case MACH_GROUP_UNKNOWN:
++              ar7_setup();
++              break;
++#endif
+       default:
+               panic("Unsupported architecture");
+       }
+diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
+--- linux.old/arch/mips/kernel/traps.c 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/kernel/traps.c 2005-08-12 23:38:46.505075576 +0200
+@@ -869,9 +869,15 @@
+ 
+       exception_handlers[n] = handler;
+       if (n == 0 && cpu_has_divec) {
++#ifdef CONFIG_AR7
++              *(volatile u32 *)(KSEG0+0x200+CONFIG_AR7_MEMORY) = 0x08000000 |
++                                               (0x03ffffff & (handler >> 2));
++              flush_icache_range(KSEG0+0x200+CONFIG_AR7_MEMORY, KSEG0 + 0x204 + CONFIG_AR7_MEMORY);
++#else
+               *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
+                                                (0x03ffffff & (handler >> 2));
+               flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
++#endif
+       }
+       return (void *)old_handler;
+ }
+@@ -1022,6 +1028,12 @@
+ 
+       if (board_nmi_handler_setup)
+               board_nmi_handler_setup();
++#ifdef CONFIG_AR7
++      memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x80), &except_vec1_generic, 0x80);
++      memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x180), &except_vec3_generic, 0x80);
++      memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x200), &except_vec4, 8);
++      flush_icache_range(KSEG0 + CONFIG_AR7_MEMORY, KSEG0 + CONFIG_AR7_MEMORY + 0x208);
++#endif
+ 
+       flush_icache_range(KSEG0, KSEG0 + 0x400);
+ 
+diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
+--- linux.old/arch/mips/lib/promlib.c  2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/lib/promlib.c  2005-08-12 20:39:57.087195024 +0200
+@@ -1,6 +1,8 @@
+ #include <stdarg.h>
+ #include <linux/kernel.h>

 +#include <linux/config.h>
 +#include <linux/config.h>

+ 
++#ifndef CONFIG_AR7
+ extern void prom_putchar(char);
+ 
+ void prom_printf(char *fmt, ...)
+@@ -22,3 +24,4 @@
+       }
+       va_end(args);
+ }
++#endif
+diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
+--- linux.old/arch/mips/Makefile       2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/Makefile       2005-08-12 20:38:28.398677728 +0200
+@@ -369,6 +369,16 @@
+ endif
+ 
+ #
++# Texas Instruments AR7
++#

 +
 +

-+/* Avalanche Interrupt number */
-+#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
-+/* Linux Interrupt number     */ 
-+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
-+/* Number of IRQ supported on hw interrupt 0. */
-+
-+//#define SEADINT_UART0      3            /* TTYS0 interrupt on SEAD */
-+//#define SEADINT_UART1      4            /* TTYS1 interrupt on SEAD */
-+
-+
-+#define MIPS_EXCEPTION_OFFSET 8
-+#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
-+#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
-+
-+#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
-+#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
++ifdef CONFIG_AR7
++LIBS          += arch/mips/ar7/ar7.o
++SUBDIRS               += arch/mips/ar7
++LOADADDR      += 0x94020000
++endif

 +
 +

++#
+ # DECstation family
+ #
+ ifdef CONFIG_DECSTATION
+diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
+--- linux.old/arch/mips/mm/init.c      2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/arch/mips/mm/init.c      2005-08-12 21:08:04.420681344 +0200
+@@ -248,6 +248,9 @@
+ 
+       max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
+       low = max_low_pfn;
++#ifdef CONFIG_AR7
++      low = NODE_DATA(0)->bdata->node_low_pfn - (CONFIG_AR7_MEMORY >> PAGE_SHIFT);
++#endif
+       high = highend_pfn;
+ 
+ #ifdef CONFIG_ISA
+@@ -270,7 +273,11 @@
+               zones_size[ZONE_HIGHMEM] = high - low;
+ #endif
+ 
++#ifdef CONFIG_AR7
++      free_area_init_node(0, NODE_DATA(0), 0, zones_size, CONFIG_AR7_MEMORY, 0);
++#else
+       free_area_init(zones_size);
++#endif
+ }
+ 
+ #define PFN_UP(x)     (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
+@@ -298,6 +305,10 @@
+       return 0;
+ }
+ 
++#ifdef CONFIG_AR7
++#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
++#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
++#endif
+ void __init mem_init(void)
+ {
+       unsigned long codesize, reservedpages, datasize, initsize;
+@@ -315,9 +326,21 @@
+ #else
+       max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
+ #endif
++      
++#ifdef CONFIG_AR7
++      max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
++      high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
++      
++#if 0
++      /* WTF? */
++      free_bootmem_node(NODE_DATA(0), (CONFIG_AR7_MEMORY+PAGE_SIZE), (__pa(&_ftext))-(CONFIG_AR7_MEMORY+PAGE_SIZE));
++#endif
++      totalram_pages += free_all_bootmem_node(NODE_DATA(0));
++#else
+       high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
+-
+       totalram_pages += free_all_bootmem();
++#endif

 +
 +

-+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
-+                     + MIPS_EXCEPTION_OFFSET - 1)
+       totalram_pages -= setup_zero_pages();   /* Setup zeroed pages.  */
+ 
+       reservedpages = ram = 0;
+diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
+--- linux.old/drivers/char/serial.c    2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/drivers/char/serial.c    2005-08-12 19:32:05.147223992 +0200
+@@ -419,7 +419,40 @@
+       return 0;
+ }
+ 
+-#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
++#if defined(CONFIG_AR7)

 +
 +

-+struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
++static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)

 +{
 +{

-+  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   */ /* 0x00 */      
-+  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   */ /* 0x04 */
-+  volatile unsigned long unused1;                                           /* 0x08 */
-+  volatile unsigned long unused2;                                           /* 0x0C */
-+  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        */ /* 0x10 */
-+  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        */ /* 0x14 */
-+  volatile unsigned long unused3;                                           /* 0x18 */
-+  volatile unsigned long unused4;                                           /* 0x1C */
-+  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
-+  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
-+  volatile unsigned long unused5;                                           /* 0x28 */
-+  volatile unsigned long unused6;                                           /* 0x2C */
-+  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 */ /* 0x30 */
-+  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 */ /* 0x34 */
-+  volatile unsigned long unused7;                                           /* 0x38 */
-+  volatile unsigned long unused8;                                           /* 0x3c */
-+  volatile unsigned long pintir;    /* Priority Interrupt Index Register */ /* 0x40 */
-+  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
-+  volatile unsigned long unused9;                                           /* 0x48 */
-+  volatile unsigned long unused10;                                          /* 0x4C */
-+  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 1*/ /* 0x50 */
-+  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 2*/ /* 0x54 */
-+};
++      return (inb(info->port + (offset * 4)) & 0xff);  
++}

 +
 +

-+struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
-+{
-+  volatile unsigned long exsr;      /* Exceptions Status/Set register    */  /* 0x80 */
-+  volatile unsigned long reserved;                                           /* 0x84 */
-+  volatile unsigned long excr;      /* Exceptions Clear Register         */  /* 0x88 */
-+  volatile unsigned long reserved1;                                          /* 0x8c */
-+  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) */  /* 0x90 */
-+  volatile unsigned long reserved2;                                          /* 0x94 */
-+  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
-+};

 +
 +

-+struct avalanche_channel_int_number
++static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)

 +{
 +{

-+  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register */  /* 0x200 */
-+  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register */  /* 0x204 */
-+  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register */  /* 0x208 */
-+  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register */  /* 0x20C */
-+  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register */  /* 0x210 */
-+  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register */  /* 0x214 */
-+  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register */  /* 0x218 */
-+  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register */  /* 0x21C */
-+  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register */  /* 0x220 */
-+  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register */  /* 0x224 */
-+  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register */  /* 0x228 */
-+  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register */  /* 0x22C */
-+  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register */  /* 0x230 */
-+  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register */  /* 0x234 */
-+  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register */  /* 0x238 */
-+  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register */  /* 0x23C */
-+  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register */  /* 0x240 */
-+  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register */  /* 0x244 */
-+  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register */  /* 0x248 */
-+  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register */  /* 0x24C */
-+  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register */  /* 0x250 */
-+  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register */  /* 0x254 */
-+  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register */  /* 0x358 */
-+  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register */  /* 0x35C */
-+  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register */  /* 0x260 */
-+  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register */  /* 0x264 */
-+  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register */  /* 0x268 */
-+  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register */  /* 0x26C */
-+  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register */  /* 0x270 */
-+  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register */  /* 0x274 */
-+  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register */  /* 0x278 */
-+  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register */  /* 0x27C */
-+  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register */  /* 0x280 */
-+  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register */  /* 0x284 */
-+  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register */  /* 0x288 */
-+  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register */  /* 0x28C */
-+  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register */  /* 0x290 */
-+  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register */  /* 0x294 */
-+  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register */  /* 0x298 */
-+  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register */  /* 0x29C */
-+};
++#ifdef CONFIG_SERIAL_NOPAUSE_IO
++      return (inb(info->port + (offset * 4)) & 0xff);
++#else
++      return (inb_p(info->port + (offset * 4)) & 0xff);
++#endif
++}

 +
 +

-+struct avalanche_interrupt_line_to_channel 
++static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)

 +{
 +{

-+  unsigned long int_line0;    /* Start of primary interrupts */
-+  unsigned long int_line1;
-+  unsigned long int_line2;
-+  unsigned long int_line3;
-+  unsigned long int_line4;
-+  unsigned long int_line5;
-+  unsigned long int_line6;
-+  unsigned long int_line7;
-+  unsigned long int_line8;
-+  unsigned long int_line9;
-+  unsigned long int_line10;
-+  unsigned long int_line11; 
-+  unsigned long int_line12; 
-+  unsigned long int_line13; 
-+  unsigned long int_line14; 
-+  unsigned long int_line15; 
-+  unsigned long int_line16; 
-+  unsigned long int_line17; 
-+  unsigned long int_line18; 
-+  unsigned long int_line19; 
-+  unsigned long int_line20; 
-+  unsigned long int_line21;
-+  unsigned long int_line22; 
-+  unsigned long int_line23; 
-+  unsigned long int_line24; 
-+  unsigned long int_line25; 
-+  unsigned long int_line26; 
-+  unsigned long int_line27; 
-+  unsigned long int_line28; 
-+  unsigned long int_line29; 
-+  unsigned long int_line30; 
-+  unsigned long int_line31; 
-+  unsigned long int_line32;
-+  unsigned long int_line33; 
-+  unsigned long int_line34; 
-+  unsigned long int_line35; 
-+  unsigned long int_line36; 
-+  unsigned long int_line37; 
-+  unsigned long int_line38; 
-+  unsigned long int_line39;  
-+};
-+
-+/* Interrupt Line #'s  (Avalanche peripherals) */
-+
-+/*------------------------------*/
-+/* Avalanche primary interrupts */
-+/*------------------------------*/
-+#define UNIFIED_SECONDARY_INTERRUPT  0
-+#define AVALANCHE_EXT_INT_0          1
-+#define AVALANCHE_EXT_INT_1          2
-+#define AVALANCHE_EXT_INT_2          3
-+#define AVALANCHE_EXT_INT_3          4
-+#define AVALANCHE_TIMER_0_INT        5
-+#define AVALANCHE_TIMER_1_INT        6
-+#define AVALANCHE_UART0_INT          7
-+#define AVALANCHE_UART1_INT          8
-+#define AVALANCHE_PDMA_INT0          9
-+#define AVALANCHE_PDMA_INT1          10
-+#define AVALANCHE_HDLC_TXA           11
-+#define AVALANCHE_HDLC_TXB           12
-+#define AVALANCHE_HDLC_RXA           13
-+#define AVALANCHE_HDLC_RXB           14
-+#define AVALANCHE_ATM_SAR_TXA        15
-+#define AVALANCHE_ATM_SAR_TXB        16
-+#define AVALANCHE_ATM_SAR_RXA        17
-+#define AVALANCHE_ATM_SAR_RXB        18
-+#define AVALANCHE_MAC_TXA            19
-+#define AVALANCHE_MAC_RXA            20
-+#define AVALANCHE_DSP_SUB0           21
-+#define AVALANCHE_DSP_SUB1           22
-+#define AVALANCHE_DES_INT            23
-+#define AVALANCHE_USB_INT            24
-+#define AVALANCHE_PCI_INTA           25
-+#define AVALANCHE_PCI_INTB           26
-+#define AVALANCHE_PCI_INTC           27
-+/*  Line #28  Reserved               */
-+#define AVALANCHE_I2CM_INT           29
-+#define AVALANCHE_PDMA_INT2          30
-+#define AVALANCHE_PDMA_INT3          31
-+#define AVALANCHE_CODEC              32
-+#define AVALANCHE_MAC_TXB            33
-+#define AVALANCHE_MAC_RXB            34
-+/*  Line #35  Reserved               */
-+/*  Line #36  Reserved               */
-+/*  Line #37  Reserved               */
-+/*  Line #38  Reserved               */
-+/*  Line #39  Reserved               */
++      outb(value, info->port + (offset * 4));      
++}

 +
 +

-+#define DEBUG_MISSED_INTS 1

 +
 +

-+#ifdef DEBUG_MISSED_INTS
-+struct debug_missed_int
++static _INLINE_ void serial_outp(struct async_struct *info, int offset,
++              int value)

 +{
 +{

-+  unsigned int atm_sar_txa;
-+  unsigned int atm_sar_txb;
-+  unsigned int atm_sar_rxa;
-+  unsigned int atm_sar_rxb;
-+  unsigned int mac_txa;
-+  unsigned int mac_rxa;
-+  unsigned int mac_txb;
-+  unsigned int mac_rxb;
-+};
-+#endif /* DEBUG_MISSED_INTS */
-+
-+/*-----------------------------------*/
-+/* Avalanche Secondary Interrupts    */
-+/*-----------------------------------*/
-+#define PRIMARY_INTS                 40
-+
-+#define AVALANCHE_HDLC_STATUS        (0 + PRIMARY_INTS)
-+#define AVALANCHE_SAR_STATUS         (1 + PRIMARY_INTS)
-+/*  Line #02  Reserved               */
-+#define AVALANCHE_ETH_MACA_LNK_CHG   (3 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACA_MGT       (4 + PRIMARY_INTS)
-+#define AVALANCHE_PCI_STATUS_INT     (5 + PRIMARY_INTS)
-+/*  Line #06  Reserved               */
-+#define AVALANCHE_EXTERN_MEM_INT     (7 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_A_DOG          (8 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_B_DOG          (9 + PRIMARY_INTS)
-+/*  Line #10-#20 Reserved            */
-+#define AVALANCHE_ETH_MACB_LNK_CHG   (21 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACB_MGT       (22 + PRIMARY_INTS)
-+#define AVALANCHE_AAL2_STATUS        (23 + PRIMARY_INTS)
-+/*  Line #24-#31 Reserved            */
-+
-+#define AVALANCHEINT_UART0        LNXINTNUM(AVALANCHE_UART0_INT)
-+#define AVALANCHEINT_UART1        LNXINTNUM(AVALANCHE_UART1_INT)
-+#define SEADINT_UART0    3   /* TTYS0 interrupt on SEAD */
-+#define SEADINT_UART1    4   /* TTYS1 interrupt on SEAD */
-+
-+#ifdef JIMK_INT_CTRLR
-+/*-----------------------------------*/
-+/* Jim Kennedy's Interrupt Controller*/
-+/*-----------------------------------*/
-+
-+/* to clear the interrupt write the bit back to the status reg */
-+
-+#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
-+#define JIMK_INT_MASK   (*(volatile unsigned int *)(0xA8612404))
-+#define JIMK_SAR_STATUS  (1<<0)
-+#define JIMK_SAR_TX_A    (1<<1)
-+#define JIMK_SAR_TX_B    (1<<2)
-+#define JIMK_SAR_RX_A    (1<<3)
-+#define JIMK_SAR_RX_B    (1<<4)
-+#define JIMK_AAL2_STATUS (1<<5)
-+#define JIMK_UART0_INT   (1<<11)
-+
-+#ifdef SEAD_USB_DEVELOPMENT
-+#define JIMK_USB_INT     (1<<0)
-+#endif /* SEAD_USB_DEVELOPMENT */
++#ifdef CONFIG_SERIAL_NOPAUSE_IO
++      outb(value, info->port + (offset * 4));
++#else
++      outb_p(value, info->port + (offset * 4));
++#endif
++}

 +
 +

-+#endif /* JIMK_INT_CTRLR */
++#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
+ 
+ #include <asm/mips-boards/atlas.h>
+ 
+@@ -478,8 +511,10 @@
+  * needed for certain old 386 machines, I've left these #define's
+  * in....
+  */
++#ifndef CONFIG_AR7
+ #define serial_inp(info, offset)              serial_in(info, offset)
+ #define serial_outp(info, offset, value)      serial_out(info, offset, value)
++#endif
+ 
+ 
+ /*
+@@ -1728,7 +1763,15 @@
+                       /* Special case since 134 is really 134.5 */
+                       quot = (2*baud_base / 269);
+               else if (baud)
++#ifdef CONFIG_AR7
++                      quot = (CONFIG_AR7_SYS*500000) / baud;

 +
 +

-+extern void avalanche_int_set(int channel, int line);
-+extern void avalancheint_init(void);
++              if ((quot%16)>7)
++                      quot += 8;
++              quot /=16;
++#else
+                       quot = baud_base / baud;
++#endif
+       }
+       /* If the quotient is zero refuse the change */
+       if (!quot && old_termios) {
+@@ -5552,8 +5595,10 @@
+               state->irq = irq_cannonicalize(state->irq);
+               if (state->hub6)
+                       state->io_type = SERIAL_IO_HUB6;
++#ifndef CONFIG_AR7
+               if (state->port && check_region(state->port,8))
+                       continue;
++#endif
+ #ifdef CONFIG_MCA                     
+               if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
+                       continue;
+@@ -6009,7 +6054,15 @@
+       info->io_type = state->io_type;
+       info->iomem_base = state->iomem_base;
+       info->iomem_reg_shift = state->iomem_reg_shift;
++#ifdef CONFIG_AR7
++      quot = (CONFIG_AR7_SYS*500000) / baud;

 +
 +

++      if ((quot%16)>7)
++              quot += 8;
++      quot /=16;
++#else
+       quot = state->baud_base / baud;
++#endif
+       cval = cflag & (CSIZE | CSTOPB);
+ #if defined(__powerpc__) || defined(__alpha__)
+       cval >>= 8;
+diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
+--- linux.old/include/asm-mips/ar7/ar7.h       1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/ar7.h       2005-08-12 19:32:05.147223992 +0200
+@@ -0,0 +1,33 @@
++/*
++ * $Id$
++ * Copyright (C) $Date$  $Author$
++ * 
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ * 
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ * 
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
++ *
++ */

 +
 +

-+#endif /* !(_MIPS_AVALANCHEINT_H) */
++#ifndef _AR7_H
++#define _AR7_H

 +
 +

++#include <asm/addrspace.h>
++#include <linux/config.h>

 +
 +

++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))

 +
 +

++#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
++#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
++#define AR7_BASE_BAUD ( 3686400 / 16 )

 +
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,273 @@
++#endif
+diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
+--- linux.old/include/asm-mips/ar7/avalanche_intc.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_intc.h    2005-08-12 19:32:05.148223840 +0200
+@@ -0,0 +1,283 @@

 + /*
 + * Nitin Dhingra, iamnd@ti.com
 + * Copyright (C) 2000 Texas Instruments Inc.
 + /*
 + * Nitin Dhingra, iamnd@ti.com
 + * Copyright (C) 2000 Texas Instruments Inc.


@@ -4063,6 +3773,16 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/in
 +#ifndef _AVALANCHE_INTC_H
 +#define _AVALANCHE_INTC_H
 +
 +#ifndef _AVALANCHE_INTC_H
 +#define _AVALANCHE_INTC_H
 +

++/* ----- */
++
++#define KSEG1_BASE                  0xA0000000
++#define KSEG_INV_MASK               0x1FFFFFFF /* Inverted mask for kseg address */
++#define PHYS_ADDR(addr)             ((addr) & KSEG_INV_MASK)
++#define PHYS_TO_K1(addr)            (PHYS_ADDR(addr)|KSEG1_BASE)
++#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
++
++/* ----- */
++

 +#define MIPS_EXCEPTION_OFFSET 8
 +
 +/******************************************************************************
 +#define MIPS_EXCEPTION_OFFSET 8
 +
 +/******************************************************************************


@@ -4296,79 +4016,199 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/in
 +#define AVALANCHE_VDMA_VT_TX_INT     38
 +#define AVALANCHE_ADSLSS_INT         39
 +
 +#define AVALANCHE_VDMA_VT_TX_INT     38
 +#define AVALANCHE_ADSLSS_INT         39
 +

-+/*-----------------------------------*/
-+/* Sangam Secondary Interrupts    */
-+/*-----------------------------------*/
-+#define PRIMARY_INTS                 40
++/*-----------------------------------*/
++/* Sangam Secondary Interrupts    */
++/*-----------------------------------*/
++#define PRIMARY_INTS                 40
++
++#define EMIF_INT                    (7 + PRIMARY_INTS)
++
++
++extern void avalanche_int_set(int channel, int line);
++
++
++#endif /* _AVALANCHE_INTC_H */
+diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
+--- linux.old/include/asm-mips/ar7/avalanche_misc.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_misc.h    2005-08-12 19:32:05.148223840 +0200
+@@ -0,0 +1,174 @@
++#ifndef _AVALANCHE_MISC_H_
++#define _AVALANCHE_MISC_H_
++
++typedef enum AVALANCHE_ERR_t
++{
++    AVALANCHE_ERR_OK        = 0,    /* OK or SUCCESS */
++    AVALANCHE_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
++
++    /* Pointers and args */
++    AVALANCHE_ERR_INVARG        = -2,   /* Invaild argument to the call */
++    AVALANCHE_ERR_NULLPTR       = -3,   /* NULL pointer */
++    AVALANCHE_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
++
++    /* Memory issues */
++    AVALANCHE_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
++    AVALANCHE_ERR_FREE_FAIL     = -11,  /* free failed */
++    AVALANCHE_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
++    AVALANCHE_ERR_BUF_LINK      = -13,  /* buffer linking failed */
++
++    /* Device issues */
++    AVALANCHE_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
++    AVALANCHE_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
++
++    AVALANCHE_ERR_INVID     = -30   /* Invalid ID */
++
++} AVALANCHE_ERR;
++
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/
++
++typedef enum AVALANCHE_RESET_MODULE_tag
++{
++    RESET_MODULE_UART0      = 0,
++    RESET_MODULE_UART1      = 1,
++    RESET_MODULE_I2C        = 2,
++    RESET_MODULE_TIMER0     = 3,
++    RESET_MODULE_TIMER1     = 4,
++    RESET_MODULE_GPIO       = 6,
++    RESET_MODULE_ADSLSS     = 7,
++    RESET_MODULE_USBS       = 8,
++    RESET_MODULE_SAR        = 9,
++    RESET_MODULE_VDMA_VT    = 11,
++    RESET_MODULE_FSER       = 12,
++    RESET_MODULE_VLYNQ1     = 16,
++    RESET_MODULE_EMAC0      = 17,
++    RESET_MODULE_DMA        = 18,
++    RESET_MODULE_BIST       = 19,
++    RESET_MODULE_VLYNQ0     = 20,
++    RESET_MODULE_EMAC1      = 21,
++    RESET_MODULE_MDIO       = 22,
++    RESET_MODULE_ADSLSS_DSP = 23,
++    RESET_MODULE_EPHY       = 26
++} AVALANCHE_RESET_MODULE_T;
++
++typedef enum AVALANCHE_RESET_CTRL_tag
++{
++    IN_RESET        = 0,
++    OUT_OF_RESET
++} AVALANCHE_RESET_CTRL_T;
++
++typedef enum AVALANCHE_SYS_RST_MODE_tag
++{
++    RESET_SOC_WITH_MEMCTRL      = 1,    /* SW0 bit in SWRCR register */
++    RESET_SOC_WITHOUT_MEMCTRL   = 2     /* SW1 bit in SWRCR register */
++} AVALANCHE_SYS_RST_MODE_T;
++
++typedef enum AVALANCHE_SYS_RESET_STATUS_tag
++{
++    HARDWARE_RESET = 0,
++    SOFTWARE_RESET0,            /* Caused by writing 1 to SW0 bit in SWRCR register */
++    WATCHDOG_RESET,
++    SOFTWARE_RESET1             /* Caused by writing 1 to SW1 bit in SWRCR register */
++} AVALANCHE_SYS_RESET_STATUS_T;
++
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
++
++typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++
++typedef enum AVALANCHE_POWER_CTRL_tag
++{
++    POWER_CTRL_POWER_UP = 0,
++    POWER_CTRL_POWER_DOWN
++} AVALANCHE_POWER_CTRL_T;

 +
 +

-+#define EMIF_INT                    (7 + PRIMARY_INTS)
++typedef enum AVALANCHE_SYS_POWER_MODE_tag
++{
++    GLOBAL_POWER_MODE_RUN       = 0,    /* All system is up */
++    GLOBAL_POWER_MODE_IDLE,             /* MIPS is power down, all peripherals working */
++    GLOBAL_POWER_MODE_STANDBY,          /* Chip in power down, but clock to ADSKL subsystem is running */
++    GLOBAL_POWER_MODE_POWER_DOWN        /* Total chip is powered down */
++} AVALANCHE_SYS_POWER_MODE_T;

 +
 +

++void avalanche_power_ctrl(unsigned int power_module,  AVALANCHE_POWER_CTRL_T power_ctrl);
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);

 +
 +

-+extern void avalanche_int_set(int channel, int line);
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/

 +
 +

++typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
++{
++    WAKEUP_INT0 = 1,
++    WAKEUP_INT1 = 2,
++    WAKEUP_INT2 = 4,
++    WAKEUP_INT3 = 8
++} AVALANCHE_WAKEUP_INTERRUPT_T;

 +
 +

-+#endif /* _AVALANCHE_INTC_H */
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,54 @@
-+/* $Id$
-+ *
-+ * prom.h
-+ *
-+ * Carsten Langgaard, carstenl@mips.com
-+ * Copyright (C) 1999 MIPS Technologies, Inc.
-+ *
-+ * ########################################################################
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ * Sead bootprom interface for the Linux kernel.
-+ *
-+ */
++typedef enum TNETV1050_WAKEUP_CTRL_tag
++{
++    WAKEUP_DISABLED = 0,
++    WAKEUP_ENABLED
++} AVALANCHE_WAKEUP_CTRL_T;

 +
 +

-+#ifndef _MIPS_PROM_H
-+#define _MIPS_PROM_H
-+
-+extern char *prom_getcmdline(void);
-+extern char *prom_getenv(char *name);
-+extern void setup_prom_printf(void);
-+extern void prom_printf(char *fmt, ...);
-+extern void prom_init_cmdline(void);
-+extern void prom_meminit(void);
-+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-+extern void prom_free_prom_memory (void);
-+extern void sead_display_message(const char *str);
-+extern void sead_display_word(unsigned int num);
-+extern int get_ethernet_addr(char *ethernet_addr);
-+
-+/* Memory descriptor management. */
-+#define PROM_MAX_PMEMBLOCKS    32
-+struct prom_pmemblock {
-+        unsigned long base; /* Within KSEG0. */
-+        unsigned int size;  /* In bytes. */
-+        unsigned int type;  /* free or prom memory */
-+};
++typedef enum TNETV1050_WAKEUP_POLARITY_tag
++{
++    WAKEUP_ACTIVE_HIGH = 0,
++    WAKEUP_ACTIVE_LOW
++} AVALANCHE_WAKEUP_POLARITY_T;
++
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++                           AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
++                           AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
++
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++typedef enum AVALANCHE_GPIO_PIN_MODE_tag
++{
++    FUNCTIONAL_PIN = 0,
++    GPIO_PIN = 1
++} AVALANCHE_GPIO_PIN_MODE_T;
++
++typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
++{
++    GPIO_OUTPUT_PIN = 0,
++    GPIO_INPUT_PIN = 1
++} AVALANCHE_GPIO_PIN_DIRECTION_T;
++
++typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
++
++void avalanche_gpio_init(void);
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++                         AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++                         AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
++                         AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++                         AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
++int avalanche_gpio_in_bit(unsigned int gpio_pin);
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);

 +
 +

++unsigned int avalanche_get_chip_version_info(void);

 +
 +

-+#endif /* !(_MIPS_PROM_H) */
++unsigned int avalanche_get_vbus_freq(void);
++void         avalanche_set_vbus_freq(unsigned int);

 +
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h     2005-06-14 15:36:59.000000000 +0200
++
++typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
++unsigned int avalanche_is_mdix_on_chip(void);
++
++#endif
+diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
+--- linux.old/include/asm-mips/ar7/avalanche_regs.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_regs.h    2005-08-12 19:32:05.149223688 +0200

 @@ -0,0 +1,567 @@
 +/* 
 + *  $Id$
 @@ -0,0 +1,567 @@
 +/* 
 + *  $Id$


@@ -4930,17 +4770,358 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h linux-2.4.30.dev/in
 +
 +#define VMAC_STATS_BASE(X)     (X + 0x00000400)
 +
 +
 +#define VMAC_STATS_BASE(X)     (X + 0x00000400)
 +

++#endif __AVALANCHE_REGS_H
++
++
++
++
++
++
+diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
+--- linux.old/include/asm-mips/ar7/if_port.h   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/if_port.h   2005-08-12 19:32:05.149223688 +0200
+@@ -0,0 +1,26 @@
++/*******************************************************************************   
++ * FILE PURPOSE:    Interface port id Header file                                      
++ *******************************************************************************   
++ * FILE NAME:       if_port.h                                                   
++ *                                                                                 
++ * DESCRIPTION:     Header file carrying information about port ids of interfaces                             
++ *                                                                                 
++ *                                                                                 
++ * (C) Copyright 2003, Texas Instruments, Inc                                      
++ ******************************************************************************/   
++#ifndef _IF_PORT_H_
++#define _IF_PORT_H_
++
++#define AVALANCHE_CPMAC_LOW_PORT_ID         0
++#define AVALANCHE_CPMAC_HIGH_PORT_ID        1    
++#define AVALANCHE_USB_PORT_ID               2
++#define AVALANCHE_WLAN_PORT_ID              3
++
++
++#define AVALANCHE_MARVELL_BASE_PORT_ID      4
++
++/* The marvell ports occupy port ids from  4 to 8 */
++/* so the next port id number should start at 9   */
++
++
++#endif /* _IF_PORT_H_ */
+diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
+--- linux.old/include/asm-mips/ar7/sangam_boards.h     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/sangam_boards.h     2005-08-12 19:32:05.150223536 +0200
+@@ -0,0 +1,77 @@
++#ifndef _SANGAM_BOARDS_H
++#define _SANGAM_BOARDS_H
++
++// Let us define board specific information here. 
++
++
++#if defined(CONFIG_AR7DB)
++
++#define AFECLK_FREQ                                 35328000
++#define REFCLK_FREQ                                 25000000
++#define OSC3_FREQ                                   24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555  
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
++
++#endif
++
++
++#if defined(CONFIG_AR7RD)
++#define AFECLK_FREQ                                 35328000
++#define REFCLK_FREQ                                 25000000
++#define OSC3_FREQ                                   24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7WI)
++#define AFECLK_FREQ                                 35328000
++#define REFCLK_FREQ                                 25000000
++#define OSC3_FREQ                                   24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7V)
++#define AFECLK_FREQ                                 35328000
++#define REFCLK_FREQ                                 25000000
++#define OSC3_FREQ                                   24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7WRD) 
++#define AFECLK_FREQ                                 35328000
++#define REFCLK_FREQ                                 25000000
++#define OSC3_FREQ                                   24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
++#endif
++
++
++#if defined(CONFIG_AR7VWI) 
++#define AFECLK_FREQ                                 35328000
++#define REFCLK_FREQ                                 25000000
++#define OSC3_FREQ                                   24000000
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
++#endif
++
++
++#if defined CONFIG_SEAD2
++#define AVALANCHE_LOW_CPMAC_PHY_MASK                0xAAAAAAAA
++#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
++#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0
++#include <asm/mips-boards/sead.h>
++#endif
++
++

 +#endif
 +#endif

+diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
+--- linux.old/include/asm-mips/ar7/sangam.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/sangam.h    2005-08-12 19:32:05.150223536 +0200
+@@ -0,0 +1,180 @@
++#ifndef _SANGAM_H_
++#define _SANGAM_H_
++
++#include <linux/config.h>
++#include <asm/addrspace.h>
++
++/*----------------------------------------------------
++ * Sangam's Module Base Addresses
++ *--------------------------------------------------*/
++#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE       (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
++#define AVALANCHE_BROADBAND_INTERFACE__BASE   (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */        
++#define AVALANCHE_ATM_SAR_BASE                (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
++#define AVALANCHE_USB_SLAVE_BASE              (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
++#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE      (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
++#define AVALANCHE_LOW_CPMAC_BASE              (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
++#define AVALANCHE_EMIF_CONTROL_BASE           (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
++#define AVALANCHE_GPIO_BASE                   (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
++#define AVALANCHE_CLOCK_CONTROL_BASE          (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
++#define AVALANCHE_WATCHDOG_TIMER_BASE         (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */  
++#define AVALANCHE_TIMER0_BASE                 (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */  
++#define AVALANCHE_TIMER1_BASE                 (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */  
++#define AVALANCHE_UART0_REGS_BASE             (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
++#define AVALANCHE_UART1_REGS_BASE             (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
++#define AVALANCHE_I2C_BASE                    (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
++#define AVALANCHE_USB_SLAVE_CONTROL_BASE      (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
++#define AVALANCHE_MCDMA0_CTRL_BASE            (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
++#define AVALANCHE_RESET_CONTROL_BASE          (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
++#define AVALANCHE_BIST_CONTROL_BASE           (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
++#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE      (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
++#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE    (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
++#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE     (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
++#define AVALANCHE_MDIO_BASE                   (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO    */
++#define AVALANCHE_FSER_BASE                   (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
++#define AVALANCHE_INTC_BASE                   (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC  */
++#define AVALANCHE_HIGH_CPMAC_BASE             (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
++#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE     (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
++
++#define AVALANCHE_SDRAM_BASE                  0x14000000UL
++
++
++/*----------------------------------------------------
++ * Sangam Interrupt Map (Primary Interrupts)
++ *--------------------------------------------------*/
++
++#define AVALANCHE_UNIFIED_SECONDARY_INT            0
++#define AVALANCHE_EXT_INT_0                        1
++#define AVALANCHE_EXT_INT_1                        2
++/* Line#  3 to 4 are reserved                            */
++#define AVALANCHE_TIMER_0_INT                      5
++#define AVALANCHE_TIMER_1_INT                      6
++#define AVALANCHE_UART0_INT                        7
++#define AVALANCHE_UART1_INT                        8
++#define AVALANCHE_DMA_INT0                         9
++#define AVALANCHE_DMA_INT1                        10
++/* Line# 11 to 14 are reserved                    */
++#define AVALANCHE_ATM_SAR_INT                     15
++/* Line# 16 to 18 are reserved                    */
++#define AVALANCHE_LOW_CPMAC_INT                   19
++/* Line# 20 is reserved                           */
++#define AVALANCHE_LOW_VLYNQ_INT                   21
++#define AVALANCHE_CODEC_WAKEUP_INT                22
++/* Line# 23 is reserved                           */
++#define AVALANCHE_USB_SLAVE_INT                   24
++#define AVALANCHE_HIGH_VLYNQ_INT                  25
++/* Line# 26 to 27 are reserved                    */
++#define AVALANCHE_UNIFIED_PHY_INT                 28
++#define AVALANCHE_I2C_INT                         29
++#define AVALANCHE_DMA_INT2                        30
++#define AVALANCHE_DMA_INT3                        31
++/* Line# 32 is reserved                           */
++#define AVALANCHE_HIGH_CPMAC_INT                  33
++/* Line# 34 to 36 is reserved                     */
++#define AVALANCHE_VDMA_VT_RX_INT                  37
++#define AVALANCHE_VDMA_VT_TX_INT                  38
++#define AVALANCHE_ADSL_SUB_SYSTEM_INT             39
++
++
++#define AVALANCHE_EMIF_INT                        47
++
++
++
++/*-----------------------------------------------------------
++ * Sangam's Reset Bits
++ *---------------------------------------------------------*/
++
++#define AVALANCHE_UART0_RESET_BIT                  0
++#define AVALANCHE_UART1_RESET_BIT                  1
++#define AVALANCHE_I2C_RESET_BIT                    2
++#define AVALANCHE_TIMER0_RESET_BIT                 3
++#define AVALANCHE_TIMER1_RESET_BIT                 4
++/* Reset bit  5 is reserved.                       */
++#define AVALANCHE_GPIO_RESET_BIT                   6
++#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT           7
++#define AVALANCHE_USB_SLAVE_RESET_BIT              8
++#define AVALANCHE_ATM_SAR_RESET_BIT                9
++/* Reset bit 10 is reserved.                      */
++#define AVALANCHE_VDMA_VT_RESET_BIT               11
++#define AVALANCHE_FSER_RESET_BIT                  12
++/* Reset bit 13 to 15 are reserved                */
++#define AVALANCHE_HIGH_VLYNQ_RESET_BIT            16
++#define AVALANCHE_LOW_CPMAC_RESET_BIT             17
++#define AVALANCHE_MCDMA_RESET_BIT                 18
++#define AVALANCHE_BIST_RESET_BIT                  19
++#define AVALANCHE_LOW_VLYNQ_RESET_BIT             20
++#define AVALANCHE_HIGH_CPMAC_RESET_BIT            21
++#define AVALANCHE_MDIO_RESET_BIT                  22
++#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT      23
++/* Reset bit 24 to 25 are reserved                */
++#define AVALANCHE_LOW_EPHY_RESET_BIT              26
++/* Reset bit 27 to 31 are reserved                */
++
++
++#define AVALANCHE_POWER_MODULE_USBSP               0
++#define AVALANCHE_POWER_MODULE_WDTP                1
++#define AVALANCHE_POWER_MODULE_UT0P                2
++#define AVALANCHE_POWER_MODULE_UT1P                3
++#define AVALANCHE_POWER_MODULE_IICP                4
++#define AVALANCHE_POWER_MODULE_VDMAP               5
++#define AVALANCHE_POWER_MODULE_GPIOP               6
++#define AVALANCHE_POWER_MODULE_VLYNQ1P             7
++#define AVALANCHE_POWER_MODULE_SARP                8
++#define AVALANCHE_POWER_MODULE_ADSLP               9
++#define AVALANCHE_POWER_MODULE_EMIFP              10
++#define AVALANCHE_POWER_MODULE_ADSPP              12
++#define AVALANCHE_POWER_MODULE_RAMP               13
++#define AVALANCHE_POWER_MODULE_ROMP               14
++#define AVALANCHE_POWER_MODULE_DMAP               15
++#define AVALANCHE_POWER_MODULE_BISTP              16
++#define AVALANCHE_POWER_MODULE_TIMER0P            18
++#define AVALANCHE_POWER_MODULE_TIMER1P            19
++#define AVALANCHE_POWER_MODULE_EMAC0P             20
++#define AVALANCHE_POWER_MODULE_EMAC1P             22
++#define AVALANCHE_POWER_MODULE_EPHYP              24
++#define AVALANCHE_POWER_MODULE_VLYNQ0P            27
++
++
++
++
++
++/*
++ * Sangam board vectors
++ */
++
++#define AVALANCHE_VECS       (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
++
++/*-----------------------------------------------------------------------------
++ * Sangam's system register.
++ * 
++ *---------------------------------------------------------------------------*/
++#define AVALANCHE_DCL_BOOTCR          (KSEG1ADDR(0x08611A00))
++#define AVALANCHE_EMIF_SDRAM_CFG      (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
++#define AVALANCHE_RST_CTRL_PRCR       (KSEG1ADDR(0x08611600))
++#define AVALANCHE_RST_CTRL_SWRCR      (KSEG1ADDR(0x08611604))
++#define AVALANCHE_RST_CTRL_RSR        (KSEG1ADDR(0x08611600))
++
++#define AVALANCHE_POWER_CTRL_PDCR     (KSEG1ADDR(0x08610A00))
++#define AVALANCHE_WAKEUP_CTRL_WKCR    (KSEG1ADDR(0x08610A0C))
++
++#define AVALANCHE_GPIO_DATA_IN        (AVALANCHE_GPIO_BASE +  0x0)
++#define AVALANCHE_GPIO_DATA_OUT       (AVALANCHE_GPIO_BASE +  0x4)
++#define AVALANCHE_GPIO_DIR            (AVALANCHE_GPIO_BASE +  0x8)    
++#define AVALANCHE_GPIO_ENBL           (AVALANCHE_GPIO_BASE +  0xC)
++#define AVALANCHE_CVR                 (AVALANCHE_GPIO_BASE +  0x14)
++
++/*
++ * Yamon Prom print address.
++ */
++#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
++#define AVALANCHE_YAMON_PROM_PRINT_ADDR           (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
++
++#define AVALANCHE_BASE_BAUD       ( 3686400 / 16 )
++
++#define  AVALANCHE_GPIO_PIN_COUNT         32             
++#define  AVALANCHE_GPIO_OFF_MAP           {0xF34FFFC0} 
++
++#include "sangam_boards.h"
++
++#endif /*_SANGAM_H_ */
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx_err.h     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h     2005-08-12 19:32:05.171220344 +0200
+@@ -0,0 +1,42 @@
++/******************************************************************************
++ * FILE PURPOSE:    TNETD73xx Error Definations Header File
++ ******************************************************************************
++ * FILE NAME:       tnetd73xx_err.h
++ *
++ * DESCRIPTION:     Error definations for TNETD73XX
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII  
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++ 
++#ifndef __TNETD73XX_ERR_H__
++#define __TNETD73XX_ERR_H__
++
++typedef enum TNETD73XX_ERR_t
++{
++    TNETD73XX_ERR_OK        = 0,    /* OK or SUCCESS */
++    TNETD73XX_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */

 +
 +

++    /* Pointers and args */
++    TNETD73XX_ERR_INVARG        = -2,   /* Invaild argument to the call */
++    TNETD73XX_ERR_NULLPTR       = -3,   /* NULL pointer */
++    TNETD73XX_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */

 +
 +

++    /* Memory issues */
++    TNETD73XX_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
++    TNETD73XX_ERR_FREE_FAIL     = -11,  /* free failed */
++    TNETD73XX_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
++    TNETD73XX_ERR_BUF_LINK      = -13,  /* buffer linking failed */

 +
 +

++    /* Device issues */
++    TNETD73XX_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
++    TNETD73XX_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */

 +
 +

++    TNETD73XX_ERR_INVID     = -30   /* Invalid ID */

 +
 +

++} TNETD73XX_ERR;

 +
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h  2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,340 @@
++#endif /* __TNETD73XX_ERR_H__ */
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-08-12 19:32:05.151223384 +0200
+@@ -0,0 +1,338 @@

 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Common Header File
 + ******************************************************************************
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Common Header File
 + ******************************************************************************


@@ -4981,8 +5162,6 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include
 +
 +#ifndef _ASMLANGUAGE        /* This part not for assembly language */
 +
 +
 +#ifndef _ASMLANGUAGE        /* This part not for assembly language */
 +

-+#include <linux/types.h>
-+

 +extern unsigned int tnetd73xx_mips_freq;
 +extern unsigned int tnetd73xx_vbus_freq;
 +
 +extern unsigned int tnetd73xx_mips_freq;
 +extern unsigned int tnetd73xx_vbus_freq;
 +


@@ -5018,15 +5197,15 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include
 +#endif
 +
 +#ifndef KSEG0
 +#endif
 +
 +#ifndef KSEG0

-+#define KSEG0(addr)                 (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
++#define KSEG0(addr)                 (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)

 +#endif
 +
 +#ifndef KSEG1
 +#endif
 +
 +#ifndef KSEG1

-+#define KSEG1(addr)                 (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
++#define KSEG1(addr)                 (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)

 +#endif
 +
 +#ifndef KUSEG
 +#endif
 +
 +#ifndef KUSEG

-+#define KUSEG(addr)                 ((u32)(addr) & ~KSEG_MSK)
++#define KUSEG(addr)                 ((__u32)(addr) & ~KSEG_MSK)

 +#endif
 +
 +#ifndef PHYS_ADDR
 +#endif
 +
 +#ifndef PHYS_ADDR


@@ -5042,24 +5221,24 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include
 +#endif
 +
 +#ifndef REG8_ADDR
 +#endif
 +
 +#ifndef REG8_ADDR

-+#define REG8_ADDR(addr)             (volatile u8 *)(PHYS_TO_K1(addr))
-+#define REG8_DATA(addr)             (*(volatile u8 *)(PHYS_TO_K1(addr)))
++#define REG8_ADDR(addr)             (volatile __u8 *)(PHYS_TO_K1(addr))
++#define REG8_DATA(addr)             (*(volatile __u8 *)(PHYS_TO_K1(addr)))

 +#define REG8_WRITE(addr, data)      REG8_DATA(addr) = data;
 +#define REG8_WRITE(addr, data)      REG8_DATA(addr) = data;

-+#define REG8_READ(addr, data)       data = (u8) REG8_DATA(addr);
++#define REG8_READ(addr, data)       data = (__u8) REG8_DATA(addr);

 +#endif
 +
 +#ifndef REG16_ADDR
 +#endif
 +
 +#ifndef REG16_ADDR

-+#define REG16_ADDR(addr)            (volatile u16 *)(PHYS_TO_K1(addr))
-+#define REG16_DATA(addr)            (*(volatile u16 *)(PHYS_TO_K1(addr)))
++#define REG16_ADDR(addr)            (volatile __u16 *)(PHYS_TO_K1(addr))
++#define REG16_DATA(addr)            (*(volatile __u16 *)(PHYS_TO_K1(addr)))

 +#define REG16_WRITE(addr, data)     REG16_DATA(addr) = data;
 +#define REG16_WRITE(addr, data)     REG16_DATA(addr) = data;

-+#define REG16_READ(addr, data)      data = (u16) REG16_DATA(addr);
++#define REG16_READ(addr, data)      data = (__u16) REG16_DATA(addr);

 +#endif
 +
 +#ifndef REG32_ADDR
 +#endif
 +
 +#ifndef REG32_ADDR

-+#define REG32_ADDR(addr)            (volatile u32 *)(PHYS_TO_K1(addr))
-+#define REG32_DATA(addr)            (*(volatile u32 *)(PHYS_TO_K1(addr)))
++#define REG32_ADDR(addr)            (volatile __u32 *)(PHYS_TO_K1(addr))
++#define REG32_DATA(addr)            (*(volatile __u32 *)(PHYS_TO_K1(addr)))

 +#define REG32_WRITE(addr, data)     REG32_DATA(addr) = data;
 +#define REG32_WRITE(addr, data)     REG32_DATA(addr) = data;

-+#define REG32_READ(addr, data)      data = (u32) REG32_DATA(addr);
++#define REG32_READ(addr, data)      data = (__u32) REG32_DATA(addr);

 +#endif
 +
 +#ifdef  _LINK_KSEG0_                /* Application is linked into KSEG0 space */
 +#endif
 +
 +#ifdef  _LINK_KSEG0_                /* Application is linked into KSEG0 space */


@@ -5281,56 +5460,10 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include
 +
 +
 +#endif /* __TNETD73XX_H_ */
 +
 +
 +#endif /* __TNETD73XX_H_ */

-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h      2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,42 @@
-+/******************************************************************************
-+ * FILE PURPOSE:    TNETD73xx Error Definations Header File
-+ ******************************************************************************
-+ * FILE NAME:       tnetd73xx_err.h
-+ *
-+ * DESCRIPTION:     Error definations for TNETD73XX
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - PSP TII  
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+ 
-+#ifndef __TNETD73XX_ERR_H__
-+#define __TNETD73XX_ERR_H__
-+
-+typedef enum TNETD73XX_ERR_t
-+{
-+    TNETD73XX_ERR_OK        = 0,    /* OK or SUCCESS */
-+    TNETD73XX_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
-+
-+    /* Pointers and args */
-+    TNETD73XX_ERR_INVARG        = -2,   /* Invaild argument to the call */
-+    TNETD73XX_ERR_NULLPTR       = -3,   /* NULL pointer */
-+    TNETD73XX_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
-+
-+    /* Memory issues */
-+    TNETD73XX_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
-+    TNETD73XX_ERR_FREE_FAIL     = -11,  /* free failed */
-+    TNETD73XX_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
-+    TNETD73XX_ERR_BUF_LINK      = -13,  /* buffer linking failed */
-+
-+    /* Device issues */
-+    TNETD73XX_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
-+    TNETD73XX_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
-+
-+    TNETD73XX_ERR_INVID     = -30   /* Invalid ID */
-+
-+} TNETD73XX_ERR;
-+
-+#endif /* __TNETD73XX_ERR_H__ */
-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,243 @@
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h    2005-08-12 19:32:05.172220192 +0200
+@@ -0,0 +1,239 @@

 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Misc modules API Header
 + ******************************************************************************
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Misc modules API Header
 + ******************************************************************************


@@ -5350,10 +5483,6 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/in
 +#ifndef __TNETD73XX_MISC_H__
 +#define __TNETD73XX_MISC_H__
 +
 +#ifndef __TNETD73XX_MISC_H__
 +#define __TNETD73XX_MISC_H__
 +

-+#include <linux/types.h>
-+
-+#define BOOTCR_MIPS_ASYNC_MODE  (1 << 25)
-+

 +/*****************************************************************************
 + * Reset Control Module
 + *****************************************************************************/
 +/*****************************************************************************
 + * Reset Control Module
 + *****************************************************************************/


@@ -5511,9 +5640,9 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/in
 +    CLKC_ADSLSS
 +} TNETD73XX_CLKC_ID_T;
 +
 +    CLKC_ADSLSS
 +} TNETD73XX_CLKC_ID_T;
 +

-+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
-+u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
++void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
++TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
++__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);

 +
 +/*****************************************************************************
 + * GPIO Control 
 +
 +/*****************************************************************************
 + * GPIO Control 


@@ -5571,17 +5700,17 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/in
 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
 +
 +/* TNETD73XX Revision */
 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
 +
 +/* TNETD73XX Revision */

-+u32 tnetd73xx_get_revision(void);
++__u32 tnetd73xx_get_revision(void);

 +
 +#endif /* __TNETD73XX_MISC_H__ */
 +
 +#endif /* __TNETD73XX_MISC_H__ */

-diff -urN linux-2.4.30/include/asm-mips/io.h linux-2.4.30.dev/include/asm-mips/io.h
---- linux-2.4.30/include/asm-mips/io.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/io.h     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
+--- linux.old/include/asm-mips/io.h    2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/io.h    2005-08-12 21:13:28.133469520 +0200

 @@ -63,8 +63,12 @@
  #ifdef CONFIG_64BIT_PHYS_ADDR
  #define page_to_phys(page)    ((u64)(page - mem_map) << PAGE_SHIFT)
  #else
 @@ -63,8 +63,12 @@
  #ifdef CONFIG_64BIT_PHYS_ADDR
  #define page_to_phys(page)    ((u64)(page - mem_map) << PAGE_SHIFT)
  #else

-+#ifdef CONFIG_AR7_PAGING
++#ifdef CONFIG_AR7

 +#define page_to_phys(page)    (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
 +#else 
  #define page_to_phys(page)    ((page - mem_map) << PAGE_SHIFT)
 +#define page_to_phys(page)    (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
 +#else 
  #define page_to_phys(page)    ((page - mem_map) << PAGE_SHIFT)


@@ -5590,9 +5719,9 @@ diff -urN linux-2.4.30/include/asm-mips/io.h linux-2.4.30.dev/include/asm-mips/i
  
  #define IO_SPACE_LIMIT 0xffff
  
  
  #define IO_SPACE_LIMIT 0xffff
  

-diff -urN linux-2.4.30/include/asm-mips/irq.h linux-2.4.30.dev/include/asm-mips/irq.h
---- linux-2.4.30/include/asm-mips/irq.h        2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/irq.h    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
+--- linux.old/include/asm-mips/irq.h   2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/irq.h   2005-08-12 19:32:05.172220192 +0200

 @@ -14,7 +14,12 @@
  #include <linux/config.h>
  #include <linux/linkage.h>
 @@ -14,7 +14,12 @@
  #include <linux/config.h>
  #include <linux/linkage.h>


@@ -5606,14 +5735,14 @@ diff -urN linux-2.4.30/include/asm-mips/irq.h linux-2.4.30.dev/include/asm-mips/
  
  #ifdef CONFIG_I8259
  static inline int irq_cannonicalize(int irq)
  
  #ifdef CONFIG_I8259
  static inline int irq_cannonicalize(int irq)

-diff -urN linux-2.4.30/include/asm-mips/page.h linux-2.4.30.dev/include/asm-mips/page.h
---- linux-2.4.30/include/asm-mips/page.h       2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/page.h   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
+--- linux.old/include/asm-mips/page.h  2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/page.h  2005-08-12 21:13:38.481896320 +0200

 @@ -129,7 +129,11 @@
  
  #define __pa(x)               ((unsigned long) (x) - PAGE_OFFSET)
  #define __va(x)               ((void *)((unsigned long) (x) + PAGE_OFFSET))
 @@ -129,7 +129,11 @@
  
  #define __pa(x)               ((unsigned long) (x) - PAGE_OFFSET)
  #define __va(x)               ((void *)((unsigned long) (x) + PAGE_OFFSET))

-+#ifdef CONFIG_AR7_PAGING
++#ifdef CONFIG_AR7

 +#define virt_to_page(kaddr)   phys_to_page(__pa(kaddr))
 +#else
  #define virt_to_page(kaddr)   (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
 +#define virt_to_page(kaddr)   phys_to_page(__pa(kaddr))
 +#else
  #define virt_to_page(kaddr)   (mem_map + (__pa(kaddr) >> PAGE_SHIFT))


@@ -5621,15 +5750,15 @@ diff -urN linux-2.4.30/include/asm-mips/page.h linux-2.4.30.dev/include/asm-mips
  #define VALID_PAGE(page)      ((page - mem_map) < max_mapnr)
  
  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
  #define VALID_PAGE(page)      ((page - mem_map) < max_mapnr)
  
  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \

-diff -urN linux-2.4.30/include/asm-mips/pgtable-32.h linux-2.4.30.dev/include/asm-mips/pgtable-32.h
---- linux-2.4.30/include/asm-mips/pgtable-32.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/pgtable-32.h     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
+--- linux.old/include/asm-mips/pgtable-32.h    2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/pgtable-32.h    2005-08-12 21:13:46.898616784 +0200

 @@ -108,7 +108,18 @@
   * and a page entry and page directory to the page they refer to.
   */
  
 -#ifdef CONFIG_CPU_VR41XX
 @@ -108,7 +108,18 @@
   * and a page entry and page directory to the page they refer to.
   */
  
 -#ifdef CONFIG_CPU_VR41XX

-+#if defined(CONFIG_AR7_PAGING)
++#if defined(CONFIG_AR7)

 +#define mk_pte(page, pgprot)                                          \
 +({                                                                    \
 +      pte_t   __pte;                                                  \
 +#define mk_pte(page, pgprot)                                          \
 +({                                                                    \
 +      pte_t   __pte;                                                  \


@@ -5657,16 +5786,16 @@ diff -urN linux-2.4.30/include/asm-mips/pgtable-32.h linux-2.4.30.dev/include/as
  }
  
 -#ifdef CONFIG_CPU_VR41XX
  }
  
 -#ifdef CONFIG_CPU_VR41XX

-+#if defined(CONFIG_AR7_PAGING)
++#if defined(CONFIG_AR7)

 +#define phys_to_page(phys)    (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
 +#define pte_page(x)           phys_to_page(pte_val(x))
 +#elif defined(CONFIG_CPU_VR41XX)
  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
  #else
 +#define phys_to_page(phys)    (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
 +#define pte_page(x)           phys_to_page(pte_val(x))
 +#elif defined(CONFIG_CPU_VR41XX)
  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
  #else

-diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mips/serial.h
---- linux-2.4.30/include/asm-mips/serial.h     2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/serial.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
+--- linux.old/include/asm-mips/serial.h        2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/include/asm-mips/serial.h        2005-08-12 19:32:05.174219888 +0200

 @@ -65,6 +65,15 @@
  
  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
 @@ -65,6 +65,15 @@
  
  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)


@@ -5674,8 +5803,8 @@ diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mi
 +#ifdef CONFIG_AR7
 +#include <asm/ar7/ar7.h>
 +#define AR7_SERIAL_PORT_DEFNS  \
 +#ifdef CONFIG_AR7
 +#include <asm/ar7/ar7.h>
 +#define AR7_SERIAL_PORT_DEFNS  \

-+      { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
-+      { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS }, 
++      { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
++      { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS }, 

 +#else 
 +#define AR7_SERIAL_PORT_DEFNS
 +#endif
 +#else 
 +#define AR7_SERIAL_PORT_DEFNS
 +#endif


@@ -5691,3 +5820,15 @@ diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mi
        ATLAS_SERIAL_PORT_DEFNS                 \
        AU1000_SERIAL_PORT_DEFNS                \
        COBALT_SERIAL_PORT_DEFNS                \
        ATLAS_SERIAL_PORT_DEFNS                 \
        AU1000_SERIAL_PORT_DEFNS                \
        COBALT_SERIAL_PORT_DEFNS                \

+diff -urN linux.old/Makefile linux.dev/Makefile
+--- linux.old/Makefile 2005-07-10 03:00:44.000000000 +0200
++++ linux.dev/Makefile 2005-08-12 19:32:05.122227792 +0200
+@@ -91,7 +91,7 @@
+ 
+ CPPFLAGS := -D__KERNEL__ -I$(HPATH)
+ 
+-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
++CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
+         -fno-strict-aliasing -fno-common
+ ifndef CONFIG_FRAME_POINTER
+ CFLAGS += -fomit-frame-pointer