-+/* For ddr: */
-+#define MEMC_CONFIG_INIT 0x00048000
-+#define MEMC_DRAMTIM2_INIT 0x000754d8
-+#define MEMC_DRAMTIM25_INIT 0x000754d9
-+#define MEMC_RDNCDLCOR_INIT 0x00000000
-+#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
-+#define MEMC_WRNCDLCOR_INIT 0x49351200
-+#define MEMC_1_WRNCDLCOR_INIT 0x14500200
-+#define MEMC_DQSGATENCDL_INIT 0x00030000
-+#define MEMC_MISCDLYCTL_INIT 0x21061c1b
-+#define MEMC_1_MISCDLYCTL_INIT 0x21021400
-+#define MEMC_NCDLCTL_INIT 0x00002001
-+#define MEMC_CONTROL_INIT0 0x00000002
-+#define MEMC_CONTROL_INIT1 0x00000008
-+#define MEMC_MODEBUF_INIT0 0x00004000
-+#define MEMC_CONTROL_INIT2 0x00000010
-+#define MEMC_MODEBUF_INIT1 0x00000100
-+#define MEMC_CONTROL_INIT3 0x00000010
-+#define MEMC_CONTROL_INIT4 0x00000008
-+#define MEMC_REFRESH_INIT 0x0000840f
-+#define MEMC_CONTROL_INIT5 0x00000004
-+#define MEMC_MODEBUF_INIT2 0x00000000
-+#define MEMC_CONTROL_INIT6 0x00000010
-+#define MEMC_CONTROL_INIT7 0x00000001
-+
-+
-+/* This is for DDRM16X16X2 */
-+#define MEMC_DDR_INIT 0x0009
-+#define MEMC_DDR_MODE 0x62
-+#define MEMC_DDR_NCDL 0x0005050a
-+#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
-+
-+/* mask for sdr/ddr calibration registers */
-+#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
-+#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
-+#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
-+
-+/* masks for miscdlyctl registers */
-+#define MEMC_MISC_SM_MASK 0x30000000
-+#define MEMC_MISC_SM_SHIFT 28
-+#define MEMC_MISC_SD_MASK 0x0f000000
-+#define MEMC_MISC_SD_SHIFT 24
-+
-+/* hw threshhold for calculating wr/rd for sdr memc */
-+#define MEMC_CD_THRESHOLD 128
-+
-+/* Low bit of init register says if memc is ddr or sdr */
-+#define MEMC_CONFIG_DDR 0x00000001
-+
-+#endif /* _SBMEMC_H */
-diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
---- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-05-02 17:20:14.000000000 +0200
-@@ -0,0 +1,114 @@
-+/*
-+ * HND SiliconBackplane PCI core hardware definitions.
-+ *
-+ * Copyright 2006, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
-+ */
-+
-+#ifndef _sbpci_h_
-+#define _sbpci_h_
-+
-+#ifndef _LANGUAGE_ASSEMBLY
-+
-+/* cpp contortions to concatenate w/arg prescan */
-+#ifndef PAD
-+#define _PADLINE(line) pad ## line
-+#define _XSTR(line) _PADLINE(line)
-+#define PAD _XSTR(__LINE__)
-+#endif
-+
-+/* Sonics side: PCI core and host control registers */
-+typedef struct sbpciregs {
-+ uint32 control; /* PCI control */
-+ uint32 PAD[3];
-+ uint32 arbcontrol; /* PCI arbiter control */
-+ uint32 PAD[3];
-+ uint32 intstatus; /* Interrupt status */
-+ uint32 intmask; /* Interrupt mask */
-+ uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
-+ uint32 PAD[9];
-+ uint32 bcastaddr; /* Sonics broadcast address */
-+ uint32 bcastdata; /* Sonics broadcast data */
-+ uint32 PAD[2];
-+ uint32 gpioin; /* ro: gpio input (>=rev2) */
-+ uint32 gpioout; /* rw: gpio output (>=rev2) */
-+ uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
-+ uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
-+ uint32 PAD[36];
-+ uint32 sbtopci0; /* Sonics to PCI translation 0 */
-+ uint32 sbtopci1; /* Sonics to PCI translation 1 */
-+ uint32 sbtopci2; /* Sonics to PCI translation 2 */
-+ uint32 PAD[189];
-+ uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
-+ uint16 sprom[36]; /* SPROM shadow Area */
-+ uint32 PAD[46];
-+} sbpciregs_t;
-+
-+#endif /* _LANGUAGE_ASSEMBLY */
-+
-+/* PCI control */
-+#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
-+#define PCI_RST 0x02 /* Value driven out to pin */
-+#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
-+#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
-+
-+/* PCI arbiter control */
-+#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
-+#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
-+/* ParkID - for PCI corerev >= 8 */
-+#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
-+#define PCI_PARKID_SHIFT 2
-+#define PCI_PARKID_EXT0 0 /* External master 0 */
-+#define PCI_PARKID_EXT1 1 /* External master 1 */
-+#define PCI_PARKID_EXT2 2 /* External master 2 */
-+#define PCI_PARKID_INT 3 /* Internal master */
-+#define PCI_PARKID_LAST 4 /* Last active master */
++/* For ddr: */
++#define MEMC_CONFIG_INIT 0x00048000
++#define MEMC_DRAMTIM2_INIT 0x000754d8
++#define MEMC_DRAMTIM25_INIT 0x000754d9
++#define MEMC_RDNCDLCOR_INIT 0x00000000
++#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
++#define MEMC_WRNCDLCOR_INIT 0x49351200
++#define MEMC_1_WRNCDLCOR_INIT 0x14500200
++#define MEMC_DQSGATENCDL_INIT 0x00030000
++#define MEMC_MISCDLYCTL_INIT 0x21061c1b
++#define MEMC_1_MISCDLYCTL_INIT 0x21021400
++#define MEMC_NCDLCTL_INIT 0x00002001
++#define MEMC_CONTROL_INIT0 0x00000002
++#define MEMC_CONTROL_INIT1 0x00000008
++#define MEMC_MODEBUF_INIT0 0x00004000
++#define MEMC_CONTROL_INIT2 0x00000010
++#define MEMC_MODEBUF_INIT1 0x00000100
++#define MEMC_CONTROL_INIT3 0x00000010
++#define MEMC_CONTROL_INIT4 0x00000008
++#define MEMC_REFRESH_INIT 0x0000840f
++#define MEMC_CONTROL_INIT5 0x00000004
++#define MEMC_MODEBUF_INIT2 0x00000000
++#define MEMC_CONTROL_INIT6 0x00000010
++#define MEMC_CONTROL_INIT7 0x00000001
projects / openwrt.git / blobdiff