/*
* Atheros AR71xx built-in ethernet mac driver
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
* by the Free Software Foundation.
*/
+#include <linux/cache.h>
#include "ag71xx.h"
#define AG71XX_DEFAULT_MSG_ENABLE \
| NETIF_MSG_RX_ERR \
| NETIF_MSG_TX_ERR )
-static int ag71xx_debug = -1;
+static int ag71xx_msg_level = -1;
-module_param(ag71xx_debug, int, 0);
-MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
+module_param_named(msg_level, ag71xx_msg_level, int, 0);
+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
static void ag71xx_dump_dma_regs(struct ag71xx *ag)
{
{
kfree(ring->buf);
- if (ring->descs)
- dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
- ring->descs, ring->descs_dma);
+ if (ring->descs_cpu)
+ dma_free_coherent(NULL, ring->size * ring->desc_size,
+ ring->descs_cpu, ring->descs_dma);
}
static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
{
int err;
+ int i;
+
+ ring->desc_size = sizeof(struct ag71xx_desc);
+ if (ring->desc_size % cache_line_size()) {
+ DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
+ ring, ring->desc_size,
+ roundup(ring->desc_size, cache_line_size()));
+ ring->desc_size = roundup(ring->desc_size, cache_line_size());
+ }
- ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
- &ring->descs_dma,
- GFP_ATOMIC);
- if (!ring->descs) {
+ ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
+ &ring->descs_dma, GFP_ATOMIC);
+ if (!ring->descs_cpu) {
err = -ENOMEM;
goto err;
}
goto err;
}
+ for (i = 0; i < size; i++) {
+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
+ DBG("ag71xx: ring %p, desc %d at %p\n",
+ ring, i, ring->buf[i].desc);
+ }
+
return 0;
err:
while (ring->curr != ring->dirty) {
u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
- if (!ag71xx_desc_empty(&ring->descs[i])) {
- ring->descs[i].ctrl = 0;
+ if (!ag71xx_desc_empty(ring->buf[i].desc)) {
+ ring->buf[i].desc->ctrl = 0;
dev->stats.tx_errors++;
}
int i;
for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
- ring->descs[i].next = (u32) (ring->descs_dma +
- sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
+ ring->buf[i].desc->next = (u32) (ring->descs_dma +
+ ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
- ring->descs[i].ctrl = DESC_EMPTY;
+ ring->buf[i].desc->ctrl = DESC_EMPTY;
ring->buf[i].skb = NULL;
}
int ret;
ret = 0;
- for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
- ring->descs[i].next = (u32) (ring->descs_dma +
- sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
+ ring->buf[i].desc->next = (u32) (ring->descs_dma +
+ ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
+
+ DBG("ag71xx: RX desc at %p, next is %08x\n",
+ ring->buf[i].desc,
+ ring->buf[i].desc->next);
+ }
for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
struct sk_buff *skb;
skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
ring->buf[i].skb = skb;
- ring->descs[i].data = virt_to_phys(skb->data);
- ring->descs[i].ctrl = DESC_EMPTY;
+ ring->buf[i].desc->data = virt_to_phys(skb->data);
+ ring->buf[i].desc->ctrl = DESC_EMPTY;
}
/* flush descriptors */
struct sk_buff *skb;
skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
- if (skb == NULL) {
- printk(KERN_ERR "%s: no memory for skb\n",
- ag->dev->name);
+ if (skb == NULL)
break;
- }
dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
DMA_FROM_DEVICE);
skb->dev = ag->dev;
ring->buf[i].skb = skb;
- ring->descs[i].data = virt_to_phys(skb->data);
+ ring->buf[i].desc->data = virt_to_phys(skb->data);
}
- ring->descs[i].ctrl = DESC_EMPTY;
+ ring->buf[i].desc->ctrl = DESC_EMPTY;
count++;
}
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
}
-#define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
- MAC_CFG1_SRX | MAC_CFG1_STX)
-#define AR71XX_FIFO_CFG5_INIT 0x0007ffef
-
-#define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
- MAC_CFG1_SRX | MAC_CFG1_STX | \
- MAC_CFG1_TFC | MAC_CFG1_RFC)
-#define AR91XX_FIFO_CFG5_INIT 0x0007efef
-
-#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
-
static void ag71xx_dma_reset(struct ag71xx *ag)
{
+ u32 val;
int i;
ag71xx_dump_dma_regs(ag);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
- if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
- printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
- ag->dev->name);
+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
+ if (val)
+ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
+ ag->dev->name, val);
+
+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
+
+ /* mask out reserved bits */
+ val &= ~0xff000000;
- if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
- printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
- ag->dev->name);
+ if (val)
+ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
+ ag->dev->name, val);
ag71xx_dump_dma_regs(ag);
}
+#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
+ MAC_CFG1_SRX | MAC_CFG1_STX)
+
+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+
+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
+ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
+ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
+ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
+ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
+ FIFO_CFG4_VT)
+
+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
+ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
+ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
+ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
+ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
+ FIFO_CFG5_17 | FIFO_CFG5_SF)
+
static void ag71xx_hw_init(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
mdelay(100);
/* setup MAC configuration registers */
- ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
- pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
/* setup FIFO configuration registers */
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
- pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
- : AR71XX_FIFO_CFG5_INIT);
+ if (pdata->is_ar724x) {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+ } else {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+ }
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
ag71xx_dma_reset(ag);
}
ag71xx_phy_stop(ag);
napi_disable(&ag->napi);
+ del_timer_sync(&ag->oom_timer);
spin_unlock_irqrestore(&ag->lock, flags);
static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct ag71xx *ag = netdev_priv(dev);
- struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct ag71xx_ring *ring = &ag->tx_ring;
struct ag71xx_desc *desc;
- unsigned long flags;
int i;
i = ring->curr % AG71XX_TX_RING_SIZE;
- desc = &ring->descs[i];
-
- spin_lock_irqsave(&ag->lock, flags);
- pdata->ddr_flush();
- spin_unlock_irqrestore(&ag->lock, flags);
+ desc = ring->buf[i].desc;
if (!ag71xx_desc_empty(desc))
goto err_drop;
+ ag71xx_add_ar8216_header(ag, skb);
+
if (skb->len <= 0) {
DBG("%s: packet len is too small\n", ag->dev->name);
goto err_drop;
return -EOPNOTSUPP;
}
+static void ag71xx_oom_timer_handler(unsigned long data)
+{
+ struct net_device *dev = (struct net_device *) data;
+ struct ag71xx *ag = netdev_priv(dev);
+
+ napi_schedule(&ag->napi);
+}
+
static void ag71xx_tx_timeout(struct net_device *dev)
{
struct ag71xx *ag = netdev_priv(dev);
sent = 0;
while (ring->dirty != ring->curr) {
unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
- struct ag71xx_desc *desc = &ring->descs[i];
+ struct ag71xx_desc *desc = ring->buf[i].desc;
struct sk_buff *skb = ring->buf[i].skb;
if (!ag71xx_desc_empty(desc))
while (done < limit) {
unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
- struct ag71xx_desc *desc = &ring->descs[i];
+ struct ag71xx_desc *desc = ring->buf[i].desc;
struct sk_buff *skb;
int pktlen;
skb_put(skb, pktlen);
skb->dev = dev;
- skb->protocol = eth_type_trans(skb, dev);
skb->ip_summed = CHECKSUM_NONE;
- netif_receive_skb(skb);
-
dev->last_rx = jiffies;
dev->stats.rx_packets++;
dev->stats.rx_bytes += pktlen;
+ if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
+ dev->stats.rx_dropped++;
+ kfree_skb(skb);
+ } else {
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_receive_skb(skb);
+ }
+
ring->buf[i].skb = NULL;
done++;
ring->curr++;
- if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
- ag71xx_ring_rx_refill(ag);
}
ag71xx_ring_rx_refill(ag);
struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct net_device *dev = ag->dev;
+ struct ag71xx_ring *rx_ring;
unsigned long flags;
u32 status;
int done;
DBG("%s: processing RX ring\n", dev->name);
done = ag71xx_rx_packets(ag, limit);
- /* TODO: add OOM handler */
+ rx_ring = &ag->rx_ring;
+ if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
+ goto oom;
status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
if (unlikely(status & RX_STATUS_OF)) {
DBG("%s: disable polling mode, done=%d, limit=%d\n",
dev->name, done, limit);
- netif_rx_complete(dev, napi);
+ napi_complete(napi);
/* enable interrupts */
spin_lock_irqsave(&ag->lock, flags);
DBG("%s: stay in polling mode, done=%d, limit=%d\n",
dev->name, done, limit);
return done;
+
+ oom:
+ if (netif_msg_rx_err(ag))
+ printk(KERN_DEBUG "%s: out of memory\n", dev->name);
+
+ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
+ napi_complete(napi);
+ return 0;
}
static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
if (likely(status & AG71XX_INT_POLL)) {
ag71xx_int_disable(ag, AG71XX_INT_POLL);
DBG("%s: enable polling mode\n", dev->name);
- netif_rx_schedule(dev, &ag->napi);
+ napi_schedule(&ag->napi);
}
return IRQ_HANDLED;
/* TODO */
}
+static const struct net_device_ops ag71xx_netdev_ops = {
+ .ndo_open = ag71xx_open,
+ .ndo_stop = ag71xx_stop,
+ .ndo_start_xmit = ag71xx_hard_start_xmit,
+ .ndo_set_multicast_list = ag71xx_set_multicast_list,
+ .ndo_do_ioctl = ag71xx_do_ioctl,
+ .ndo_tx_timeout = ag71xx_tx_timeout,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+};
+
static int __init ag71xx_probe(struct platform_device *pdev)
{
struct net_device *dev;
goto err_out;
}
+ if (pdata->mii_bus_dev == NULL) {
+ dev_err(&pdev->dev, "no MII bus device specified\n");
+ err = -EINVAL;
+ goto err_out;
+ }
+
dev = alloc_etherdev(sizeof(*ag));
if (!dev) {
dev_err(&pdev->dev, "alloc_etherdev failed\n");
ag = netdev_priv(dev);
ag->pdev = pdev;
ag->dev = dev;
- ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
- ag->msg_enable = netif_msg_init(ag71xx_debug,
+ ag->msg_enable = netif_msg_init(ag71xx_msg_level,
AG71XX_DEFAULT_MSG_ENABLE);
spin_lock_init(&ag->lock);
goto err_free_dev;
}
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
- if (!res) {
- dev_err(&pdev->dev, "no mac_base2 resource found\n");
- err = -ENXIO;
- goto err_unmap_base1;
- }
-
- ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
- if (!ag->mac_base) {
- dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
- err = -ENOMEM;
- goto err_unmap_base1;
- }
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
if (!res) {
dev_err(&pdev->dev, "no mii_ctrl resource found\n");
err = -ENXIO;
- goto err_unmap_base2;
+ goto err_unmap_base;
}
ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
if (!ag->mii_ctrl) {
dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
err = -ENOMEM;
- goto err_unmap_base2;
+ goto err_unmap_base;
}
dev->irq = platform_get_irq(pdev, 0);
}
dev->base_addr = (unsigned long)ag->mac_base;
- dev->open = ag71xx_open;
- dev->stop = ag71xx_stop;
- dev->hard_start_xmit = ag71xx_hard_start_xmit;
- dev->set_multicast_list = ag71xx_set_multicast_list;
- dev->do_ioctl = ag71xx_do_ioctl;
+ dev->netdev_ops = &ag71xx_netdev_ops;
dev->ethtool_ops = &ag71xx_ethtool_ops;
- dev->tx_timeout = ag71xx_tx_timeout;
INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
- netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
+ init_timer(&ag->oom_timer);
+ ag->oom_timer.data = (unsigned long) dev;
+ ag->oom_timer.function = ag71xx_oom_timer_handler;
- if (is_valid_ether_addr(pdata->mac_addr))
- memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
- else {
- dev->dev_addr[0] = 0xde;
- dev->dev_addr[1] = 0xad;
- get_random_bytes(&dev->dev_addr[2], 3);
- dev->dev_addr[5] = pdev->id & 0xff;
- }
+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
+
+ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
err = register_netdev(dev);
if (err) {
ag71xx_dump_regs(ag);
- /* Reset the mdio bus explicitly */
- if (ag->mii_bus) {
- mutex_lock(&ag->mii_bus->mdio_lock);
- ag->mii_bus->reset(ag->mii_bus);
- mutex_unlock(&ag->mii_bus->mdio_lock);
- }
-
err = ag71xx_phy_connect(ag);
if (err)
goto err_unregister_netdev;
free_irq(dev->irq, dev);
err_unmap_mii_ctrl:
iounmap(ag->mii_ctrl);
- err_unmap_base2:
- iounmap(ag->mac_base2);
- err_unmap_base1:
+ err_unmap_base:
iounmap(ag->mac_base);
err_free_dev:
kfree(dev);
unregister_netdev(dev);
free_irq(dev->irq, dev);
iounmap(ag->mii_ctrl);
- iounmap(ag->mac_base2);
iounmap(ag->mac_base);
kfree(dev);
platform_set_drvdata(pdev, NULL);
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