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add descriptions to the broadcom target profiles and export them to the target metada...
[openwrt.git] / target / linux / brcm-2.6 / patches / 003-bcm4710_cache_fixes.patch
diff --git a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
index d0487fb..d9e4dd7 100644 (file)
--- a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
+++ b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
@@ -1,6 +1,6 @@
-diff -ur linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
---- linux.old/arch/mips/kernel/genex.S 2006-10-16 19:09:36.000000000 +0200
-+++ linux.dev/arch/mips/kernel/genex.S 2006-10-16 19:06:50.000000000 +0200
+diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S
+--- linux-2.6.19.ref/arch/mips/kernel/genex.S  2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/arch/mips/kernel/genex.S      2006-12-04 21:34:09.000000000 +0100
 @@ -73,6 +73,10 @@
        .set    push
        .set    mips3
 @@ -73,6 +73,10 @@
        .set    push
        .set    mips3
@@ -12,10 +12,10 @@ diff -ur linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
        mfc0    k1, CP0_CAUSE
        li      k0, 31<<2
        andi    k1, k1, 0x7c
        mfc0    k1, CP0_CAUSE
        li      k0, 31<<2
        andi    k1, k1, 0x7c
-diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
---- linux.old/arch/mips/mm/c-r4k.c     2006-10-16 19:09:36.000000000 +0200
-+++ linux.dev/arch/mips/mm/c-r4k.c     2006-10-16 19:08:46.000000000 +0200
-@@ -14,6 +14,15 @@
+diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
+--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c      2006-12-04 21:34:04.000000000 +0100
++++ linux-2.6.19/arch/mips/mm/c-r4k.c  2006-12-04 21:34:09.000000000 +0100
+@@ -13,6 +13,15 @@
  #include <linux/mm.h>
  #include <linux/bitops.h>
  
  #include <linux/mm.h>
  #include <linux/bitops.h>
  
@@ -31,7 +31,7 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
  #include <asm/bcache.h>
  #include <asm/bootinfo.h>
  #include <asm/cache.h>
  #include <asm/bcache.h>
  #include <asm/bootinfo.h>
  #include <asm/cache.h>
-@@ -30,6 +39,9 @@
+@@ -29,6 +38,9 @@
  #include <asm/cacheflush.h> /* for run_uncached() */
  
  
  #include <asm/cacheflush.h> /* for run_uncached() */
  
  
@@ -41,40 +41,37 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
-@@ -94,7 +106,9 @@
+@@ -93,6 +105,9 @@
  {
        unsigned long  dc_lsize = cpu_dcache_line_size();
  
  {
        unsigned long  dc_lsize = cpu_dcache_line_size();
  
--      if (dc_lsize == 16)
 +      if (bcm4710)
 +              r4k_blast_dcache_page = blast_dcache_page;
 +      if (bcm4710)
 +              r4k_blast_dcache_page = blast_dcache_page;
-+      else if (dc_lsize == 16)
-               r4k_blast_dcache_page = blast_dcache16_page;
-       else if (dc_lsize == 32)
-               r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
-@@ -106,7 +120,9 @@
++      else
+       if (dc_lsize == 0)
+               r4k_blast_dcache_page = (void *)cache_noop;
+       else if (dc_lsize == 16)
+@@ -107,6 +122,9 @@
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
--      if (dc_lsize == 16)
 +      if (bcm4710)
 +              r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
 +      if (bcm4710)
 +              r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+      else if (dc_lsize == 16)
-               r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
-       else if (dc_lsize == 32)
-               r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
-@@ -118,7 +134,9 @@
++      else
+       if (dc_lsize == 0)
+               r4k_blast_dcache_page_indexed = (void *)cache_noop;
+       else if (dc_lsize == 16)
+@@ -121,6 +139,9 @@
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
  {
        unsigned long dc_lsize = cpu_dcache_line_size();
  
--      if (dc_lsize == 16)
 +      if (bcm4710)
 +              r4k_blast_dcache = blast_dcache;
 +      if (bcm4710)
 +              r4k_blast_dcache = blast_dcache;
-+      else if (dc_lsize == 16)
-               r4k_blast_dcache = blast_dcache16;
-       else if (dc_lsize == 32)
-               r4k_blast_dcache = blast_dcache32;
-@@ -527,6 +545,9 @@
++      else
+       if (dc_lsize == 0)
+               r4k_blast_dcache = (void *)cache_noop;
+       else if (dc_lsize == 16)
+@@ -538,6 +559,9 @@
                r4k_blast_icache();
        else
                protected_blast_icache_range(start, end);
                r4k_blast_icache();
        else
                protected_blast_icache_range(start, end);
@@ -84,17 +81,17 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
  }
  
  static void r4k_flush_icache_range(unsigned long start, unsigned long end)
  }
  
  static void r4k_flush_icache_range(unsigned long start, unsigned long end)
-@@ -683,6 +704,8 @@
+@@ -618,6 +642,8 @@
        unsigned long addr = (unsigned long) arg;
  
        R4600_HIT_CACHEOP_WAR_IMPL;
 +      BCM4710_PROTECTED_FILL_TLB(addr);
 +      BCM4710_PROTECTED_FILL_TLB(addr + 4);
        unsigned long addr = (unsigned long) arg;
  
        R4600_HIT_CACHEOP_WAR_IMPL;
 +      BCM4710_PROTECTED_FILL_TLB(addr);
 +      BCM4710_PROTECTED_FILL_TLB(addr + 4);
-       protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+       if (dc_lsize)
+               protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
        if (!cpu_icache_snoops_remote_store && scache_size)
        if (!cpu_icache_snoops_remote_store && scache_size)
-               protected_writeback_scache_line(addr & ~(sc_lsize - 1));
-@@ -1189,6 +1212,16 @@
- static inline void coherency_setup(void)
+@@ -1135,6 +1161,16 @@
+ static void __init coherency_setup(void)
  {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
 +#ifdef CONFIG_BCM947XX
  {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
 +#ifdef CONFIG_BCM947XX
@@ -110,7 +107,7 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
  
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
  
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
-@@ -1227,6 +1260,15 @@
+@@ -1173,6 +1209,15 @@
  
        /* Default cache error handler for R4000 and R5000 family */
        set_uncached_handler (0x100, &except_vec2_generic, 0x80);
  
        /* Default cache error handler for R4000 and R5000 family */
        set_uncached_handler (0x100, &except_vec2_generic, 0x80);
@@ -126,21 +123,21 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
  
        probe_pcache();
        setup_scache();
  
        probe_pcache();
        setup_scache();
-diff -ur linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
---- linux.old/arch/mips/mm/tlbex.c     2006-10-16 19:09:36.000000000 +0200
-+++ linux.dev/arch/mips/mm/tlbex.c     2006-10-16 19:06:50.000000000 +0200
-@@ -38,6 +38,10 @@
- 
- /* #define DEBUG_TLB */
+diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c
+--- linux-2.6.19.ref/arch/mips/mm/tlbex.c      2006-12-04 21:33:48.000000000 +0100
++++ linux-2.6.19/arch/mips/mm/tlbex.c  2006-12-04 21:34:09.000000000 +0100
+@@ -1174,6 +1174,10 @@
+ #endif
+ }
  
 +#ifdef CONFIG_BCM947XX
 +extern int bcm4710;
 +#endif
 +
  
 +#ifdef CONFIG_BCM947XX
 +extern int bcm4710;
 +#endif
 +
- static __init int __attribute__((unused)) r45k_bvahwbug(void)
+ static void __init build_r4000_tlb_refill_handler(void)
  {
  {
-       /* XXX: We should probe for the presence of this bug, but we don't. */
-@@ -1184,6 +1188,12 @@
+       u32 *p = tlb_handler;
+@@ -1188,6 +1192,12 @@
        memset(relocs, 0, sizeof(relocs));
        memset(final_handler, 0, sizeof(final_handler));
  
        memset(relocs, 0, sizeof(relocs));
        memset(final_handler, 0, sizeof(final_handler));
  
@@ -153,9 +150,9 @@ diff -ur linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
        /*
         * create the plain linear handler
         */
        /*
         * create the plain linear handler
         */
-diff -ur linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
---- linux.old/include/asm-mips/r4kcache.h      2006-10-16 19:09:36.000000000 +0200
-+++ linux.dev/include/asm-mips/r4kcache.h      2006-10-16 19:09:11.000000000 +0200
+diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h
+--- linux-2.6.19.ref/include/asm-mips/r4kcache.h       2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/include/asm-mips/r4kcache.h   2006-12-04 21:34:09.000000000 +0100
 @@ -17,6 +17,18 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
 @@ -17,6 +17,18 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
@@ -356,10 +353,10 @@ diff -ur linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcac
 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
  
  #endif /* _ASM_R4KCACHE_H */
 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
  
  #endif /* _ASM_R4KCACHE_H */
-diff -ur linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
---- linux.old/include/asm-mips/stackframe.h    2006-10-16 19:09:36.000000000 +0200
-+++ linux.dev/include/asm-mips/stackframe.h    2006-10-16 19:06:50.000000000 +0200
-@@ -361,6 +361,10 @@
+diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h
+--- linux-2.6.19.ref/include/asm-mips/stackframe.h     2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100
+@@ -334,6 +334,10 @@
                .macro  RESTORE_SP_AND_RET
                LONG_L  sp, PT_R29(sp)
                .set    mips3
                .macro  RESTORE_SP_AND_RET
                LONG_L  sp, PT_R29(sp)
                .set    mips3
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