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cleaned up amazon serial and prom code
[openwrt.git] / target / linux / amazon-2.6 / files / arch / mips / amazon / interrupt.c
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c b/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c
index 6702ecf..5e34e05 100644 (file)
--- a/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c
@@ -1,6 +1,7 @@
 /*
  *  Gary Jennejohn (C) 2003 <gj@denx.de>
  *  Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
 /*
  *  Gary Jennejohn (C) 2003 <gj@denx.de>
  *  Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -35,77 +36,64 @@
 
 static void amazon_disable_irq(unsigned int irq_nr)
 {
 
 static void amazon_disable_irq(unsigned int irq_nr)
 {
-       /* have to access the correct register here */
+       int i;
+       u32 amazon_ier = AMAZON_ICU_IM0_IER;
+
        if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
        if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
-               /* access IM0 DMA channels */
-               *AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK));
-       else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
-               /* access IM0 except DMA*/
-               *AMAZON_ICU_IM0_IER &= (~AMAZON_ICU_IM0_IER_IR(irq_nr));
-       else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
-               /* access IM1 */
-               *AMAZON_ICU_IM1_IER &= (~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0));
-       else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
-               /* access IM2 */
-               *AMAZON_ICU_IM2_IER &= (~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0));
-       else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
-               /* access IM3 */
-               *AMAZON_ICU_IM3_IER &= (~AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0)));
-       else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
-               /* access IM4 */
-               *AMAZON_ICU_IM4_IER &= (~AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0)));
+               amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
+       else {
+               irq_nr -= INT_NUM_IRQ0;
+               for (i = 0; i <= 4; i++)
+               {
+                       if (irq_nr <= 31) 
+                       amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier);
+                       amazon_ier += 0x10;
+                       irq_nr -= 32;
+               }
+       }       
 }
 
 static void amazon_mask_and_ack_irq(unsigned int irq_nr)
 {
 }
 
 static void amazon_mask_and_ack_irq(unsigned int irq_nr)
 {
-       /* have to access the correct register here */
-       if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) {
-               /* access IM0 DMA channels */
-               *AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK)); /* mask */
-               *AMAZON_ICU_IM0_ISR = AMAZON_DMA_H_MASK; /* ack */
-       } else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12) {
-               /* access IM0 except DMA */
-               *AMAZON_ICU_IM0_IER &= ~AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0); /* mask */
-               *AMAZON_ICU_IM0_ISR = AMAZON_ICU_IM0_ISR_IR(irq_nr - INT_NUM_IM0_IRL0); /* ack */
-       } else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0) {
-               /* access IM1 */
-               *AMAZON_ICU_IM1_IER &= ~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0); /* mask */
-               *AMAZON_ICU_IM1_ISR = AMAZON_ICU_IM1_ISR_IR(irq_nr - INT_NUM_IM1_IRL0); /* ack */
-       } else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0) {
-               /* access IM2 */
-               *AMAZON_ICU_IM2_IER &= ~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0); /* mask */
-               *AMAZON_ICU_IM2_ISR = AMAZON_ICU_IM2_ISR_IR(irq_nr - INT_NUM_IM2_IRL0); /* ack */
-       } else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0) {
-               /* access IM3 */
-               *AMAZON_ICU_IM3_IER &= ~AMAZON_ICU_IM3_IER_IR(irq_nr - INT_NUM_IM3_IRL0); /* mask */
-               *AMAZON_ICU_IM3_ISR = AMAZON_ICU_IM3_ISR_IR(irq_nr - INT_NUM_IM3_IRL0); /* ack */
-       } else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0) {
-               *AMAZON_ICU_IM4_IER &= ~AMAZON_ICU_IM4_IER_IR(irq_nr - INT_NUM_IM4_IRL0); /* mask */
-               *AMAZON_ICU_IM4_ISR = AMAZON_ICU_IM4_ISR_IR(irq_nr - INT_NUM_IM4_IRL0); /* ack */
+       int i;
+       u32 amazon_ier = AMAZON_ICU_IM0_IER;
+       u32 amazon_isr = AMAZON_ICU_IM0_ISR;
+
+       if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0){
+               amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
+               amazon_writel(AMAZON_DMA_H_MASK, amazon_isr); 
+       } else {
+               irq_nr -= INT_NUM_IRQ0;
+               for (i = 0; i <= 4; i++)
+               {
+                       if (irq_nr <= 31){ 
+                       amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier);
+                               amazon_writel((1 << irq_nr ), amazon_isr);
+                       }
+                       amazon_ier += 0x10;
+                       amazon_isr += 0x10;
+                       irq_nr -= 32;
+               }
        }
 }
 
 static void amazon_enable_irq(unsigned int irq_nr)
 {
        }
 }
 
 static void amazon_enable_irq(unsigned int irq_nr)
 {
-       /* have to access the correct register here */
+       int i;
+       u32 amazon_ier = AMAZON_ICU_IM0_IER;
+
        if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
        if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
-               /* access IM0 DMA*/
-               *AMAZON_ICU_IM0_IER |= AMAZON_DMA_H_MASK;
-       else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
-               /* access IM0 except DMA*/
-               *AMAZON_ICU_IM0_IER |= AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0);
-       else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
-               /* access IM1 */
-               *AMAZON_ICU_IM1_IER |= AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0);
-       else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
-               /* access IM2 */
-               *AMAZON_ICU_IM2_IER |= AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0);
-       else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
-               /* access IM3 */
-               *AMAZON_ICU_IM3_IER |= AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0));
-       else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
-               /* access IM4 */
-               *AMAZON_ICU_IM4_IER |= AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0));
+               amazon_writel(amazon_readl(amazon_ier) | AMAZON_DMA_H_MASK, amazon_ier);
+       else {
+               irq_nr -= INT_NUM_IRQ0;
+               for (i = 0; i <= 4; i++)
+               {
+                       if (irq_nr <= 31)
+                               amazon_writel(amazon_readl(amazon_ier) | (1 << irq_nr ), amazon_ier);
+                       amazon_ier += 0x10;
+                       irq_nr -= 32;
+               }
+       }
 }
 
 static unsigned int amazon_startup_irq(unsigned int irq)
 }
 
 static unsigned int amazon_startup_irq(unsigned int irq)
@@ -133,53 +121,17 @@ static struct hw_interrupt_type amazon_irq_type = {
        .end = amazon_end_irq
 };
 
        .end = amazon_end_irq
 };
 
-/* Cascaded interrupts from IM0 */
-static inline void amazon_hw0_irqdispatch(void)
+/* Cascaded interrupts from IM0-4 */
+static inline void amazon_hw_irqdispatch(u8 line)
 {
        u32 irq;
 {
        u32 irq;
-                                                                                                                                                                                                
-       irq = (*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM0_VEC_MASK;
-       if (irq <= 11 && irq >= 0) {
+
+       irq = (amazon_readl(AMAZON_ICU_IM_VEC) >> (line * 5)) & AMAZON_ICU_IM0_VEC_MASK;
+       if (line == 0 && irq <= 11 && irq >= 0) {
                //DMA fixed to IM0_IRL0
                irq = 0;
        }
                //DMA fixed to IM0_IRL0
                irq = 0;
        }
-       do_IRQ(irq + INT_NUM_IM0_IRL0);
-}
-                                                                                                         
-/* Cascaded interrupts from IM1 */
-static inline void amazon_hw1_irqdispatch(void)
-{
-       u32 irq;
-
-       irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM1_VEC_MASK) >> 5;
-       do_IRQ(irq + INT_NUM_IM1_IRL0);
-}
-
-/* Cascaded interrupts from IM2 */
-static inline void amazon_hw2_irqdispatch(void)
-{
-       u32 irq;
-                                                                                                                                                                                                
-       irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM2_VEC_MASK) >> 10;
-       do_IRQ(irq + INT_NUM_IM2_IRL0);
-}
-
-/* Cascaded interrupts from IM3 */
-static inline void amazon_hw3_irqdispatch(void)
-{
-       u32 irq;
-
-       irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM3_VEC_MASK) >> 15;
-       do_IRQ(irq + INT_NUM_IM3_IRL0);
-}
-
-/* Cascaded interrupts from IM4 */
-static inline void amazon_hw4_irqdispatch(void)
-{
-       u32 irq;
-
-       irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM4_VEC_MASK) >> 20;
-       do_IRQ(irq + INT_NUM_IM4_IRL0);
+       do_IRQ(irq + INT_NUM_IRQ0 + (line * 32));
 }
 
 asmlinkage void plat_irq_dispatch(void)
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -187,19 +139,20 @@ asmlinkage void plat_irq_dispatch(void)
        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & CAUSEF_IP7){
                do_IRQ(MIPS_CPU_TIMER_IRQ);
        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & CAUSEF_IP7){
                do_IRQ(MIPS_CPU_TIMER_IRQ);
+               goto out;
+       } else {
+               unsigned int i;
+               for (i = 0; i <= 4; i++)
+               {
+                       if(pending & (CAUSEF_IP2 << i)){
+                               amazon_hw_irqdispatch(i);
+                               goto out;
+                       }
+               }
        }
        }
-       else if (pending & CAUSEF_IP2)
-               amazon_hw0_irqdispatch();
-       else if (pending & CAUSEF_IP3)
-               amazon_hw1_irqdispatch();
-       else if (pending & CAUSEF_IP4)
-               amazon_hw2_irqdispatch();
-       else if (pending & CAUSEF_IP5)
-               amazon_hw3_irqdispatch();
-       else if (pending & CAUSEF_IP6)
-               amazon_hw4_irqdispatch();
-       else
-               printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+       printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+out:
+       return;
 }
 
 static struct irqaction cascade = {
 }
 
 static struct irqaction cascade = {
@@ -208,19 +161,14 @@ static struct irqaction cascade = {
        .name           = "cascade",
 };
 
        .name           = "cascade",
 };
 
-
-/* Function for careful CP0 interrupt mask access */
-
 void __init arch_init_irq(void)
 {
        int i;
 
        /* mask all interrupt sources */
 void __init arch_init_irq(void)
 {
        int i;
 
        /* mask all interrupt sources */
-       *AMAZON_ICU_IM0_IER = 0;
-       *AMAZON_ICU_IM1_IER = 0;
-       *AMAZON_ICU_IM2_IER = 0;
-       *AMAZON_ICU_IM3_IER = 0;
-       *AMAZON_ICU_IM4_IER = 0;
+       for(i = 0; i <= 4; i++){
+               amazon_writel(0, AMAZON_ICU_IM0_IER + (i * 0x10));
+       }
 
        mips_cpu_irq_init();
 
 
        mips_cpu_irq_init();
 
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