+++ /dev/null
-diff -NurbwB linux-2.6.17/arch/arm/mach-pxa/pm.c linux-2.6.17-patched/arch/arm/mach-pxa/pm.c
---- linux-2.6.17/arch/arm/mach-pxa/pm.c 2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17-patched/arch/arm/mach-pxa/pm.c 2006-09-11 10:58:41.000000000 -0700
-@@ -10,35 +10,50 @@
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- */
-+
- #include <linux/config.h>
- #include <linux/init.h>
--#include <linux/module.h>
--#include <linux/suspend.h>
-+#include <linux/pm.h>
-+#include <linux/slab.h>
-+#include <linux/sched.h>
-+#include <linux/interrupt.h>
-+#include <linux/sysctl.h>
- #include <linux/errno.h>
--#include <linux/time.h>
-
- #include <asm/hardware.h>
- #include <asm/memory.h>
- #include <asm/system.h>
--#include <asm/arch/pm.h>
-+#include <asm/leds.h>
-+#include <asm/uaccess.h>
- #include <asm/arch/pxa-regs.h>
- #include <asm/arch/lubbock.h>
- #include <asm/mach/time.h>
-
-+/**/
-+#include <linux/module.h>
-+/**/
-+//kirti
-+#include <linux/delay.h>
-+//kirti~
-
- /*
- * Debug macros
- */
--#undef DEBUG
-+#define DEBUG
-+
-+extern void pxa_cpu_suspend(void);
-+extern void pxa_cpu_resume(void);
-+
-+int pm_pwronoff;
-+/*Angelia Additions */
-+int pm_pedr=0;
-+EXPORT_SYMBOL(pm_pwronoff);
-+EXPORT_SYMBOL(pm_pedr);
-+
-
- #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
- #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
-
--#define RESTORE_GPLEVEL(n) do { \
-- GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
-- GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
--} while (0)
--
- /*
- * List of global PXA peripheral registers to preserve.
- * More ones like CP and general purpose register values are preserved
-@@ -46,97 +61,405 @@
- */
- enum { SLEEP_SAVE_START = 0,
-
-- SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
-- SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
-- SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
-- SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
-- SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
--
-- SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
-- SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
-- SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
-- SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
-+ SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
-+ SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
-
-- SLEEP_SAVE_PSTR,
-+ SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
-+ SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
-+ SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
-+ SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
-+ SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
-+
-+ SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
-+ SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
-+ SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,SLEEP_SAVE_FFFCR,
-+
-+ SLEEP_SAVE_STIER, SLEEP_SAVE_STLCR, SLEEP_SAVE_STMCR,
-+ SLEEP_SAVE_STSPR, SLEEP_SAVE_STISR,
-+ SLEEP_SAVE_STDLL, SLEEP_SAVE_STDLH,
-+
-+ SLEEP_SAVE_BTIER, SLEEP_SAVE_BTLCR, SLEEP_SAVE_BTMCR,
-+ SLEEP_SAVE_BTSPR, SLEEP_SAVE_BTISR,
-+ SLEEP_SAVE_BTDLL, SLEEP_SAVE_BTDLH,
-
- SLEEP_SAVE_ICMR,
- SLEEP_SAVE_CKEN,
-
--#ifdef CONFIG_PXA27x
-- SLEEP_SAVE_MDREFR,
-- SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
-- SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
--#endif
-+ SLEEP_SAVE_LCCR0, SLEEP_SAVE_LCCR1, SLEEP_SAVE_LCCR2,SLEEP_SAVE_LCCR3,
-+ SLEEP_SAVE_TMEDCR, SLEEP_SAVE_FDADR0, SLEEP_SAVE_FSADR0,SLEEP_SAVE_FIDR0,SLEEP_SAVE_FDADR1,
-+ SLEEP_SAVE_LDCMD0,
-+
-+ SLEEP_SAVE_NSSCR0,SLEEP_SAVE_NSSCR1,SLEEP_SAVE_NSSSR,SLEEP_SAVE_NSSITR,SLEEP_SAVE_NSSDR,
-+ SLEEP_SAVE_NSSTO,SLEEP_SAVE_NSSPSP,
-
-- SLEEP_SAVE_CKSUM,
-
-+ SLEEP_SAVE_CKSUM,
- SLEEP_SAVE_SIZE
- };
-
-+/**/
-+#define UART_DTR 1
-+#define UART_RTS 2
-+
-+/**/
-
--int pxa_pm_enter(suspend_state_t state)
-+int pm_do_suspend(void)
- {
- unsigned long sleep_save[SLEEP_SAVE_SIZE];
- unsigned long checksum = 0;
-- struct timespec delta, rtc;
- int i;
-+ int valbefore,valafter,valafter1;
-+ int gpsr0,gpsr1,gpsr2;
- extern void pxa_cpu_pm_enter(suspend_state_t state);
-
--#ifdef CONFIG_IWMMXT
-- /* force any iWMMXt context to ram **/
-- iwmmxt_task_disable(NULL);
--#endif
-+ // YoKu 16Feb06 GPIO Changed ----->
-+
-+ PGSR2 |= GPIO_bit(78);
-+/* if(GPLR2 & GPIO_bit(78)) // LCD Reset Pin
-+ PGSR2 |= GPIO_bit(78);
-+ else
-+ PGSR2 &= ~GPIO_bit(78); */
-+ GPDR0 &= ~GPIO_bit(0);
-+ GPDR0 &= ~GPIO_bit(1);
-+ GPDR0 &= ~GPIO_bit(3); //Tushar: 20 apr GPIO3 configured as input
-+ GPDR0 &= ~GPIO_bit(2);
-+// GPDR0 &= ~GPIO_bit(5);
-+// GPDR0 &= ~GPIO_bit(6);
-+// GPDR0 &= ~GPIO_bit(7);
-+// GPDR0 &= ~GPIO_bit(8);
-+
-+
-+// KeyCol pin Status in sleep mode
-+ PGSR0 &= ~GPIO_bit(9); //19
-+ PGSR0 &= ~GPIO_bit(10); //20
-+ PGSR0 &= ~GPIO_bit(11); //21
-+ PGSR0 &= ~GPIO_bit(12); //22
-+ PGSR0 &= ~GPIO_bit(13); //23
-+ PGSR0 &= ~GPIO_bit(14); //24
-+
-+ printk("KER_PM: Setting up wakeup sources 26May06\n");
-+
-+ // KeyPad
-+ //printk("KER_PM: Uncommented key pad wakeup sources\n");
-+ PWER |= GPIO_bit(5); //11
-+ PWER |= GPIO_bit(6); //12
-+ PWER |= GPIO_bit(7); //13
-+ PWER |= GPIO_bit(8); //14
-+ PFER |= GPIO_bit(5); //11
-+ PFER |= GPIO_bit(6); //12
-+ PFER |= GPIO_bit(7); //13
-+ PFER |= GPIO_bit(8); //14
-+ PRER |= GPIO_bit(5); //11
-+ PRER |= GPIO_bit(6); //12
-+ PRER |= GPIO_bit(7); //13
-+ PRER |= GPIO_bit(8); //14
-+
-+ // USB
-+ PWER |= GPIO_bit(3); //6
-+ PFER |= GPIO_bit(3); //6
-+ PRER |= GPIO_bit(3); //6
-+
-+ // PMU
-+ PWER |= GPIO_bit(2); //4
-+ PFER |= GPIO_bit(2); //4
-+ PRER |= GPIO_bit(2); //4
-+
-+ // Anup : GSM RI
-+ PWER |= GPIO_bit(0); //0
-+ PFER |= GPIO_bit(0); //0
-+ PRER |= GPIO_bit(0); //0
-+ // anup prashant : for gsm reset problem 19 may 2006
-+ //GPDR0 |= GPIO_bit(18); YoKu Commented this line, GPIO18 should be i/p pin to avoid GSM Reset pulse
-+ PGSR0 |= GPIO_bit(18); // GSM reset pin
-+ PGSR0 |= GPIO_bit(0); //
-+ PGSR1 |= GPIO_bit(38); // commneted .18 apr
-+ // <----- YoKu
-+
-+ // YoKu ----->
-+ // When exiting from sleep mode, 10us Low pulse comes on GSM Reset and Pwr pin
-+ // to avoid this configure GPIO 18,80 as input pins before going to sleep mode
-+ GPDR0 &= ~GPIO_bit(18);
-+ //GPDR2 &= ~GPIO_bit(80);
-+ // <----- YoKu
-+
-+ //kirti for RTC
-+ PWER |= PWER_RTC;
-+ //kirti cli();
-+ local_irq_disable();
-+ //kirti clf();
-+ local_fiq_disable();
-+ leds_event(led_stop);
-+
-+ /* Put Current time into RCNR */
-+ RCNR = xtime.tv_sec;
-
-- /* preserve current time */
-- rtc.tv_sec = RCNR;
-- rtc.tv_nsec = 0;
-- save_time_delta(&delta, &rtc);
-+ printk("11May2006 KERR: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2);
-+ printk("KER_PM_DELAY: SSCR Going to Sleep at RCNR =%d\n\n\n\n\n\n",RCNR);
-+
-+ /*
-+ * Temporary solution. This won't be necessary once
-+ * we move pxa support into the serial driver
-+ * Save the FF UART
-+ */
-+
-+ // Anup : commented for power saving mode problem
-+ printk("\nPM: Why doesnt it prnt?? 26May06\n");
-+ printk("\nPM : GSM Sleep Mode enabled");
-+
-+
-+ FFMCR &= ~UART_RTS;
-+ udelay(2000);
-+ udelay(2000);
-+ FFMCR &= ~UART_DTR ;
-+ udelay(2000);
-+
-+ udelay(2000);
-+ // rupali
-+ // Anup : Do not check here
-+/* if(!pm_pwronoff)
-+ {
-+ printk("\nPM : Modem Control Register = %x " , FFMCR);
-+ while( FFMSR & 0x00000020)
-+ {
-+ printk("\nPM : FFFSR = %x " , FFMSR);
-+ }
-+ } */
-+ udelay(2000);
-+
-+//Tushar: 19 apr
-+// NSSCR0 &= 0xFFFFFF7F;
-+// printk("\nPM: NSSCR0 = %x" ,NSSCR0 );
-+
-+ SAVE(FFIER);
-+ SAVE(FFLCR);
-+ SAVE(FFMCR);
-+ SAVE(FFSPR);
-+ SAVE(FFISR);
-+ FFLCR |= 0x80;
-+ SAVE(FFDLL);
-+ SAVE(FFDLH);
-+ SAVE(FFFCR);
-+ FFLCR &= 0xef;
-+
-+ SAVE(STIER);
-+ SAVE(STLCR);
-+ SAVE(STMCR);
-+ SAVE(STSPR);
-+ SAVE(STISR);
-+ STLCR |= 0x80;
-+ SAVE(STDLL);
-+ SAVE(STDLH);
-+ STLCR &= 0xef;
-+
-+ SAVE(BTIER);
-+ SAVE(BTLCR);
-+ SAVE(BTMCR);
-+ SAVE(BTSPR);
-+ SAVE(BTISR);
-+ BTLCR |= 0x80;
-+ SAVE(BTDLL);
-+ SAVE(BTDLH);
-+ BTLCR &= 0xef;
-+
-+ /* save vital registers */
-+ SAVE(OSCR);
-+ SAVE(OSMR0);
-+ SAVE(OSMR1);
-+ SAVE(OSMR2);
-+ SAVE(OSMR3);
-+ SAVE(OIER);
-
-- SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
- SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
- SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
- SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
-- SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
--
- SAVE(GAFR0_L); SAVE(GAFR0_U);
- SAVE(GAFR1_L); SAVE(GAFR1_U);
- SAVE(GAFR2_L); SAVE(GAFR2_U);
-
--#ifdef CONFIG_PXA27x
-- SAVE(MDREFR);
-- SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
-- SAVE(GAFR3_L); SAVE(GAFR3_U);
-- SAVE(PWER); SAVE(PCFR); SAVE(PRER);
-- SAVE(PFER); SAVE(PKWR);
--#endif
-+ // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 ----->
-+ SAVE(LCCR0); SAVE(LCCR1); SAVE(LCCR2); SAVE(LCCR3);
-+ SAVE(FDADR0);
-+ SAVE(FDADR1);
-+ LCSR = 0xffffffff; /* Clear LCD Status Register */
-+
-+// LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
-+// LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
-+
-+ SAVE(LDCMD0);
-+ // <----- YoKu
-+
-+// LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
-+// LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
-+
-
- SAVE(ICMR);
- ICMR = 0;
-
- SAVE(CKEN);
-- SAVE(PSTR);
-+ CKEN = 0;
-+
-+ // Anup : For Wifi power saving mode 2 May 2006
-+ SAVE(NSSCR0);SAVE(NSSCR1);SAVE(NSSSR);SAVE(NSSITR);SAVE(NSSDR);SAVE(NSSTO);
-+ SAVE(NSSPSP);
-+ printk("\nMY favourite mode in life.......sleep.....\n");
-+
-
- /* Note: wake up source are set up in each machine specific files */
-
-+ /*Changes to keep the right sim selected */
-+ gpsr0 = GPLR0;
-+ gpsr1 = GPLR1;
-+ gpsr2 = GPLR2;
-+
-+ /*Sim 1 selected */
-+ // YoKu GPIOs Changed ----->
-+ if( (GPLR0 & GPIO_bit(21)) && !(GPLR0 & GPIO_bit(22)) ) // 62,63
-+ {
-+ PGSR0 |= GPIO_bit(21) ; //62
-+ PGSR0 &= ~GPIO_bit(22) ; //63
-+ }
-+ else if (!(GPLR0 & GPIO_bit(21)) && (GPLR0 & GPIO_bit(22)) ) // 62,63
-+ {
-+ PGSR0 |= GPIO_bit(22) ; //63
-+ PGSR0 &= ~GPIO_bit(21) ; //62
-+ } /* sim 2*/
-+ // <----- YoKu
-+
- /* clear GPIO transition detect bits */
- GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
--#ifdef CONFIG_PXA27x
-- GEDR3 = GEDR3;
--#endif
-
- /* Clear sleep reset status */
- RCSR = RCSR_SMR;
-
-+ /* set resume return address */
-+ PSPR = virt_to_phys(pxa_cpu_resume);
-+
- /* before sleeping, calculate and save a checksum */
- for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
- checksum += sleep_save[i];
- sleep_save[SLEEP_SAVE_CKSUM] = checksum;
-
-- /* *** go zzz *** */
-- pxa_cpu_pm_enter(state);
-+ PGSR0 |= GPIO_bit(15); //sidd for wake from Sleep 15, YoKu Comented ?? GPIO15 was ChipSelect
-+ PGSR2 |= GPIO_bit(80); //sidd for GSM Engine 69, YoKu GPIO Changed Anup :commented
-+
-+ PGSR1 &= ~GPIO_bit(33); //Tushar: BT Codec Power Down
-+
-+ PGSR0 &= ~GPIO_bit(23); //Tushar: BGW200 Regulator OFF
-+
-+// GPDR1 |= GPIO_bit(49); //Tushar: LCD Serial Data in changed to O/P
-+
-+// PGSR1 &= ~GPIO_bit(48);//Tushar: LCD Serial Pins
-+
-+// PGSR1 &= ~GPIO_bit(49);
-+
-+// PGSR1 &= ~GPIO_bit(50);
-+
-+// PGSR1 |= GPIO_bit(51);
-+
-+// PGSR1 &= 0x03FFFFFF;//Tushar: 24apr LCD datalines
-+// PGSR2 &= 0xFFFFFC00;
-+
-+ PGSR0 &= ~GPIO_bit(24); //Tushar: Mux Control Signals
-+
-+ PGSR0 &= ~GPIO_bit(25);
-+
-+ PGSR0 &= ~GPIO_bit(26);
-+
-+ PGSR0 &= ~GPIO_bit(27);
-+
-+ // GPDR0 |= GPIO_bit(17); //Tushar: unused GPIOs 19apr
-+ // GPCR0 |= GPIO_bit(17);
-+ PGSR0 &= ~GPIO_bit(17);
-+
-+// GPDR1 |= GPIO_bit(56); //Tushar: unused GPIOs 19apr
-+ // GPCR1 |= GPIO_bit(56);
-+ PGSR1 &= ~GPIO_bit(56);
-+
-+// GPDR2 |= GPIO_bit(79);//Tushar: unused GPIOs 19apr
-+// GPCR2 |= GPIO_bit(79);
-+ PGSR2 &= ~GPIO_bit(79);
-+
-+// GPDR1 |= 0x03F00000;//Tushar: unused GPIOs 19apr
-+// GPCR1 |= 0x03F00000;
-+ PGSR1 &= 0xFC0FFFFF;
-+
-+
-+ GPDR0 |= GPIO_bit(19);//Tushar: SIM Present Inputs configured as outputs
-+ GPDR0 |= GPIO_bit(20);
-+ PGSR0 &= ~GPIO_bit(19);
-+ PGSR0 &= ~GPIO_bit(20);
-+
-+
-+//Tushar: 25apr FFRTS FFDTR & FFTXD
-+
-+ PGSR1 |= GPIO_bit(39);
-+ PGSR1 |= GPIO_bit(40);
-+ PGSR1 |= GPIO_bit(41);
-+/*
-+ PGSR2 &= GPIO_bit(81); //Tushar: 24apr NSSP pins
-+ PGSR2 &= GPIO_bit(82);
-+ PGSR2 &= GPIO_bit(83);
-+
-+ PGSR2 |= GPIO_bit(74);
-+ PGSR2 |= GPIO_bit(75);
-+ PGSR2 |= GPIO_bit(76);
-+ PGSR2 |= GPIO_bit(77);
-+*/
-+ if(pm_pwronoff)
-+ {
-+ /* We are here bcos of pressing of on off switch
-+ We wake up now only on pwr switch */
-+ printk("Anup: Before sleeping \n");
-+ pm_pwronoff = 0;
-+ PGSR0 &= ~GPIO_bit(23); //7 YoKu GPIO Changed
-+ //PGSR2 &= ~GPIO_bit(64); //64 YoKu Commented in PWG500 64,7 was WifiReg, IN PWG600 it is 23
-+
-+ PGSR2 &= ~GPIO_bit(80); //69 YoKu GPIO Changed Anup : commnented
-+ PWER = 0x0004; // YoKu Changed from 0x10 to 0x04 (i.e GPIO 4 -> 2)
-+ PFER = 0x0004;
-+ PRER = 0x0004;
-+
-+// YoKu ---->
-+// 11May2006 To reduce Power Off current from 7mA to 4mA
-+ GPDR0 |= GPIO_bit(16); // BTReset o/p Low
-+ PGSR0 &= ~GPIO_bit(16);
-+
-+ GPDR1 |= GPIO_bit(33); // nMEC/nPDI o/p Low
-+ PGSR1 &= ~GPIO_bit(33);
-+
-+ GPDR1 |= GPIO_bit(45); // BTRTS o/p High
-+ PGSR1 |= GPIO_bit(45);
-+
-+
-+ GPDR1 |= GPIO_bit(43); // BTTXD o/p High
-+ PGSR1 |= GPIO_bit(43);
-+
-+ GPDR1 &= ~GPIO_bit(42); // BTRXD i/p
-+ GPDR1 &= ~GPIO_bit(44); // BTCTS i/p
-+// <---- YoKu
-+
-+ PSPR = virt_to_phys(pxa_cpu_resume); // YoKu 29July05 to Resume from where u left, Original PSPR = 0
-+ }
-+
-+ valbefore = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; // 62,63 YoKu GPIO Changed
-+
-+ //printk("Anup: Before sleeping gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2);
-+ //kirti pxa_cpu_suspend();
-+ //printk("KER_PM: Going to sleep zzzzzzzzz\n");
-+
-+// OSCC |= OSCC_OON; //Tushar: 18 apr. enable 32.768KHz Oscillator
-+
-+// PCFR |= PCFR_OPDE; //Tushar: 18 apr. disable 3.6864MHz oscillator
-+
-+ pxa_cpu_pm_enter(PM_SUSPEND_MEM);
-
- cpu_init();
-
-+ //kirti~
-+ /**/
-+ //FFMCR |= UART_DTR ;
-+ /**/
-+
- /* after sleeping, validate the checksum */
- checksum = 0;
- for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
-@@ -141,39 +464,63 @@
- checksum = 0;
- for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
- checksum += sleep_save[i];
--
- /* if invalid, display message and wait for a hardware reset */
-- if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
-+ if (checksum != sleep_save[SLEEP_SAVE_CKSUM])
-+ {
- #ifdef CONFIG_ARCH_LUBBOCK
- LUB_HEXLED = 0xbadbadc5;
- #endif
- while (1)
-- pxa_cpu_pm_enter(state);
-+ {
-+ printk("\n\n\nKERN_PM: CRC Error!!! after wakeup\n\n\n"); // YoKu 25May06
-+
- }
-
-+ }
-+ valafter = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; //62,63 YoKu GPIO Changed
-+ pm_pedr = PEDR ;
-+
- /* ensure not to come back here if it wasn't intended */
- PSPR = 0;
-
-+ /*printk("YoKu: gafr0_L=0x%08x gafr0_U=0x%08x\n",GAFR0_L,GAFR0_U);
-+ printk(" gafr1_L= 0x%08x gafr1_U= 0x%08x\n",GAFR1_L,GAFR1_U);
-+ printk(" gafr2_L= 0x%08x gafr2_U= 0x%08x\n",GAFR2_L,GAFR2_U); */
- /* restore registers */
-- RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
- RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
-+ RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
-+ RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
- RESTORE(GAFR0_L); RESTORE(GAFR0_U);
- RESTORE(GAFR1_L); RESTORE(GAFR1_U);
- RESTORE(GAFR2_L); RESTORE(GAFR2_U);
-- RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
-- RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
-- RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
-
--#ifdef CONFIG_PXA27x
-- RESTORE(MDREFR);
-- RESTORE_GPLEVEL(3); RESTORE(GPDR3);
-- RESTORE(GAFR3_L); RESTORE(GAFR3_U);
-- RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
-- RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
-- RESTORE(PFER); RESTORE(PKWR);
--#endif
-
-- PSSR = PSSR_RDH | PSSR_PH;
-+ // Anup : For Wifi power saving mode 2 May 2006
-+ RESTORE(NSSCR0);RESTORE(NSSCR1);RESTORE(NSSSR);RESTORE(NSSITR);RESTORE(NSSDR);RESTORE(NSSTO);
-+ RESTORE(NSSPSP);
-+
-+ // PSSR = PSSR_PH;
-+ GPSR0 = gpsr0;
-+ GPSR1 = gpsr1;
-+ GPSR2 = gpsr2;
-+
-+ // Anup : check values of these registers
-+// printk("YoKu: gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2);
-+ //sidd
-+
-+ GPCR0 |= ~gpsr0;
-+ GPCR1 |= ~gpsr1;
-+ GPCR2 |= ~gpsr2;
-+
-+
-+ PSSR = ~PSSR_PH;
-+
-+ RESTORE(OSMR0);
-+ RESTORE(OSMR1);
-+ RESTORE(OSMR2);
-+ RESTORE(OSMR3);
-+ RESTORE(OSCR);
-+ RESTORE(OIER);
-
- RESTORE(CKEN);
-
-@@ -181,62 +528,181 @@
- ICCR = 1;
- RESTORE(ICMR);
-
-- RESTORE(PSTR);
-+ /*
-+ * Temporary solution. This won't be necessary once
-+ * we move pxa support into the serial driver.
-+ * Restore the FF UART.
-+ */
-+ RESTORE(BTMCR);
-+ RESTORE(BTSPR);
-+ RESTORE(BTLCR);
-+ BTLCR |= 0x80;
-+ RESTORE(BTDLH);
-+ RESTORE(BTDLL);
-+ RESTORE(BTLCR);
-+ RESTORE(BTISR);
-+ BTFCR = 0xc7;
-+ RESTORE(BTIER);
-+
-+ RESTORE(STMCR);
-+ RESTORE(STSPR);
-+ RESTORE(STLCR);
-+ STLCR |= 0x80;
-+ RESTORE(STDLH);
-+ RESTORE(STDLL);
-+ RESTORE(STLCR);
-+ RESTORE(STISR);
-+ STFCR = 0xc7;
-+ RESTORE(STIER);
-+
-+ RESTORE(FFMCR);
-+ RESTORE(FFSPR);
-+ RESTORE(FFLCR);
-+ FFLCR |= 0x80;
-+ RESTORE(FFDLH);
-+ RESTORE(FFDLL);
-+ RESTORE(FFLCR);
-+ RESTORE(FFISR);
-+ RESTORE(FFFCR);
-+ FFFCR = 0xc7;
-+ RESTORE(FFIER);
-+
-+ // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 ----->
-+ RESTORE(LCCR3); RESTORE(LCCR2); RESTORE(LCCR1);
-+ LCCR0=RESTORE(LCCR0) & ~LCCR0_ENB;
-+ RESTORE(FDADR0); RESTORE(FDADR1);
-+ LCCR0 |= LCCR0_ENB;
-+
-+ // <----- YoKu
-
- /* restore current time */
-- rtc.tv_sec = RCNR;
-- restore_time_delta(&delta, &rtc);
-+ xtime.tv_sec = RCNR;
-+
-+ valafter1 = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; //62,63 YoKu GPIO Changed
-+
-+// SSCR0 &=0xFFFFFFFF;
-+// printk("\nPM : val of SSCR0 = %x " , SSCR0);
-+
-+ printk("KER_PM: Resumed at RCNR = %d RTSR= %x\n",RCNR,RTSR);
-+
-+ printk("YoKu: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2);
-+
-+ OSMR0 = 0; /* set initial match at 0 */
-+ OSSR = 0xf; /* clear status on all timers */
-+ OIER |= OIER_E0; /* enable match on timer 0 to cause interrupts */
-+ OSCR = 0; /* initialize free-running timer, force first match */
-+
-+ leds_event(led_start);
-+ //kirti sti();
-+ // call i2c reset here---->
-+ ICR = ICR_UR;
-+ ISR = 0x7FF; //I2C_ISR_INIT;
-+ ICR &= ~ICR_UR;
-+
-+ ISAR = 0x32;//i2c->slave_addr;
-+
-+ /* set control register values */
-+ ICR = (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE);//I2C_ICR_INIT;
-+
-+ /* enable unit */
-+ ICR |= ICR_IUE;
-+ udelay(100);
-+ //<-----
-+
-+ local_irq_enable();
-
--#ifdef DEBUG
-- printk(KERN_DEBUG "*** made it back from resume\n");
--#endif
-
- return 0;
- }
-
--EXPORT_SYMBOL_GPL(pxa_pm_enter);
--
- unsigned long sleep_phys_sp(void *sp)
- {
- return virt_to_phys(sp);
- }
-
-+#ifdef CONFIG_SYSCTL
- /*
-- * Called after processes are frozen, but before we shut down devices.
-+ * ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than
-+ * linux/sysctl.h.
-+ *
-+ * This means our interface here won't survive long - it needs a new
-+ * interface. Quick hack to get this working - use sysctl id 9999.
- */
--int pxa_pm_prepare(suspend_state_t state)
--{
-- extern int pxa_cpu_pm_prepare(suspend_state_t state);
-+#warning ACPI broke the kernel, this interface needs to be fixed up.
-+#define CTL_ACPI 9999
-+#define ACPI_S1_SLP_TYP 19
-
-- return pxa_cpu_pm_prepare(state);
-+/*
-+ * Send us to sleep.
-+ */
-+static int sysctl_pm_do_suspend(ctl_table *ctl, int write, struct file *filp,
-+ void *buffer, size_t *lenp)
-+{
-+ int retval=0;
-+ unsigned i , clock ;
-+ if (write)
-+ {
-+ char buf[16], *p;
-+ unsigned int sleepsec;
-+ int len,left = *lenp;
-+
-+ len = left;
-+ if (left > sizeof(buf))
-+ left = sizeof(buf);
-+ if (!copy_from_user(buf, buffer, left))
-+ {
-+ buf[sizeof(buf) - 1] = '\0';
-+ sleepsec = simple_strtoul(buf, &p, 0);
-+ printk("\nSleeping %d Pwronoff=%x RCNR=%d\n",sleepsec,pm_pwronoff,RCNR);
-+ printk("\nPWER %x PFER=%x PRER=%x\n",PWER,PFER,PRER);
-+ RTAR = xtime.tv_sec + sleepsec;
-+ printk("\nRTAR=%d \n",RTAR);
-+ }
-+ }
-+ retval = pm_do_suspend();
-+ clock = get_memclk_frequency_10khz();
-+ return retval;
- }
--
--EXPORT_SYMBOL_GPL(pxa_pm_prepare);
-
- /*
-- * Called after devices are re-setup, but before processes are thawed.
-+static struct ctl_table pm_table[] =
-+{
-+ {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
-+ {0}
-+};
- */
--int pxa_pm_finish(suspend_state_t state)
-+static struct ctl_table pm_table[] =
- {
-- return 0;
-+ {
-+ ctl_name: ACPI_S1_SLP_TYP,
-+ procname: "suspend",
-+ mode: 0600,
-+ proc_handler: (proc_handler *)&sysctl_pm_do_suspend,
-+ },
-+ {
-+ ctl_name: 0
- }
-+};
-
--EXPORT_SYMBOL_GPL(pxa_pm_finish);
-+static struct ctl_table pm_dir_table[] =
-+{
-+ {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
-+ {0}
-+};
-
- /*
-- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
-+ * Initialize power interface
- */
--static struct pm_ops pxa_pm_ops = {
-- .pm_disk_mode = PM_DISK_FIRMWARE,
-- .prepare = pxa_pm_prepare,
-- .enter = pxa_pm_enter,
-- .finish = pxa_pm_finish,
--};
--
--static int __init pxa_pm_init(void)
-+static int __init pm_init(void)
- {
-- pm_set_ops(&pxa_pm_ops);
-+ register_sysctl_table(pm_dir_table, 1);
-+ /*Adi: Adjust for clock value to RTC
-+ RTTR = RTC clk - 1*/
-+ RTTR = 32913;
-+
- return 0;
- }
-
--device_initcall(pxa_pm_init);
-+__initcall(pm_init);
-+
-+#endif
-diff -NurbwB linux-2.6.17/arch/arm/mach-pxa/sleep.S linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S
---- linux-2.6.17/arch/arm/mach-pxa/sleep.S 2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S 2006-09-11 13:07:05.000000000 -0700
-@@ -79,7 +79,7 @@
- ldr r5, [r4]
-
- @ enable SDRAM self-refresh mode
-- orr r5, r5, #MDREFR_SLFRSH
-+ orr r5, r5, #(MDREFR_SLFRSH | MDREFR_APD)
-
- #ifdef CONFIG_PXA27x
- @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
-diff -NurbwB linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h
---- linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h 2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h 2006-09-11 11:04:36.000000000 -0700
-@@ -1748,6 +1748,15 @@
- #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
- #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
-
-+#define NSSCR0 __REG(0x41400000) /* SSP Port 1 Control Register 0 */
-+#define NSSCR1 __REG(0x41400004) /* SSP Port 1 Control Register 1 */
-+#define NSSSR __REG(0x41400008) /* SSP Port 1 Status Register */
-+#define NSSITR __REG(0x4140000C) /* SSP Port 1 Interrupt Test Register */
-+#define NSSDR __REG(0x41400010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
-+#define NSSTO __REG(0x41400028) /* SSP Port 1 Time Out Register */
-+#define NSSPSP __REG(0x4140002C) /* SSP Port 1 Programmable Serial Port Register */
-+
-+
- /*
- * MultiMediaCard (MMC) controller
- */
-diff -NurbwB linux-2.6.17/kernel/power/main.c linux-2.6.17-patched/kernel/power/main.c
---- linux-2.6.17/kernel/power/main.c 2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17-patched/kernel/power/main.c 2006-09-11 12:59:20.000000000 -0700
-@@ -66,10 +66,12 @@
- goto Enable_cpu;
- }
-
-+ /*
- if (freeze_processes()) {
- error = -EAGAIN;
- goto Thaw;
- }
-+ */
-
- if ((free_pages = nr_free_pages()) < FREE_PAGE_NUMBER) {
- pr_debug("PM: free some memory\n");
-@@ -110,12 +112,15 @@
-
- local_irq_save(flags);
-
-+ /*
- if ((error = device_power_down(PMSG_SUSPEND))) {
- printk(KERN_ERR "Some devices failed to power down\n");
- goto Done;
- }
-+ */
-+
- error = pm_ops->enter(state);
-- device_power_up();
-+ //device_power_up();
- Done:
- local_irq_restore(flags);
- return error;
projects / openwrt.git / blobdiff