++uint32
++BCMINITFN(sb_cpu_clock)(sb_t *sbh)
++{
++ extifregs_t *eir;
++ chipcregs_t *cc;
++ uint32 n, m;
++ uint idx;
++ uint32 pll_type, rate = 0;
++
++ /* get index of the current core */
++ idx = sb_coreidx(sbh);
++ pll_type = PLL_TYPE1;
++
++ /* switch to extif or chipc core */
++ if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
++ n = R_REG(&eir->clockcontrol_n);
++ m = R_REG(&eir->clockcontrol_sb);
++ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++ pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
++ n = R_REG(&cc->clockcontrol_n);
++ if ((pll_type == PLL_TYPE2) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE6) ||
++ (pll_type == PLL_TYPE7))
++ m = R_REG(&cc->clockcontrol_mips);
++ else if (pll_type == PLL_TYPE5) {
++ rate = 200000000;
++ goto out;
++ }
++ else if (pll_type == PLL_TYPE3) {
++ if (sb_chip(sbh) == 0x5365) {
++ rate = 200000000;
++ goto out;
++ }
++ /* 5350 uses m2 to control mips */
++ else
++ m = R_REG(&cc->clockcontrol_m2);
++ } else
++ m = R_REG(&cc->clockcontrol_sb);
++ } else
++ goto out;
++
++
++ /* calculate rate */
++ if (BCMINIT(sb_chip)(sbh) == 0x5365)
++ rate = 100000000;
++ else
++ rate = sb_clock_rate(pll_type, n, m);
++
++ if (pll_type == PLL_TYPE6)
++ rate = SB2MIPS_T6(rate);
++
++out:
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++
++ return rate;
++}
++
++EXPORT_SYMBOL(sb_irq);
+diff -urN linux-2.6.19.ref/arch/mips/bcm947xx/broadcom/sbpci.c linux-2.6.19/arch/mips/bcm947xx/broadcom/sbpci.c
+--- linux-2.6.19.ref/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19/arch/mips/bcm947xx/broadcom/sbpci.c 2006-12-04 21:33:48.000000000 +0100