#include <linux/glamofb.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/host.h>
+#include <linux/mfd/core.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/div64.h>
-//#include <mach/regs-irq.h>
-
#ifdef CONFIG_PM
#include <linux/pm.h>
#endif
#include "glamo-regs.h"
#include "glamo-core.h"
-#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
-
#define GLAMO_MEM_REFRESH_COUNT 0x100
-
/*
* Glamo internal settings
*
__reg_set_bit_mask(glamo, reg, bit, 0);
}
-static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
- u_int16_t *src, int len)
-{
- if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
- dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
- "0x%x)!!\n", addr, src, len);
- }
-
-}
-
-static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
- u_int32_t addr, int len)
-{
- if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
- dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
- "0x%x)!!\n", buf, addr, len);
- }
-
-
-}
-
/***********************************************************************
* resources of sibling devices
***********************************************************************/
-#if 0
-static struct resource glamo_core_resources[] = {
- {
- .start = GLAMO_REGOFS_GENERIC,
- .end = GLAMO_REGOFS_GENERIC + 0x400,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_core_dev = {
- .name = "glamo-core",
- .resource = &glamo_core_resources,
- .num_resources = ARRAY_SIZE(glamo_core_resources),
-};
-#endif
-
-static struct resource glamo_jpeg_resources[] = {
- {
- .start = GLAMO_REGOFS_JPEG,
- .end = GLAMO_REGOFS_MPEG - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_GLAMO_JPEG,
- .end = IRQ_GLAMO_JPEG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_jpeg_dev = {
- .name = "glamo-jpeg",
- .resource = glamo_jpeg_resources,
- .num_resources = ARRAY_SIZE(glamo_jpeg_resources),
-};
-
-static struct resource glamo_mpeg_resources[] = {
- {
- .start = GLAMO_REGOFS_MPEG,
- .end = GLAMO_REGOFS_LCD - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_GLAMO_MPEG,
- .end = IRQ_GLAMO_MPEG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_mpeg_dev = {
- .name = "glamo-mpeg",
- .resource = glamo_mpeg_resources,
- .num_resources = ARRAY_SIZE(glamo_mpeg_resources),
-};
-
-static struct resource glamo_2d_resources[] = {
- {
- .start = GLAMO_REGOFS_2D,
- .end = GLAMO_REGOFS_3D - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_GLAMO_2D,
- .end = IRQ_GLAMO_2D,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_2d_dev = {
- .name = "glamo-2d",
- .resource = glamo_2d_resources,
- .num_resources = ARRAY_SIZE(glamo_2d_resources),
-};
-
-static struct resource glamo_3d_resources[] = {
- {
- .start = GLAMO_REGOFS_3D,
- .end = GLAMO_REGOFS_END - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device glamo_3d_dev = {
- .name = "glamo-3d",
- .resource = glamo_3d_resources,
- .num_resources = ARRAY_SIZE(glamo_3d_resources),
-};
-
-static struct platform_device glamo_spigpio_dev = {
- .name = "glamo-spi-gpio",
-};
-
static struct resource glamo_fb_resources[] = {
- /* FIXME: those need to be incremented by parent base */
{
.name = "glamo-fb-regs",
.start = GLAMO_REGOFS_LCD,
},
};
-static struct platform_device glamo_fb_dev = {
- .name = "glamo-fb",
- .resource = glamo_fb_resources,
- .num_resources = ARRAY_SIZE(glamo_fb_resources),
-};
-
static struct resource glamo_mmc_resources[] = {
{
- /* FIXME: those need to be incremented by parent base */
.start = GLAMO_REGOFS_MMC,
.end = GLAMO_REGOFS_MPROC0 - 1,
.flags = IORESOURCE_MEM
},
};
-struct glamo_mci_pdata glamo_mci_def_pdata = {
+static struct glamo_mci_pdata glamo_mci_def_pdata = {
.gpio_detect = 0,
.glamo_can_set_mci_power = NULL, /* filled in from MFD platform data */
- .ocr_avail = MMC_VDD_20_21 |
- MMC_VDD_21_22 |
- MMC_VDD_22_23 |
- MMC_VDD_23_24 |
- MMC_VDD_24_25 |
- MMC_VDD_25_26 |
- MMC_VDD_26_27 |
- MMC_VDD_27_28 |
- MMC_VDD_28_29 |
- MMC_VDD_29_30 |
- MMC_VDD_30_31 |
- MMC_VDD_32_33,
.glamo_irq_is_wired = NULL, /* filled in from MFD platform data */
.mci_suspending = NULL, /* filled in from MFD platform data */
.mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
};
-EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
-
+enum glamo_cells {
+ GLAMO_CELL_FB,
+ GLAMO_CELL_MMC,
+ GLAMO_CELL_SPI_GPIO
+};
-static void mangle_mem_resources(struct resource *res, int num_res,
- struct resource *parent)
-{
- int i;
+static struct mfd_cell glamo_cells[] = {
+ [GLAMO_CELL_FB] = {
+ .name = "glamo-fb",
+ .num_resources = ARRAY_SIZE(glamo_fb_resources),
+ .resources = glamo_fb_resources,
+ },
+ [GLAMO_CELL_MMC] = {
+ .name = "glamo-mci",
+ .num_resources = ARRAY_SIZE(glamo_mmc_resources),
+ .resources = glamo_mmc_resources,
+ },
+ [GLAMO_CELL_SPI_GPIO] = {
+ .name = "glamo-spi-gpio",
+ },
+};
- for (i = 0; i < num_res; i++) {
- if (res[i].flags != IORESOURCE_MEM)
- continue;
- res[i].start += parent->start;
- res[i].end += parent->start;
- res[i].parent = parent;
- }
-}
/***********************************************************************
* IRQ demultiplexer
desc->chip->ack(irq);
return;
}
- kstat_incr_irqs_this_cpu(irq, desc);
+ kstat_incr_irqs_this_cpu(irq, desc);
desc->chip->ack(irq);
desc->status |= IRQ_INPROGRESS;
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_2D,
GLAMO_HOSTBUS2_MMIO_EN_2D);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
+ 0xffff);
break;
case GLAMO_ENGINE_CMDQ:
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_CQ,
GLAMO_HOSTBUS2_MMIO_EN_CQ);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
+ 0xffff);
break;
/* FIXME: Implementation */
default:
- break;
+ return -EINVAL;
}
glamo->engine_enabled_bitfield |= 1 << engine;
break;
case GLAMO_ENGINE_MMC:
-// __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
-// GLAMO_CLOCK_MMC_EN_M9CLK |
-// GLAMO_CLOCK_MMC_EN_TCLK |
-// GLAMO_CLOCK_MMC_DG_M9CLK |
-// GLAMO_CLOCK_MMC_DG_TCLK, 0);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
+ GLAMO_CLOCK_MMC_EN_M9CLK |
+ GLAMO_CLOCK_MMC_EN_TCLK |
+ GLAMO_CLOCK_MMC_DG_M9CLK |
+ GLAMO_CLOCK_MMC_DG_TCLK, 0);
/* disable the TCLK divider clk input */
-// __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
-// GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
-
- default:
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
break;
+ case GLAMO_ENGINE_CMDQ:
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
+ GLAMO_CLOCK_2D_EN_M6CLK,
+ 0);
+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
+ GLAMO_HOSTBUS2_MMIO_EN_CQ,
+ GLAMO_HOSTBUS2_MMIO_EN_CQ);
+/* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
+ 0);*/
+ break;
+ case GLAMO_ENGINE_2D:
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
+ GLAMO_CLOCK_2D_EN_M7CLK |
+ GLAMO_CLOCK_2D_EN_GCLK |
+ GLAMO_CLOCK_2D_DG_M7CLK |
+ GLAMO_CLOCK_2D_DG_GCLK,
+ 0);
+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
+ GLAMO_HOSTBUS2_MMIO_EN_2D,
+ GLAMO_HOSTBUS2_MMIO_EN_2D);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
+ 0);
+ break;
+ default:
+ return -EINVAL;
}
glamo->engine_enabled_bitfield &= ~(1 << engine);
[GLAMO_ENGINE_MMC] = {
GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
},
+ [GLAMO_ENGINE_CMDQ] = {
+ GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
+ },
[GLAMO_ENGINE_2D] = {
GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
},
{
int rc = 0, irq;
struct glamo_core *glamo;
- struct platform_device *glamo_mmc_dev;
if (glamo_handle) {
dev_err(&pdev->dev,
/* register a number of sibling devices whoise IOMEM resources
* are siblings of pdev's IOMEM resource */
-#if 0
- glamo_core_dev.dev.parent = &pdev.dev;
- mangle_mem_resources(glamo_core_dev.resources,
- glamo_core_dev.num_resources, glamo->mem);
- glamo_core_dev.resources[1].start = glamo->irq;
- glamo_core_dev.resources[1].end = glamo->irq;
- platform_device_register(&glamo_core_dev);
-#endif
+
/* only remap the generic, hostbus and memory controller registers */
glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
if (!glamo->base) {
glamo->irq_works = 0;
}
-
/* confirm it isn't insane version */
if (!glamo_supported(glamo)) {
dev_err(&pdev->dev, "This Glamo is not supported\n");
glamo_pll_rate(glamo, GLAMO_PLL1),
glamo_pll_rate(glamo, GLAMO_PLL2));
+ glamo->pdata->glamo = glamo;
+
/* bring MCI specific stuff over from our MFD platform data */
glamo_mci_def_pdata.glamo_can_set_mci_power =
glamo->pdata->glamo_can_set_mci_power;
glamo->pdata->glamo_mci_use_slow;
glamo_mci_def_pdata.glamo_irq_is_wired =
glamo->pdata->glamo_irq_is_wired;
+ glamo_mci_def_pdata.pglamo = glamo;
- /* start creating the siblings */
-
- glamo_2d_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_2d_dev.resource,
- glamo_2d_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_2d_dev);
-
- glamo_3d_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_3d_dev.resource,
- glamo_3d_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_3d_dev);
-
- glamo_jpeg_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_jpeg_dev.resource,
- glamo_jpeg_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_jpeg_dev);
-
- glamo_mpeg_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_mpeg_dev.resource,
- glamo_mpeg_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_mpeg_dev);
+ /* register siblings */
+ glamo_cells[GLAMO_CELL_MMC].platform_data = &glamo_mci_def_pdata;
+ glamo_cells[GLAMO_CELL_MMC].data_size = sizeof(glamo_mci_def_pdata);
- glamo->pdata->glamo = glamo;
- glamo_fb_dev.dev.parent = &pdev->dev;
- glamo_fb_dev.dev.platform_data = glamo->pdata;
- mangle_mem_resources(glamo_fb_dev.resource,
- glamo_fb_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_fb_dev);
+ glamo_cells[GLAMO_CELL_FB].platform_data = glamo->pdata;
+ glamo_cells[GLAMO_CELL_FB].data_size = sizeof(struct glamofb_platform_data);
glamo->pdata->spigpio_info->glamo = glamo;
- glamo_spigpio_dev.dev.parent = &pdev->dev;
- glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
- platform_device_register(&glamo_spigpio_dev);
-
- glamo_mmc_dev = glamo->pdata->mmc_dev;
- glamo_mmc_dev->name = "glamo-mci";
- glamo_mmc_dev->dev.parent = &pdev->dev;
- glamo_mmc_dev->resource = glamo_mmc_resources;
- glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
+ glamo_cells[GLAMO_CELL_SPI_GPIO].platform_data = glamo->pdata->spigpio_info;
+ glamo_cells[GLAMO_CELL_SPI_GPIO].data_size =
+ sizeof(struct glamo_spigpio_info);
- /* we need it later to give to the engine enable and disable */
- glamo_mci_def_pdata.pglamo = glamo;
- mangle_mem_resources(glamo_mmc_dev->resource,
- glamo_mmc_dev->num_resources, glamo->mem);
- platform_device_register(glamo_mmc_dev);
+ mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
+ ARRAY_SIZE(glamo_cells),
+ glamo->mem, 0);
/* only request the generic, hostbus and memory controller MMIO */
glamo->mem = request_mem_region(glamo->mem->start,
}
platform_set_drvdata(pdev, NULL);
- platform_device_unregister(&glamo_fb_dev);
- platform_device_unregister(glamo->pdata->mmc_dev);
+ mfd_remove_devices(&pdev->dev);
iounmap(glamo->base);
release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
glamo_handle = NULL;
projects / openwrt.git / blobdiff