X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/0c4c78bf4c8df288a664bf6dca154d77ea03f14e..ab881f8a9d0933f1064532287a4797f6070d6f39:/target/linux/generic/files/drivers/net/phy/rtl8366rb.c diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366rb.c b/target/linux/generic/files/drivers/net/phy/rtl8366rb.c index ec196f941..020e93a44 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8366rb.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8366rb.c @@ -1,8 +1,9 @@ /* - * Platform driver for the Realtek RTL8366S ethernet switch + * Platform driver for the Realtek RTL8366RB ethernet switch * * Copyright (C) 2009-2010 Gabor Juhos * Copyright (C) 2010 Antti Seppälä + * Copyright (C) 2010 Roman Yeryomin * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -15,12 +16,12 @@ #include #include #include -#include +#include #include "rtl8366_smi.h" #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver" -#define RTL8366RB_DRIVER_VER "0.2.2" +#define RTL8366RB_DRIVER_VER "0.2.3" #define RTL8366RB_PHY_NO_MAX 4 #define RTL8366RB_PHY_PAGE_MAX 7 @@ -163,6 +164,33 @@ #define RTL8366RB_VLAN_MEMBER_MASK 0xff #define RTL8366RB_VLAN_FID_MASK 0x7 + +/* Port ingress bandwidth control */ +#define RTL8366RB_IB_BASE 0x0200 +#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum) +#define RTL8366RB_IB_BDTH_MASK 0x3fff +#define RTL8366RB_IB_PREIFG_OFFSET 14 +#define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET) + +/* Port egress bandwidth control */ +#define RTL8366RB_EB_BASE 0x02d1 +#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum) +#define RTL8366RB_EB_BDTH_MASK 0x3fff +#define RTL8366RB_EB_PREIFG_REG 0x02f8 +#define RTL8366RB_EB_PREIFG_OFFSET 9 +#define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET) + +#define RTL8366RB_BDTH_SW_MAX 1048512 +#define RTL8366RB_BDTH_UNIT 64 +#define RTL8366RB_BDTH_REG_DEFAULT 16383 + +/* QOS */ +#define RTL8366RB_QOS_BIT 15 +#define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT) +/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */ +#define RTL8366RB_QOS_DEFAULT_PREIFG 1 + + static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = { { 0, 0, 4, "IfInOctets" }, { 0, 4, 4, "EtherStatsOctets" }, @@ -218,8 +246,8 @@ static int rtl8366rb_reset_chip(struct rtl8366_smi *smi) int timeout = 10; u32 data; - rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG, - RTL8366RB_CHIP_CTRL_RESET_HW); + rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG, + RTL8366RB_CHIP_CTRL_RESET_HW); do { msleep(1); if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data)) @@ -245,9 +273,6 @@ static int rtl8366rb_hw_init(struct rtl8366_smi *smi) REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK, RTL8366RB_SGCR_MAX_LENGTH_1536); - /* enable all ports */ - REG_WR(smi, RTL8366RB_PECR, 0); - /* enable learning for all ports */ REG_WR(smi, RTL8366RB_SSCR0, 0); @@ -429,8 +454,8 @@ static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi, int i; if (vlan4k->vid >= RTL8366RB_NUM_VIDS || - vlan4k->member > RTL8366RB_PORT_ALL || - vlan4k->untag > RTL8366RB_PORT_ALL || + vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK || + vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK || vlan4k->fid > RTL8366RB_FIDMAX) return -EINVAL; @@ -496,8 +521,8 @@ static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index, if (index >= RTL8366RB_NUM_VLANS || vlanmc->vid >= RTL8366RB_NUM_VIDS || vlanmc->priority > RTL8366RB_PRIORITYMAX || - vlanmc->member > RTL8366RB_PORT_ALL || - vlanmc->untag > RTL8366RB_PORT_ALL || + vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK || + vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK || vlanmc->fid > RTL8366RB_FIDMAX) return -EINVAL; @@ -578,6 +603,12 @@ static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable) (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0); } +static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port), + (enable) ? 0 : (1 << port)); +} + static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -650,59 +681,47 @@ static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev, return 0; } - -static const char *rtl8366rb_speed_str(unsigned speed) -{ - switch (speed) { - case 0: - return "10baseT"; - case 1: - return "100baseT"; - case 2: - return "1000baseT"; - } - - return "unknown"; -} - static int rtl8366rb_sw_get_port_link(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) + int port, + struct switch_port_link *link) { struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); - u32 len = 0, data = 0; + u32 data = 0; + u32 speed; - if (val->port_vlan >= RTL8366RB_NUM_PORTS) + if (port >= RTL8366RB_NUM_PORTS) return -EINVAL; - memset(smi->buf, '\0', sizeof(smi->buf)); - rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + - (val->port_vlan / 2), &data); + rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2), + &data); - if (val->port_vlan % 2) + if (port % 2) data = data >> 8; - if (data & RTL8366RB_PORT_STATUS_LINK_MASK) { - len = snprintf(smi->buf, sizeof(smi->buf), - "port:%d link:up speed:%s %s-duplex %s%s%s", - val->port_vlan, - rtl8366rb_speed_str(data & - RTL8366RB_PORT_STATUS_SPEED_MASK), - (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ? - "full" : "half", - (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ? - "tx-pause ": "", - (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ? - "rx-pause " : "", - (data & RTL8366RB_PORT_STATUS_AN_MASK) ? - "nway ": ""); - } else { - len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down", - val->port_vlan); - } + link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK); + if (!link->link) + return 0; - val->value.s = smi->buf; - val->len = len; + link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK); + link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK); + link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK); + link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK); + + speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK); + switch (speed) { + case 0: + link->speed = SWITCH_PORT_SPEED_10; + break; + case 1: + link->speed = SWITCH_PORT_SPEED_100; + break; + case 2: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } return 0; } @@ -748,6 +767,159 @@ static int rtl8366rb_sw_get_port_led(struct switch_dev *dev, return 0; } +static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 mask, data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + mask = 1 << val->port_vlan ; + if (val->value.i) + data = mask; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data); +} + +static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data); + if (data & (1 << val->port_vlan)) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX) + val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT; + else + val->value.i = RTL8366RB_BDTH_REG_DEFAULT; + + return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan), + RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK, + val->value.i | + (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET)); + +} + +static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data); + data &= RTL8366RB_IB_BDTH_MASK; + if (data < RTL8366RB_IB_BDTH_MASK) + data += 1; + + val->value.i = (int)data * RTL8366RB_BDTH_UNIT; + + return 0; +} + +static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG, + RTL8366RB_EB_PREIFG_MASK, + (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET)); + + if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX) + val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT; + else + val->value.i = RTL8366RB_BDTH_REG_DEFAULT; + + return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan), + RTL8366RB_EB_BDTH_MASK, val->value.i ); + +} + +static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data); + data &= RTL8366RB_EB_BDTH_MASK; + if (data < RTL8366RB_EB_BDTH_MASK) + data += 1; + + val->value.i = (int)data * RTL8366RB_BDTH_UNIT; + + return 0; +} + +static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->value.i) + data = RTL8366RB_QOS_MASK; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data); +} + +static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data); + if (data & RTL8366RB_QOS_MASK) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -774,7 +946,15 @@ static int rtl8366rb_sw_reset_switch(struct switch_dev *dev) if (err) return err; - return rtl8366_reset_vlan(smi); + err = rtl8366_reset_vlan(smi); + if (err) + return err; + + err = rtl8366_enable_vlan(smi, 1); + if (err) + return err; + + return rtl8366_enable_all_ports(smi, 1); } static struct switch_attr rtl8366rb_globals[] = { @@ -814,18 +994,18 @@ static struct switch_attr rtl8366rb_globals[] = { .set = rtl8366rb_sw_set_blinkrate, .get = rtl8366rb_sw_get_blinkrate, .max = 5 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_qos", + .description = "Enable QOS", + .set = rtl8366rb_sw_set_qos_enable, + .get = rtl8366rb_sw_get_qos_enable, + .max = 1 }, }; static struct switch_attr rtl8366rb_port[] = { { - .type = SWITCH_TYPE_STRING, - .name = "link", - .description = "Get port link information", - .max = 1, - .set = NULL, - .get = rtl8366rb_sw_get_port_link, - }, { .type = SWITCH_TYPE_NOVAL, .name = "reset_mib", .description = "Reset single port MIB counters", @@ -844,6 +1024,27 @@ static struct switch_attr rtl8366rb_port[] = { .max = 15, .set = rtl8366rb_sw_set_port_led, .get = rtl8366rb_sw_get_port_led, + }, { + .type = SWITCH_TYPE_INT, + .name = "disable", + .description = "Get/Set port state (enabled or disabled)", + .max = 1, + .set = rtl8366rb_sw_set_port_disable, + .get = rtl8366rb_sw_get_port_disable, + }, { + .type = SWITCH_TYPE_INT, + .name = "rate_in", + .description = "Get/Set port ingress (incoming) bandwidth limit in kbps", + .max = RTL8366RB_BDTH_SW_MAX, + .set = rtl8366rb_sw_set_port_rate_in, + .get = rtl8366rb_sw_get_port_rate_in, + }, { + .type = SWITCH_TYPE_INT, + .name = "rate_out", + .description = "Get/Set port egress (outgoing) bandwidth limit in kbps", + .max = RTL8366RB_BDTH_SW_MAX, + .set = rtl8366rb_sw_set_port_rate_out, + .get = rtl8366rb_sw_get_port_rate_out, }, }; @@ -855,6 +1056,13 @@ static struct switch_attr rtl8366rb_vlan[] = { .max = 1, .set = NULL, .get = rtl8366_sw_get_vlan_info, + }, { + .type = SWITCH_TYPE_INT, + .name = "fid", + .description = "Get/Set vlan FID", + .max = RTL8366RB_FIDMAX, + .set = rtl8366_sw_set_vlan_fid, + .get = rtl8366_sw_get_vlan_fid, }, }; @@ -877,6 +1085,7 @@ static const struct switch_dev_ops rtl8366_ops = { .get_port_pvid = rtl8366_sw_get_port_pvid, .set_port_pvid = rtl8366_sw_set_port_pvid, .reset_switch = rtl8366rb_sw_reset_switch, + .get_port_link = rtl8366rb_sw_get_port_link, }; static int rtl8366rb_switch_init(struct rtl8366_smi *smi) @@ -889,7 +1098,7 @@ static int rtl8366rb_switch_init(struct rtl8366_smi *smi) dev->ports = RTL8366RB_NUM_PORTS; dev->vlans = RTL8366RB_NUM_VIDS; dev->ops = &rtl8366_ops; - dev->devname = dev_name(smi->parent); + dev->alias = dev_name(smi->parent); err = register_switch(dev, NULL); if (err) @@ -929,12 +1138,6 @@ static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) return err; } -static int rtl8366rb_mii_bus_match(struct mii_bus *bus) -{ - return (bus->read == rtl8366rb_mii_read && - bus->write == rtl8366rb_mii_write); -} - static int rtl8366rb_setup(struct rtl8366_smi *smi) { int ret; @@ -997,12 +1200,13 @@ static struct rtl8366_smi_ops rtl8366rb_smi_ops = { .is_vlan_valid = rtl8366rb_is_vlan_valid, .enable_vlan = rtl8366rb_enable_vlan, .enable_vlan4k = rtl8366rb_enable_vlan4k, + .enable_port = rtl8366rb_enable_port, }; -static int __init rtl8366rb_probe(struct platform_device *pdev) +static int __devinit rtl8366rb_probe(struct platform_device *pdev) { static int rtl8366_smi_version_printed; - struct rtl8366rb_platform_data *pdata; + struct rtl8366_platform_data *pdata; struct rtl8366_smi *smi; int err; @@ -1025,6 +1229,9 @@ static int __init rtl8366rb_probe(struct platform_device *pdev) smi->gpio_sda = pdata->gpio_sda; smi->gpio_sck = pdata->gpio_sck; + smi->clk_delay = 10; + smi->cmd_read = 0xa9; + smi->cmd_write = 0xa8; smi->ops = &rtl8366rb_smi_ops; smi->cpu_port = RTL8366RB_PORT_NUM_CPU; smi->num_ports = RTL8366RB_NUM_PORTS; @@ -1053,32 +1260,6 @@ static int __init rtl8366rb_probe(struct platform_device *pdev) return err; } -static int rtl8366rb_phy_config_init(struct phy_device *phydev) -{ - if (!rtl8366rb_mii_bus_match(phydev->bus)) - return -EINVAL; - - return 0; -} - -static int rtl8366rb_phy_config_aneg(struct phy_device *phydev) -{ - return 0; -} - -static struct phy_driver rtl8366rb_phy_driver = { - .phy_id = 0x001cc960, - .name = "Realtek RTL8366RB", - .phy_id_mask = 0x1ffffff0, - .features = PHY_GBIT_FEATURES, - .config_aneg = rtl8366rb_phy_config_aneg, - .config_init = rtl8366rb_phy_config_init, - .read_status = genphy_read_status, - .driver = { - .owner = THIS_MODULE, - }, -}; - static int __devexit rtl8366rb_remove(struct platform_device *pdev) { struct rtl8366_smi *smi = platform_get_drvdata(pdev); @@ -1104,26 +1285,12 @@ static struct platform_driver rtl8366rb_driver = { static int __init rtl8366rb_module_init(void) { - int ret; - ret = platform_driver_register(&rtl8366rb_driver); - if (ret) - return ret; - - ret = phy_driver_register(&rtl8366rb_phy_driver); - if (ret) - goto err_platform_unregister; - - return 0; - - err_platform_unregister: - platform_driver_unregister(&rtl8366rb_driver); - return ret; + return platform_driver_register(&rtl8366rb_driver); } module_init(rtl8366rb_module_init); static void __exit rtl8366rb_module_exit(void) { - phy_driver_unregister(&rtl8366rb_phy_driver); platform_driver_unregister(&rtl8366rb_driver); } module_exit(rtl8366rb_module_exit); @@ -1132,5 +1299,6 @@ MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC); MODULE_VERSION(RTL8366RB_DRIVER_VER); MODULE_AUTHOR("Gabor Juhos "); MODULE_AUTHOR("Antti Seppälä "); +MODULE_AUTHOR("Roman Yeryomin "); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);