X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/16afabf47d3f67930f7acef9fff8b449cba9499c..030341e663f32bc3740a1edf5e2a01c198c979f2:/target/linux/brcm47xx/patches-2.6.37/150-cpu_fixes.patch

diff --git a/target/linux/brcm47xx/patches-2.6.37/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.37/150-cpu_fixes.patch
index 4533998e6..eae16b081 100644
--- a/target/linux/brcm47xx/patches-2.6.37/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx/patches-2.6.37/150-cpu_fixes.patch
@@ -299,7 +299,7 @@
  	 * silly idea of putting something else there ...
  	 */
  	switch (current_cpu_type()) {
-+	case CPU_BMIPS3300:
++	case CPU_BCM3302:
 +		{
 +			u32 cm;
 +			cm = read_c0_diag();
@@ -319,7 +319,7 @@
  
 +	/* Check if special workarounds are required */
 +#ifdef CONFIG_BCM47XX
-+	if (current_cpu_data.cputype == CPU_4KC && (current_cpu_data.processor_id & 0xff) == 0) {
++	if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
 +		printk("Enabling BCM4710A0 cache workarounds.\n");
 +		bcm4710 = 1;
 +	} else
@@ -345,7 +345,7 @@
  }
 --- a/arch/mips/mm/tlbex.c
 +++ b/arch/mips/mm/tlbex.c
-@@ -872,6 +872,9 @@ static void __cpuinit build_r4000_tlb_re
+@@ -873,6 +873,9 @@ static void __cpuinit build_r4000_tlb_re
  		/* No need for uasm_i_nop */
  	}
  
@@ -355,7 +355,7 @@
  #ifdef CONFIG_64BIT
  	build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
  #else
-@@ -1322,6 +1325,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -1323,6 +1326,9 @@ build_r4000_tlbchange_handler_head(u32 *
  				   struct uasm_reloc **r, unsigned int pte,
  				   unsigned int ptr)
  {