X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/191909b36e827ee338a367044652c3cd56c86517..e191d5d165c3d9ebaf04a7017079869e060e8341:/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
index 0f9bd2f22..5fcfc8738 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
@@ -29,6 +29,7 @@
 
 static void __iomem *ar724x_pci_localcfg_base;
 static void __iomem *ar724x_pci_devcfg_base;
+static int ar724x_pci_fixup_enable;
 
 static DEFINE_SPINLOCK(ar724x_pci_lock);
 
@@ -75,7 +76,7 @@ static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
 		data |= ((value & 0xFF) << s);
 		break;
 	case 2:
-		s = ((where & 2) << 4);
+		s = ((where & 2) << 3);
 		data &= ~(0xFFFF << s);
 		data |= ((value & 0xFFFF) << s);
 		break;
@@ -128,6 +129,26 @@ static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 	return PCIBIOS_SUCCESSFUL;
 }
 
+static void ar724x_pci_fixup(struct pci_dev *dev)
+{
+	u16 cmd;
+
+	if (!ar724x_pci_fixup_enable)
+		return;
+
+	if (dev->bus->number != 0 || dev->devfn != 0)
+		return;
+
+	/* setup COMMAND register */
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+	       PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+	       PCI_COMMAND_FAST_BACK;
+
+	pci_write_config_word(dev, PCI_COMMAND, cmd);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
+
 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 				  uint8_t pin)
 {
@@ -179,22 +200,68 @@ static struct pci_controller ar724x_pci_controller = {
 	.io_resource	= &ar724x_pci_io_resource,
 };
 
-int __init ar724x_pcibios_init(void)
+static void __init ar724x_pci_reset(void)
+{
+	ar71xx_device_stop(AR724X_RESET_PCIE);
+	ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
+	ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
+	udelay(100);
+
+	ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
+	udelay(100);
+	ar71xx_device_start(AR724X_RESET_PCIE_PHY);
+	ar71xx_device_start(AR724X_RESET_PCIE);
+}
+
+static int __init ar724x_pci_setup(void)
 {
 	u32 t;
 
+	/* setup COMMAND register */
+	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
+	    PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
+
+	ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
+	ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
+	ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
+
+	t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
+	if (t != 0x7) {
+		udelay(100000);
+		ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
+		udelay(100);
+		ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
+		udelay(100000);
+	}
+
+	ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
+	udelay(1000);
+
+	t = ar724x_pci_rr(AR724X_PCI_REG_APP);
+	if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
+		printk(KERN_WARNING "PCI: no PCIe module found\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+int __init ar724x_pcibios_init(void)
+{
+	int ret;
+
 	ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 						   AR724X_PCI_CRP_SIZE);
 
 	ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 						 AR724X_PCI_CFG_SIZE);
 
-	/* setup COMMAND register */
-	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
-	    PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-
-	ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
+	ar724x_pci_reset();
+	ret = ar724x_pci_setup();
+	if (ret)
+		return ret;
 
+	ar724x_pci_fixup_enable = 1;
 	register_pci_controller(&ar724x_pci_controller);
 
 	return 0;