X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/2f3b768d56c443c04e57ada7ac6893ef7c8ab7bc..ad3e5bb07833a31add352653c4f418854e30023c:/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
index d29880611..b5f4812b5 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
@@ -1,7 +1,7 @@
 /*
  *  Ralink RT288x SoC register definitions
  *
- *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  This program is free software; you can redistribute it and/or modify it
@@ -23,27 +23,31 @@
 #define RT2880_I2C_BASE		0x00300900
 #define RT2880_SPI_BASE		0x00300b00
 #define RT2880_UART1_BASE	0x00300c00
-#define RT2880_FE_BASE		0x00310000
-#define RT2880_ROM_BASE		0x00400000
-#define RT2880_PCI_BASE		0x00500000
-#define RT2880_WMAC_BASE	0x00600000
+#define RT2880_FE_BASE		0x00400000
+#define RT2880_ROM_BASE		0x00410000
+#define RT2880_PCM_BASE		0x00420000
+#define RT2880_PCI_BASE		0x00440000
+#define RT2880_WMAC_BASE	0x00480000
 #define RT2880_FLASH1_BASE	0x01000000
-#define RT2880_FLASH0_BASE	0x1fc00000
+#define RT2880_FLASH0_BASE	0x1dc00000
 #define RT2880_SDRAM_BASE	0x08000000
 
 #define RT2880_SYSC_SIZE	0x100
+#define RT2880_TIMER_SIZE	0x100
 #define RT2880_INTC_SIZE	0x100
 #define RT2880_MEMC_SIZE	0x100
 #define RT2880_UART0_SIZE	0x100
+#define RT2880_PIO_SIZE		0x100
 #define RT2880_UART1_SIZE	0x100
 #define RT2880_FLASH1_SIZE	(16 * 1024 * 1024)
-#define RT2880_FLASH0_SIZE	(4 * 1024 * 1024)
+#define RT2880_FLASH0_SIZE	(32 * 1024 * 1024)
 
 /* SYSC registers */
 #define SYSC_REG_CHIP_NAME0	0x000	/* Chip Name 0 */
 #define SYSC_REG_CHIP_NAME1	0x004	/* Chip Name 1 */
 #define SYSC_REG_CHIP_ID	0x00c	/* Chip Identification */
 #define SYSC_REG_SYSTEM_CONFIG	0x010	/* System Configuration */
+#define SYSC_REG_CLKCFG		0x030
 #define SYSC_REG_RESET_CTRL	0x034	/* Reset Control*/
 #define SYSC_REG_RESET_STATUS	0x038	/* Reset Status*/
 #define SYSC_REG_GPIO_MODE	0x060	/* GPIO Purpose Select */
@@ -61,6 +65,8 @@
 #define SYSTEM_CONFIG_CPUCLK_280	0x2
 #define SYSTEM_CONFIG_CPUCLK_300	0x3
 
+#define CLKCFG_SRAM_CS_N_WDT	BIT(9)
+
 #define RT2880_RESET_SYSTEM	BIT(0)
 #define RT2880_RESET_TIMER	BIT(1)
 #define RT2880_RESET_INTC	BIT(2)