X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/481a574f0f36e0c5b4602f503682d2b7fc7cab76..3d1e9d69441a6a32e5c437bdecebb421b818742d:/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch?ds=sidebyside diff --git a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch index eaa523126..d9e4dd78b 100644 --- a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch +++ b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch @@ -1,90 +1,100 @@ -diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S ---- linux.old/arch/mips/kernel/genex.S 2006-03-20 06:53:29.000000000 +0100 -+++ linux.dev/arch/mips/kernel/genex.S 2006-03-21 12:19:26.000000000 +0100 -@@ -72,6 +72,10 @@ +diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S +--- linux-2.6.19.ref/arch/mips/kernel/genex.S 2006-11-29 22:57:37.000000000 +0100 ++++ linux-2.6.19/arch/mips/kernel/genex.S 2006-12-04 21:34:09.000000000 +0100 +@@ -73,6 +73,10 @@ .set push .set mips3 .set noat -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + nop + nop +#endif mfc0 k1, CP0_CAUSE li k0, 31<<2 andi k1, k1, 0x7c -diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c ---- linux.old/arch/mips/mm/c-r4k.c 2006-03-20 06:53:29.000000000 +0100 -+++ linux.dev/arch/mips/mm/c-r4k.c 2006-03-21 12:19:26.000000000 +0100 -@@ -14,6 +14,12 @@ +diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c +--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100 ++++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:09.000000000 +0100 +@@ -13,6 +13,15 @@ #include #include -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX +#include "../bcm947xx/include/typedefs.h" +#include "../bcm947xx/include/sbconfig.h" ++#include "../bcm947xx/include/mipsinc.h" ++#undef MTC0 ++#undef MFC0 ++#undef cache_op +#include +#endif -+ #include #include #include -@@ -29,6 +35,9 @@ - #include +@@ -29,6 +38,9 @@ #include /* for run_uncached() */ + +/* For enabling BCM4710 cache workarounds */ +int bcm4710 = 0; + /* - * Must die. - */ -@@ -73,7 +82,9 @@ + * Special Variant of smp_call_function for use by cache functions: + * +@@ -93,6 +105,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); -- if (dc_lsize == 16) + if (bcm4710) + r4k_blast_dcache_page = blast_dcache_page; -+ else if (dc_lsize == 16) - r4k_blast_dcache_page = blast_dcache16_page; - else if (dc_lsize == 32) - r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; -@@ -85,7 +96,9 @@ ++ else + if (dc_lsize == 0) + r4k_blast_dcache_page = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -107,6 +122,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); -- if (dc_lsize == 16) + if (bcm4710) + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed; -+ else if (dc_lsize == 16) - r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; - else if (dc_lsize == 32) - r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; -@@ -97,7 +110,9 @@ ++ else + if (dc_lsize == 0) + r4k_blast_dcache_page_indexed = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -121,6 +139,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); -- if (dc_lsize == 16) + if (bcm4710) + r4k_blast_dcache = blast_dcache; -+ else if (dc_lsize == 16) - r4k_blast_dcache = blast_dcache16; - else if (dc_lsize == 32) - r4k_blast_dcache = blast_dcache32; -@@ -660,6 +675,8 @@ ++ else + if (dc_lsize == 0) + r4k_blast_dcache = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -538,6 +559,9 @@ + r4k_blast_icache(); + else + protected_blast_icache_range(start, end); ++ ++ if (bcm4710) ++ r4k_flush_cache_all(); + } + + static void r4k_flush_icache_range(unsigned long start, unsigned long end) +@@ -618,6 +642,8 @@ unsigned long addr = (unsigned long) arg; R4600_HIT_CACHEOP_WAR_IMPL; + BCM4710_PROTECTED_FILL_TLB(addr); + BCM4710_PROTECTED_FILL_TLB(addr + 4); - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + if (dc_lsize) + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); if (!cpu_icache_snoops_remote_store && scache_size) - protected_writeback_scache_line(addr & ~(sc_lsize - 1)); -@@ -1136,6 +1153,16 @@ - static inline void coherency_setup(void) +@@ -1135,6 +1161,16 @@ + static void __init coherency_setup(void) { change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); -+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365) ++#ifdef CONFIG_BCM947XX + if (BCM330X(current_cpu_data.processor_id)) { + __u32 cm = read_c0_diag(); + /* Enable icache */ @@ -97,13 +107,13 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c /* * c0_status.cu=0 specifies that updates by the sc instruction use -@@ -1165,6 +1192,15 @@ +@@ -1173,6 +1209,15 @@ /* Default cache error handler for R4000 and R5000 family */ set_uncached_handler (0x100, &except_vec2_generic, 0x80); + + /* Check if special workarounds are required */ -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) { + printk("Enabling BCM4710A0 cache workarounds.\n"); + bcm4710 = 1; @@ -113,25 +123,25 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c probe_pcache(); setup_scache(); -diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c ---- linux.old/arch/mips/mm/tlbex.c 2006-03-21 12:12:38.000000000 +0100 -+++ linux.dev/arch/mips/mm/tlbex.c 2006-03-21 12:19:26.000000000 +0100 -@@ -28,6 +28,10 @@ - - /* #define DEBUG_TLB */ +diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c +--- linux-2.6.19.ref/arch/mips/mm/tlbex.c 2006-12-04 21:33:48.000000000 +0100 ++++ linux-2.6.19/arch/mips/mm/tlbex.c 2006-12-04 21:34:09.000000000 +0100 +@@ -1174,6 +1174,10 @@ + #endif + } -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX +extern int bcm4710; +#endif + - static __init int __attribute__((unused)) r45k_bvahwbug(void) + static void __init build_r4000_tlb_refill_handler(void) { - /* XXX: We should probe for the presence of this bug, but we don't. */ -@@ -1152,6 +1156,12 @@ + u32 *p = tlb_handler; +@@ -1188,6 +1192,12 @@ memset(relocs, 0, sizeof(relocs)); memset(final_handler, 0, sizeof(final_handler)); -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + if (bcm4710) { + i_nop(&p); + } @@ -140,14 +150,14 @@ diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c /* * create the plain linear handler */ -diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h ---- linux.old/include/asm-mips/r4kcache.h 2006-03-20 06:53:29.000000000 +0100 -+++ linux.dev/include/asm-mips/r4kcache.h 2006-03-21 18:40:32.000000000 +0100 -@@ -16,6 +16,18 @@ - #include +diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h +--- linux-2.6.19.ref/include/asm-mips/r4kcache.h 2006-11-29 22:57:37.000000000 +0100 ++++ linux-2.6.19/include/asm-mips/r4kcache.h 2006-12-04 21:34:09.000000000 +0100 +@@ -17,6 +17,18 @@ #include + #include -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate) + +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr)) @@ -162,29 +172,31 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca /* * This macro return a properly sign-extended address suitable as base address * for indexed cache operations. Two issues here: -@@ -46,6 +58,7 @@ - +@@ -150,6 +162,7 @@ static inline void flush_dcache_line_indexed(unsigned long addr) { + __dflush_prologue + BCM4710_DUMMY_RREG(); cache_op(Index_Writeback_Inv_D, addr); + __dflush_epilogue } - -@@ -61,11 +74,13 @@ - +@@ -169,6 +182,7 @@ static inline void flush_dcache_line(unsigned long addr) { + __dflush_prologue + BCM4710_DUMMY_RREG(); cache_op(Hit_Writeback_Inv_D, addr); + __dflush_epilogue } - +@@ -176,6 +190,7 @@ static inline void invalidate_dcache_line(unsigned long addr) { + __dflush_prologue + BCM4710_DUMMY_RREG(); cache_op(Hit_Invalidate_D, addr); + __dflush_epilogue } - -@@ -97,6 +112,7 @@ +@@ -208,6 +223,7 @@ */ static inline void protected_flush_icache_line(unsigned long addr) { @@ -192,7 +204,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca protected_cache_op(Hit_Invalidate_I, addr); } -@@ -108,6 +124,7 @@ +@@ -219,6 +235,7 @@ */ static inline void protected_writeback_dcache_line(unsigned long addr) { @@ -200,7 +212,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca protected_cache_op(Hit_Writeback_Inv_D, addr); } -@@ -228,8 +245,52 @@ +@@ -339,8 +356,52 @@ : "r" (base), \ "i" (op)); @@ -254,30 +266,33 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca static inline void blast_##pfx##cache##lsize(void) \ { \ unsigned long start = INDEX_BASE; \ -@@ -239,6 +300,7 @@ - current_cpu_data.desc.waybit; \ - unsigned long ws, addr; \ +@@ -352,6 +413,7 @@ + \ + __##pfx##flush_prologue \ \ + war \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ cache##lsize##_unroll32(addr|ws,indexop); \ -@@ -249,6 +311,7 @@ - unsigned long start = page; \ - unsigned long end = page + PAGE_SIZE; \ +@@ -366,6 +428,7 @@ + \ + __##pfx##flush_prologue \ \ + war \ do { \ cache##lsize##_unroll32(start,hitop); \ start += lsize * 32; \ -@@ -265,29 +328,31 @@ +@@ -384,6 +447,8 @@ current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ + war \ ++ \ + __##pfx##flush_prologue \ + \ for (ws = 0; ws < ws_end; ws += ws_inc) \ - for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ +@@ -393,28 +458,30 @@ + __##pfx##flush_epilogue \ } -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) @@ -301,7 +316,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca /* build blast_xxx_range, protected_blast_xxx_range */ -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ -+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war) \ ++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ unsigned long end) \ { \ @@ -309,11 +324,16 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca unsigned long addr = start & ~(lsize - 1); \ unsigned long aend = (end - 1) & ~(lsize - 1); \ + war \ + \ + __##pfx##flush_prologue \ + \ while (1) { \ ++ war2 \ prot##cache_op(hitop, addr); \ if (addr == aend) \ -@@ -296,12 +361,12 @@ - } \ + break; \ +@@ -424,13 +491,13 @@ + __##pfx##flush_epilogue \ } -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) @@ -321,24 +341,26 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) -+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);) -+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) -+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) -+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);) -+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, ) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, ) /* blast_inv_dcache_range */ -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) -+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) +-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) ++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, ) #endif /* _ASM_R4KCACHE_H */ -diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h ---- linux.old/include/asm-mips/stackframe.h 2006-03-20 06:53:29.000000000 +0100 -+++ linux.dev/include/asm-mips/stackframe.h 2006-03-21 12:19:26.000000000 +0100 -@@ -285,6 +285,10 @@ +diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h +--- linux-2.6.19.ref/include/asm-mips/stackframe.h 2006-11-29 22:57:37.000000000 +0100 ++++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100 +@@ -334,6 +334,10 @@ .macro RESTORE_SP_AND_RET LONG_L sp, PT_R29(sp) .set mips3 -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + nop + nop +#endif