X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/5301b468d5943bbfa99b9386d2e00206f9223277..ca18bd2e66accae4cb8ca110a5a372b4b081d100:/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h index 8dbe02161..c0f3e7bc9 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h @@ -1,7 +1,7 @@ /* * Atheros AR71xx SoC specific definitions * - * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008-2009 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * Parts of this file are based on Atheros' 2.6.15 BSP @@ -56,6 +56,11 @@ #define AR71XX_DMA_SIZE 0x10000 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) #define AR71XX_STEREO_SIZE 0x10000 +#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR91XX_WMAC_SIZE 0x30000 + +#define AR71XX_MEM_SIZE_MIN 0x0200000 +#define AR71XX_MEM_SIZE_MAX 0x8000000 #define AR71XX_CPU_IRQ_BASE 0 #define AR71XX_MISC_IRQ_BASE 8 @@ -66,6 +71,7 @@ #define AR71XX_PCI_IRQ_COUNT 4 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2) +#define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2) #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) @@ -103,16 +109,32 @@ enum ar71xx_soc_type { extern enum ar71xx_soc_type ar71xx_soc; +extern unsigned long ar71xx_mach_type; + +#define AR71XX_MACH_GENERIC 0 +#define AR71XX_MACH_WP543 1 /* Compex WP543 */ +#define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */ +#define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */ +#define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */ +#define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */ +#define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */ +#define AR71XX_MACH_AP83 7 /* Atheros AP83 */ +#define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */ +#define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */ +#define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */ +#define AR71XX_MACH_WNR2000 11 /* NETGEAR WNR2000 */ +#define AR71XX_MACH_PB42 12 /* Atheros PB42 */ +#define AR71XX_MACH_MZK_W300NH 13 /* Planex MZK-W300NH */ +#define AR71XX_MACH_MZK_W04NU 14 /* Planex MZK-W04NU */ +#define AR71XX_MACH_UBNT_LSSR71 15 /* Ubiquiti LS-SR71 */ + /* * PLL block */ -#define PLL_REG_CPU_PLL_CFG 0x00 -#define PLL_REG_SEC_PLL_CFG 0x04 -#define PLL_REG_CPU_CLK_CTRL 0x08 -#define PLL_REG_ETH_INT0_CLK 0x10 -#define PLL_REG_ETH_INT1_CLK 0x14 -#define PLL_REG_ETH_EXT_CLK 0x18 -#define PLL_REG_PCI_CLK 0x1c +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 #define AR71XX_PLL_DIV_SHIFT 3 #define AR71XX_PLL_DIV_MASK 0x1f @@ -123,6 +145,14 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR71XX_AHB_DIV_SHIFT 20 #define AR71XX_AHB_DIV_MASK 0x7 +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR91XX_PLL_REG_CPU_CONFIG 0x00 +#define AR91XX_PLL_REG_ETH_CONFIG 0x04 +#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 + #define AR91XX_PLL_DIV_SHIFT 0 #define AR91XX_PLL_DIV_MASK 0x3ff #define AR91XX_DDR_DIV_SHIFT 22 @@ -130,6 +160,9 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR91XX_AHB_DIV_SHIFT 19 #define AR91XX_AHB_DIV_MASK 0x1 +#define AR91XX_ETH0_PLL_SHIFT 20 +#define AR91XX_ETH1_PLL_SHIFT 22 + extern void __iomem *ar71xx_pll_base; static inline void ar71xx_pll_wr(unsigned reg, u32 val) @@ -179,14 +212,14 @@ extern void ar71xx_add_device_usb(void) __init; #define GPIO_FUNC_STEREO_EN BIT(17) #define GPIO_FUNC_SLIC_EN BIT(16) -#define GPIO_FUNC_SPI_CS1_EN BIT(15) -#define GPIO_FUNC_SPI_CS0_EN BIT(14) -#define GPIO_FUNC_SPI_EN BIT(13) +#define GPIO_FUNC_SPI_CS2_EN BIT(13) +#define GPIO_FUNC_SPI_CS1_EN BIT(12) #define GPIO_FUNC_UART_EN BIT(8) #define GPIO_FUNC_USB_OC_EN BIT(4) #define GPIO_FUNC_USB_CLK_EN BIT(0) #define AR71XX_GPIO_COUNT 16 +#define AR91XX_GPIO_COUNT 22 extern void __iomem *ar71xx_gpio_base; @@ -207,18 +240,23 @@ extern void ar71xx_gpio_function_disable(u32 mask); /* * DDR_CTRL block */ -#define DDR_REG_PCI_WIN0 0x7c -#define DDR_REG_PCI_WIN1 0x80 -#define DDR_REG_PCI_WIN2 0x84 -#define DDR_REG_PCI_WIN3 0x88 -#define DDR_REG_PCI_WIN4 0x8c -#define DDR_REG_PCI_WIN5 0x90 -#define DDR_REG_PCI_WIN6 0x94 -#define DDR_REG_PCI_WIN7 0x98 -#define DDR_REG_FLUSH_GE0 0x9c -#define DDR_REG_FLUSH_GE1 0xa0 -#define DDR_REG_FLUSH_USB 0xa4 -#define DDR_REG_FLUSH_PCI 0xa8 +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR91XX_DDR_REG_FLUSH_GE0 0x7c +#define AR91XX_DDR_REG_FLUSH_GE1 0x80 +#define AR91XX_DDR_REG_FLUSH_USB 0x84 +#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 #define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN1_OFFS 0x11000000 @@ -271,20 +309,26 @@ extern void ar71xx_ddr_flush(u32 reg); /* * RESET block */ -#define RESET_REG_TIMER 0x00 -#define RESET_REG_TIMER_RELOAD 0x04 -#define RESET_REG_WDOG_CTRL 0x08 -#define RESET_REG_WDOG 0x0c -#define RESET_REG_MISC_INT_STATUS 0x10 -#define RESET_REG_MISC_INT_ENABLE 0x14 -#define RESET_REG_PCI_INT_STATUS 0x18 -#define RESET_REG_PCI_INT_ENABLE 0x1c -#define RESET_REG_GLOBAL_INT_STATUS 0x20 -#define RESET_REG_RESET_MODULE 0x24 -#define RESET_REG_PERFC_CTRL 0x2c -#define RESET_REG_PERFC0 0x30 -#define RESET_REG_PERFC1 0x34 -#define RESET_REG_REV_ID 0x90 +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR91XX_RESET_REG_RESET_MODULE 0x1c +#define AR91XX_RESET_REG_PERF_CTRL 0x20 +#define AR91XX_RESET_REG_PERFC0 0x24 +#define AR91XX_RESET_REG_PERFC1 0x28 #define WDOG_CTRL_LAST_RESET BIT(31) #define WDOG_CTRL_ACTION_MASK 3 @@ -309,6 +353,7 @@ extern void ar71xx_ddr_flush(u32 reg); #define RESET_MODULE_EXTERNAL BIT(28) #define RESET_MODULE_FULL_CHIP BIT(24) +#define RESET_MODULE_AMBA2WMAC BIT(22) #define RESET_MODULE_CPU_NMI BIT(21) #define RESET_MODULE_CPU_COLD BIT(20) #define RESET_MODULE_DMA BIT(19)