X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/5375152a1a3df5dfe8c0e82f6f42a63f059083b6..ca18bd2e66accae4cb8ca110a5a372b4b081d100:/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index f5de7c033..c0f3e7bc9 100644
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx SoC specific definitions
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP
@@ -56,6 +56,11 @@
 #define AR71XX_DMA_SIZE		0x10000
 #define AR71XX_STEREO_BASE	(AR71XX_APB_BASE + 0x000B0000)
 #define AR71XX_STEREO_SIZE	0x10000
+#define AR91XX_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
+#define AR91XX_WMAC_SIZE	0x30000
+
+#define AR71XX_MEM_SIZE_MIN	0x0200000
+#define AR71XX_MEM_SIZE_MAX	0x8000000
 
 #define AR71XX_CPU_IRQ_BASE	0
 #define AR71XX_MISC_IRQ_BASE	8
@@ -66,6 +71,7 @@
 #define AR71XX_PCI_IRQ_COUNT	4
 
 #define AR71XX_CPU_IRQ_PCI	(AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_WMAC	(AR71XX_CPU_IRQ_BASE + 2)
 #define AR71XX_CPU_IRQ_USB	(AR71XX_CPU_IRQ_BASE + 3)
 #define AR71XX_CPU_IRQ_GE0	(AR71XX_CPU_IRQ_BASE + 4)
 #define AR71XX_CPU_IRQ_GE1	(AR71XX_CPU_IRQ_BASE + 5)
@@ -116,6 +122,11 @@ extern unsigned long ar71xx_mach_type;
 #define AR71XX_MACH_TEW_632BRP	8	/* TRENDnet TEW-632BRP */
 #define AR71XX_MACH_UBNT_RS	9	/* Ubiquiti RouterStation */
 #define AR71XX_MACH_UBNT_LSX	10	/* Ubiquiti LSX */
+#define AR71XX_MACH_WNR2000	11	/* NETGEAR WNR2000 */
+#define AR71XX_MACH_PB42	12	/* Atheros PB42 */
+#define AR71XX_MACH_MZK_W300NH	13	/* Planex MZK-W300NH */
+#define AR71XX_MACH_MZK_W04NU	14	/* Planex MZK-W04NU */
+#define AR71XX_MACH_UBNT_LSSR71	15	/* Ubiquiti LS-SR71 */
 
 /*
  * PLL block
@@ -342,6 +353,7 @@ extern void ar71xx_ddr_flush(u32 reg);
 
 #define RESET_MODULE_EXTERNAL		BIT(28)
 #define RESET_MODULE_FULL_CHIP		BIT(24)
+#define RESET_MODULE_AMBA2WMAC		BIT(22)
 #define RESET_MODULE_CPU_NMI		BIT(21)
 #define RESET_MODULE_CPU_COLD		BIT(20)
 #define RESET_MODULE_DMA		BIT(19)