X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/60da4b4a94df250ac7cde9d73bdc97fb1ebc5774..4f3a09388f325ee4a6e3591bcd1b6224c88eb3e5:/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
index 98308ffe0..b2be7e508 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
@@ -25,7 +25,7 @@
 #define RT2880_UART1_BASE	0x00300c00
 #define RT2880_FE_BASE		0x00310000
 #define RT2880_ROM_BASE		0x00400000
-#define RT2880_PCI_BASE		0x00500000
+#define RT2880_PCI_BASE		0x00440000
 #define RT2880_WMAC_BASE	0x00600000
 #define RT2880_FLASH1_BASE	0x01000000
 #define RT2880_FLASH0_BASE	0x1fc00000
@@ -46,6 +46,7 @@
 #define SYSC_REG_SYSTEM_CONFIG	0x010	/* System Configuration */
 #define SYSC_REG_RESET_CTRL	0x034	/* Reset Control*/
 #define SYSC_REG_RESET_STATUS	0x038	/* Reset Status*/
+#define SYSC_REG_GPIO_MODE	0x060	/* GPIO Purpose Select */
 #define SYSC_REG_IA_ADDRESS	0x310	/* Illegal Access Address */
 #define SYSC_REG_IA_TYPE	0x314	/* Illegal Access Type */
 
@@ -75,6 +76,15 @@
 #define RT2880_RESET_FE		BIT(18)
 #define RT2880_RESET_PCM	BIT(19)
 
+#define RT2880_GPIO_MODE_I2C	BIT(0)
+#define RT2880_GPIO_MODE_UART0	BIT(1)
+#define RT2880_GPIO_MODE_SPI	BIT(2)
+#define RT2880_GPIO_MODE_UART1	BIT(3)
+#define RT2880_GPIO_MODE_JTAG	BIT(4)
+#define RT2880_GPIO_MODE_MDIO	BIT(5)
+#define RT2880_GPIO_MODE_SDRAM	BIT(6)
+#define RT2880_GPIO_MODE_PCI	BIT(7)
+
 #define RT2880_INTC_INT_TIMER0	BIT(0)
 #define RT2880_INTC_INT_TIMER1	BIT(1)
 #define RT2880_INTC_INT_UART0	BIT(2)