X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/74975289a3766867f9d3a513ebd1cbd26671574d..494412bf0a06cdb958e1c4aff3c5de820c57e960:/target/linux/brcm47xx-2.6/patches/100-board_support.patch diff --git a/target/linux/brcm47xx-2.6/patches/100-board_support.patch b/target/linux/brcm47xx-2.6/patches/100-board_support.patch index b6b953acb..d80a4fbc8 100644 --- a/target/linux/brcm47xx-2.6/patches/100-board_support.patch +++ b/target/linux/brcm47xx-2.6/patches/100-board_support.patch @@ -1,8157 +1,202 @@ -diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c ---- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,232 @@ -+/* -+ * CFE environment varialble access -+ * -+ * Copyright 2006, Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * Copyright 2001-2003, Broadcom Corporation -+ * -+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY -+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM -+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS -+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NVRAM_SIZE (0x1ff0) -+static char _nvdata[NVRAM_SIZE] __initdata; -+static char _valuestr[256] __initdata; -+ -+/* -+ * TLV types. These codes are used in the "type-length-value" -+ * encoding of the items stored in the NVRAM device (flash or EEPROM) -+ * -+ * The layout of the flash/nvram is as follows: -+ * -+ * -+ * -+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list. -+ * The "length" field marks the length of the data section, not -+ * including the type and length fields. -+ * -+ * Environment variables are stored as follows: -+ * -+ * = -+ * -+ * If bit 0 (low bit) is set, the length is an 8-bit value. -+ * If bit 0 (low bit) is clear, the length is a 16-bit value -+ * -+ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still -+ * indicates the size of the length field. -+ * -+ * Flags are from the constants below: -+ * -+ */ -+#define ENV_LENGTH_16BITS 0x00 /* for low bit */ -+#define ENV_LENGTH_8BITS 0x01 -+ -+#define ENV_TYPE_USER 0x80 -+ -+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l)) -+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER) -+ -+/* -+ * The actual TLV types we support -+ */ -+ -+#define ENV_TLV_TYPE_END 0x00 -+#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS) -+ -+/* -+ * Environment variable flags -+ */ -+ -+#define ENV_FLG_NORMAL 0x00 /* normal read/write */ -+#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */ -+#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */ -+ -+#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */ -+#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */ -+ -+ -+/* ********************************************************************* -+ * _nvram_read(buffer,offset,length) -+ * -+ * Read data from the NVRAM device -+ * -+ * Input parameters: -+ * buffer - destination buffer -+ * offset - offset of data to read -+ * length - number of bytes to read -+ * -+ * Return value: -+ * number of bytes read, or <0 if error occured -+ ********************************************************************* */ -+static int -+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length) -+{ -+ int i; -+ if (offset > NVRAM_SIZE) -+ return -1; -+ -+ for ( i = 0; i < length; i++) { -+ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i]; -+ } -+ return length; -+} -+ -+ -+static char* -+_strnchr(const char *dest,int c,size_t cnt) -+{ -+ while (*dest && (cnt > 0)) { -+ if (*dest == c) return (char *) dest; -+ dest++; -+ cnt--; -+ } -+ return NULL; -+} -+ -+ -+ -+/* -+ * Core support API: Externally visible. -+ */ +diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig +--- linux.old/arch/mips/Kconfig 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/arch/mips/Kconfig 2007-01-26 00:51:18.000000000 +0100 +@@ -4,6 +4,10 @@ + # Horrible source of confusion. Die, die, die ... + select EMBEDDED + ++config CFE ++ bool ++ # Common Firmware Environment + -+/* -+ * Get the value of an NVRAM variable -+ * @param name name of variable to get -+ * @return value of variable or NULL if undefined -+ */ + mainmenu "Linux/MIPS Kernel Configuration" + + menu "Machine selection" +@@ -240,6 +240,23 @@ + Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and + Olivetti M700-10 workstations. + ++config BCM947XX ++ bool "Support for BCM947xx based boards" ++ select DMA_NONCOHERENT ++ select HW_HAS_PCI ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SSB ++ select SSB_SERIAL ++ select SSB_DRIVER_PCICORE ++ select SSB_PCICORE_HOSTMODE ++ select CFE ++ select GENERIC_GPIO ++ help ++ Support for BCM947xx based boards + -+char* -+cfe_env_get(unsigned char *nv_buf, char* name) + config LASAT + bool "LASAT Networks platforms" + select DMA_NONCOHERENT +diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c +--- linux.old/arch/mips/kernel/cpu-probe.c 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/arch/mips/kernel/cpu-probe.c 2007-01-25 23:34:01.000000000 +0100 +@@ -711,6 +711,28 @@ + } + + ++static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +{ -+ int size; -+ unsigned char *buffer; -+ unsigned char *ptr; -+ unsigned char *envval; -+ unsigned int reclen; -+ unsigned int rectype; -+ int offset; -+ int flg; -+ -+ size = NVRAM_SIZE; -+ buffer = &_nvdata[0]; -+ -+ ptr = buffer; -+ offset = 0; -+ -+ /* Read the record type and length */ -+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { -+ goto error; -+ } -+ -+ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) { -+ -+ /* Adjust pointer for TLV type */ -+ rectype = *(ptr); -+ offset++; -+ size--; -+ -+ /* -+ * Read the length. It can be either 1 or 2 bytes -+ * depending on the code -+ */ -+ if (rectype & ENV_LENGTH_8BITS) { -+ /* Read the record type and length - 8 bits */ -+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { -+ goto error; -+ } -+ reclen = *(ptr); -+ size--; -+ offset++; -+ } -+ else { -+ /* Read the record type and length - 16 bits, MSB first */ -+ if (_nvram_read(nv_buf, ptr,offset,2) != 2) { -+ goto error; -+ } -+ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1); -+ size -= 2; -+ offset += 2; -+ } -+ -+ if (reclen > size) -+ break; /* should not happen, bad NVRAM */ -+ -+ switch (rectype) { -+ case ENV_TLV_TYPE_ENV: -+ /* Read the TLV data */ -+ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen) -+ goto error; -+ flg = *ptr++; -+ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1)); -+ if (envval) { -+ *envval++ = '\0'; -+ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr)); -+ _valuestr[(reclen-1)-(envval-ptr)] = '\0'; -+#if 0 -+ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr); -+#endif -+ if(!strcmp(ptr, name)){ -+ return _valuestr; -+ } -+ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name)) -+ return _valuestr; -+ } ++ decode_config1(c); ++ switch (c->processor_id & 0xff00) { ++ case PRID_IMP_BCM3302: ++ c->cputype = CPU_BCM3302; ++ c->isa_level = MIPS_CPU_ISA_M32R1; ++ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | ++ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER; ++ break; ++ case PRID_IMP_BCM4710: ++ c->cputype = CPU_BCM4710; ++ c->isa_level = MIPS_CPU_ISA_M32R1; ++ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | ++ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER; + break; -+ -+ default: -+ /* Unknown TLV type, skip it. */ ++ default: ++ c->cputype = CPU_UNKNOWN; + break; -+ } -+ -+ /* -+ * Advance to next TLV -+ */ -+ -+ size -= (int)reclen; -+ offset += reclen; -+ -+ /* Read the next record type */ -+ ptr = buffer; -+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) -+ goto error; + } -+ -+error: -+ return NULL; -+ +} + -diff -urN linux.old/arch/mips/bcm947xx/include/nvram.h linux.dev/arch/mips/bcm947xx/include/nvram.h ---- linux.old/arch/mips/bcm947xx/include/nvram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/include/nvram.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,37 @@ -+/* -+ * Copyright (C) 2006 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#ifndef __NVRAM_H -+#define __NVRAM_H -+ -+struct nvram_header { -+ u32 magic; -+ u32 len; -+ u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ -+ u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ -+ u32 config_ncdl; /* ncdl values for memc */ -+}; -+ -+struct nvram_tuple { -+ char *name; -+ char *value; -+ struct nvram_tuple *next; -+}; -+ -+#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */ -+#define NVRAM_VERSION 1 -+#define NVRAM_HEADER_SIZE 20 -+#define NVRAM_SPACE 0x8000 -+ -+#define NVRAM_MAX_VALUE_LEN 255 -+#define NVRAM_MAX_PARAM_LEN 64 -+ -+char *nvram_get(const char *name); -+ -+#endif -diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c ---- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/irq.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,63 @@ -+/* -+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+void plat_irq_dispatch(void) -+{ -+ u32 cause; -+ -+ cause = read_c0_cause() & read_c0_status() & CAUSEF_IP; -+ -+ clear_c0_status(cause); -+ -+ if (cause & CAUSEF_IP7) -+ do_IRQ(7); -+ if (cause & CAUSEF_IP2) -+ do_IRQ(2); -+ if (cause & CAUSEF_IP3) -+ do_IRQ(3); -+ if (cause & CAUSEF_IP4) -+ do_IRQ(4); -+ if (cause & CAUSEF_IP5) -+ do_IRQ(5); -+ if (cause & CAUSEF_IP6) -+ do_IRQ(6); -+} + __init void cpu_probe(void) + { + struct cpuinfo_mips *c = ¤t_cpu_data; +@@ -733,6 +755,9 @@ + case PRID_COMP_SIBYTE: + cpu_probe_sibyte(c); + break; ++ case PRID_COMP_BROADCOM: ++ cpu_probe_broadcom(c); ++ break; + case PRID_COMP_SANDCRAFT: + cpu_probe_sandcraft(c); + break; +diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c +--- linux.old/arch/mips/kernel/proc.c 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/arch/mips/kernel/proc.c 2007-01-25 23:34:01.000000000 +0100 +@@ -83,6 +83,8 @@ + [CPU_VR4181] = "NEC VR4181", + [CPU_VR4181A] = "NEC VR4181A", + [CPU_SR71000] = "Sandcraft SR71000", ++ [CPU_BCM3302] = "Broadcom BCM3302", ++ [CPU_BCM4710] = "Broadcom BCM4710", + [CPU_PR4450] = "Philips PR4450", + }; + +diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile +--- linux.old/arch/mips/Makefile 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/arch/mips/Makefile 2007-01-25 23:34:01.000000000 +0100 +@@ -576,6 +576,18 @@ + load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 + + # ++# Broadcom BCM47XX boards ++# ++core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ ++cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx ++load-$(CONFIG_BCM947XX) := 0xffffffff80001000 + -+void __init arch_init_irq(void) -+{ -+ mips_cpu_irq_init(0); -+} -diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile ---- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/Makefile 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,8 @@ +# -+# Makefile for the BCM47xx specific kernel interface routines -+# under Linux. ++# Common Firmware Environment ++# ++core-$(CONFIG_CFE) += arch/mips/cfe/ ++ +# + # SNI RM + # + core-$(CONFIG_SNI_RM) += arch/mips/sni/ +diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c +--- linux.old/arch/mips/mm/tlbex.c 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/arch/mips/mm/tlbex.c 2007-01-25 23:34:01.000000000 +0100 +@@ -892,6 +892,8 @@ + case CPU_4KSC: + case CPU_20KC: + case CPU_25KF: ++ case CPU_BCM3302: ++ case CPU_BCM4710: + tlbw(p); + break; + +diff -urN linux.old/drivers/Kconfig linux.dev/drivers/Kconfig +--- linux.old/drivers/Kconfig 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/drivers/Kconfig 2007-01-25 23:34:01.000000000 +0100 +@@ -56,6 +56,8 @@ + + source "drivers/hwmon/Kconfig" + ++source "drivers/ssb/Kconfig" + -+obj-y := irq.o prom.o setup.o time.o -+obj-y += nvram.o cfe_env.o -+#obj-y += pci.o -diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c ---- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/nvram.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,131 @@ + source "drivers/mfd/Kconfig" + + source "drivers/media/Kconfig" +diff -urN linux.old/drivers/Makefile linux.dev/drivers/Makefile +--- linux.old/drivers/Makefile 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/drivers/Makefile 2007-01-25 23:34:01.000000000 +0100 +@@ -81,3 +81,4 @@ + obj-$(CONFIG_DMA_ENGINE) += dma/ + obj-$(CONFIG_HID) += hid/ + obj-$(CONFIG_PPC_PS3) += ps3/ ++obj-$(CONFIG_SSB) += ssb/ +diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h +--- linux.old/include/asm-mips/bootinfo.h 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/include/asm-mips/bootinfo.h 2007-01-25 23:34:01.000000000 +0100 +@@ -213,6 +213,12 @@ + #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ + #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ + +/* -+ * BCM947xx nvram variable access -+ * -+ * Copyright 2006, Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * -+ * Copyright 2005, Broadcom Corporation -+ * -+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY -+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM -+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS -+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. -+ * ++ * Valid machtype for group Broadcom + */ ++#define MACH_GROUP_BRCM 23 /* Broadcom */ ++#define MACH_BCM47XX 1 /* Broadcom BCM47xx */ + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define MB * 1048576 -+extern struct ssb_bus ssb; -+ -+static char nvram_buf[NVRAM_SPACE]; -+static int cfe_env; -+extern char *cfe_env_get(char *nv_buf, const char *name); -+ -+/* Probe for NVRAM header */ -+static void __init early_nvram_init(void) -+{ -+ struct ssb_mipscore *mcore = &ssb.mipscore; -+ struct nvram_header *header; -+ int i; -+ u32 base, lim, off; -+ u32 *src, *dst; -+ -+ base = mcore->flash_window; -+ lim = mcore->flash_window_size; -+ cfe_env = 0; -+ -+ -+ /* XXX: hack for supporting the CFE environment stuff on WGT634U */ -+ if (lim >= 8 MB) { -+ src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000); -+ dst = (u32 *) nvram_buf; -+ -+ if ((*src & 0xff00ff) == 0x000001) { -+ printk("early_nvram_init: WGT634U NVRAM found.\n"); -+ -+ for (i = 0; i < 0x1ff0; i++) { -+ if (*src == 0xFFFFFFFF) -+ break; -+ *dst++ = *src++; -+ } -+ cfe_env = 1; -+ return; -+ } -+ } -+ -+ off = 0x20000; -+ while (off <= lim) { -+ /* Windowed flash access */ -+ header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE); -+ if (header->magic == NVRAM_HEADER) -+ goto found; -+ off <<= 1; -+ } -+ -+ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ -+ header = (struct nvram_header *) KSEG1ADDR(base + 4096); -+ if (header->magic == NVRAM_HEADER) -+ goto found; -+ -+ header = (struct nvram_header *) KSEG1ADDR(base + 1024); -+ if (header->magic == NVRAM_HEADER) -+ goto found; -+ -+ return; -+ -+found: -+ src = (u32 *) header; -+ dst = (u32 *) nvram_buf; -+ for (i = 0; i < sizeof(struct nvram_header); i += 4) -+ *dst++ = *src++; -+ for (; i < header->len && i < NVRAM_SPACE; i += 4) -+ *dst++ = le32_to_cpu(*src++); -+} -+ -+char *nvram_get(const char *name) -+{ -+ char *var, *value, *end, *eq; -+ -+ if (!name) -+ return NULL; -+ -+ if (!nvram_buf[0]) -+ early_nvram_init(); -+ -+ if (cfe_env) -+ return cfe_env_get(nvram_buf, name); -+ -+ /* Look for name=value and return value */ -+ var = &nvram_buf[sizeof(struct nvram_header)]; -+ end = nvram_buf + sizeof(nvram_buf) - 2; -+ end[0] = end[1] = '\0'; -+ for (; *var; var = value + strlen(value) + 1) { -+ if (!(eq = strchr(var, '='))) -+ break; -+ value = eq + 1; -+ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0) -+ return value; -+ } -+ -+ return NULL; -+} -diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c ---- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/pci.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,227 @@ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern sb_t *sbh; -+extern spinlock_t sbh_lock; -+ -+ -+static int -+sb_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int reg, int size, u32 *val) -+{ -+ int ret; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sbh_lock, flags); -+ ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size); -+ spin_unlock_irqrestore(&sbh_lock, flags); -+ -+ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -+} -+ -+static int -+sb_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int reg, int size, u32 val) -+{ -+ int ret; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sbh_lock, flags); -+ ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size); -+ spin_unlock_irqrestore(&sbh_lock, flags); -+ -+ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -+} -+ -+ -+static struct pci_ops sb_pci_ops = { -+ .read = sb_pci_read_config, -+ .write = sb_pci_write_config, -+}; -+ -+static struct resource sb_pci_mem_resource = { -+ .name = "SB PCI Memory resources", -+ .start = SB_ENUM_BASE, -+ .end = SB_ENUM_LIM - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource sb_pci_io_resource = { -+ .name = "SB PCI I/O resources", -+ .start = 0x000, -+ .end = 0x0FF, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct pci_controller bcm47xx_sb_pci_controller = { -+ .pci_ops = &sb_pci_ops, -+ .mem_resource = &sb_pci_mem_resource, -+ .io_resource = &sb_pci_io_resource, -+}; -+ -+static struct resource ext_pci_mem_resource = { -+ .name = "Ext PCI Memory resources", -+ .start = 0x40000000, -+ .end = 0x7fffffff, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource ext_pci_io_resource = { -+ .name = "Ext PCI I/O resources", -+ .start = 0x100, -+ .end = 0x7FF, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct pci_controller bcm47xx_ext_pci_controller = { -+ .pci_ops = &sb_pci_ops, -+ .io_resource = &ext_pci_io_resource, -+ .mem_resource = &ext_pci_mem_resource, -+ .mem_offset = 0x24000000, -+}; -+ -+void bcm47xx_pci_init(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sbh_lock, flags); -+ sbpci_init(sbh); -+ spin_unlock_irqrestore(&sbh_lock, flags); -+ -+ set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000)); -+ -+ register_pci_controller(&bcm47xx_sb_pci_controller); -+ register_pci_controller(&bcm47xx_ext_pci_controller); -+} -+ -+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ unsigned long flags; -+ u8 irq; -+ uint idx; -+ -+ /* external: use the irq of the pci core */ -+ if (dev->bus->number >= 1) { -+ spin_lock_irqsave(&sbh_lock, flags); -+ idx = sb_coreidx(sbh); -+ sb_setcore(sbh, SB_PCI, 0); -+ irq = sb_irq(sbh); -+ sb_setcoreidx(sbh, idx); -+ spin_unlock_irqrestore(&sbh_lock, flags); -+ -+ return irq + 2; -+ } -+ -+ /* internal */ -+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); -+ return irq + 2; -+} -+ -+u32 pci_iobase = 0x100; -+u32 pci_membase = SB_PCI_DMA; -+ -+static void bcm47xx_fixup_device(struct pci_dev *d) -+{ -+ struct resource *res; -+ int pos, size; -+ u32 *base; -+ -+ if (d->bus->number == 0) -+ return; -+ -+ printk("PCI: Fixing up device %s\n", pci_name(d)); -+ -+ /* Fix up resource bases */ -+ for (pos = 0; pos < 6; pos++) { -+ res = &d->resource[pos]; -+ base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase); -+ if (res->end) { -+ size = res->end - res->start + 1; -+ if (*base & (size - 1)) -+ *base = (*base + size) & ~(size - 1); -+ res->start = *base; -+ res->end = res->start + size - 1; -+ *base += size; -+ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); -+ } -+ /* Fix up PCI bridge BAR0 only */ -+ if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0) -+ break; -+ } -+ /* Fix up interrupt lines */ -+ if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL)) -+ d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq; -+ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); -+} -+ -+ -+static void bcm47xx_fixup_bridge(struct pci_dev *dev) -+{ -+ if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0) -+ return; -+ -+ printk("PCI: fixing up bridge\n"); + #define CL_SIZE COMMAND_LINE_SIZE + + const char *get_system_type(void); +diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h +--- linux.old/include/asm-mips/cpu.h 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/include/asm-mips/cpu.h 2007-01-25 23:34:01.000000000 +0100 +@@ -104,6 +104,13 @@ + #define PRID_IMP_SR71000 0x0400 + + /* ++ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM ++ */ + -+ /* Enable PCI bridge bus mastering and memory space */ -+ pci_set_master(dev); -+ pcibios_enable_device(dev, ~0); -+ -+ /* Enable PCI bridge BAR1 prefetch and burst */ -+ pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3); -+} ++#define PRID_IMP_BCM4710 0x4000 ++#define PRID_IMP_BCM3302 0x9000 + -+/* Do platform specific device initialization at pci_enable_device() time */ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ uint coreidx; -+ unsigned long flags; -+ -+ bcm47xx_fixup_device(dev); -+ -+ /* These cores come out of reset enabled */ -+ if ((dev->bus->number != 0) || -+ (dev->device == SB_MIPS) || -+ (dev->device == SB_MIPS33) || -+ (dev->device == SB_EXTIF) || -+ (dev->device == SB_CC)) -+ return 0; -+ -+ /* Do a core reset */ -+ spin_lock_irqsave(&sbh_lock, flags); -+ coreidx = sb_coreidx(sbh); -+ if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) { -+ /* -+ * The USB core requires a special bit to be set during core -+ * reset to enable host (OHCI) mode. Resetting the SB core in -+ * pcibios_enable_device() is a hack for compatibility with -+ * vanilla usb-ohci so that it does not have to know about -+ * SB. A driver that wants to use the USB core in device mode -+ * should know about SB and should reset the bit back to 0 -+ * after calling pcibios_enable_device(). -+ */ -+ sb_core_disable(sbh, sb_coreflags(sbh, 0, 0)); -+ sb_core_reset(sbh, 1 << 29); -+ } else { -+ sb_core_reset(sbh, 0); -+ } -+ sb_setcoreidx(sbh, coreidx); -+ spin_unlock_irqrestore(&sbh_lock, flags); -+ -+ return 0; -+} -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge); -diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c ---- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/prom.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,59 @@ -+/* -+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+const char *get_system_type(void) -+{ -+ return "Broadcom BCM47xx"; -+} -+ -+void __init prom_init(void) -+{ -+ unsigned long mem; -+ -+ mips_machgroup = MACH_GROUP_BRCM; -+ mips_machtype = MACH_BCM47XX; -+ -+ /* Figure out memory size by finding aliases */ -+ for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) { -+ if (*(unsigned long *)((unsigned long)(prom_init) + mem) == -+ *(unsigned long *)(prom_init)) -+ break; -+ } -+ -+ add_memory_region(0, mem, BOOT_MEM_RAM); -+} -+ -+unsigned long __init prom_free_prom_memory(void) -+{ -+ return 0; -+} -diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c ---- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/setup.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,161 @@ -+/* -+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) -+ * Copyright (C) 2005 Waldemar Brodkorb -+ * Copyright (C) 2006 Felix Fietkau -+ * Copyright (C) 2006 Michael Buesch -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+extern void bcm47xx_pci_init(void); -+extern void bcm47xx_time_init(void); -+ -+struct ssb_bus ssb; -+ -+static void bcm47xx_machine_restart(char *command) -+{ -+ printk(KERN_ALERT "Please stand by while rebooting the system...\n"); -+ local_irq_disable(); -+ /* CFE has a reboot callback, but that does not work. -+ * Oopses with: Reserved instruction in kernel code. -+ */ -+ -+ /* Set the watchdog timer to reset immediately */ -+//TODO sb_watchdog(sbh, 1); -+ while (1) -+ cpu_relax(); -+} -+ -+static void bcm47xx_machine_halt(void) -+{ -+ /* Disable interrupts and watchdog and spin forever */ -+ local_irq_disable(); -+//TODO sb_watchdog(sbh, 0); -+ while (1) -+ cpu_relax(); -+} -+ -+static void e_aton(char *str, char *dest) -+{ -+ int i = 0; -+ -+ if (str == NULL) { -+ memset(dest, 0, 6); -+ return; -+ } -+ -+ for (;;) { -+ dest[i++] = (char) simple_strtoul(str, NULL, 16); -+ str += 2; -+ if (!*str++ || i == 6) -+ break; -+ } -+} -+ -+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) -+{ -+ // TODO -+} -+ -+static void bcm47xx_fill_sprom_nvram(struct ssb_sprom *sprom) -+{ -+ char *s; -+ -+ memset(sprom, 0, sizeof(struct ssb_sprom)); -+ -+ sprom->revision = 3; -+ if ((s = nvram_get("et0macaddr"))) -+ e_aton(s, sprom->r1.et0mac); -+ if ((s = nvram_get("et1macaddr"))) -+ e_aton(s, sprom->r1.et1mac); -+ if ((s = nvram_get("et0phyaddr"))) -+ sprom->r1.et0phyaddr = simple_strtoul(s, NULL, 10); -+ if ((s = nvram_get("et1phyaddr"))) -+ sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10); -+} -+ -+void __init plat_mem_setup(void) -+{ -+ int i, err; -+ char *s; -+ struct ssb_mipscore *mcore; -+ -+ err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom); -+ if (err) { -+ const char *msg = "Failed to initialize SSB bus (err %d)\n"; -+ cfe_printk(msg, err); /* Make sure the message gets out of the box. */ -+ panic(msg, err); -+ } -+ mcore = &ssb.mipscore; -+ -+ /* FIXME: the nvram init depends on the ssb being fully initializes, -+ * can't use the fill_sprom callback yet! */ -+ bcm47xx_fill_sprom_nvram(&ssb.sprom); -+ -+ s = nvram_get("kernel_args"); -+ if (s && !strncmp(s, "console=ttyS1", 13) && (mcore->nr_serial_ports >= 2)) { -+ struct ssb_serial_port port; -+ -+ /* swap serial ports */ -+ memcpy(&port, &mcore->serial_ports[0], sizeof(port)); -+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port)); -+ memcpy(&mcore->serial_ports[1], &port, sizeof(port)); -+ } -+ -+ for (i = 0; i < mcore->nr_serial_ports; i++) { -+ struct ssb_serial_port *port = &(mcore->serial_ports[i]); -+ struct uart_port s; -+ -+ memset(&s, 0, sizeof(s)); -+ s.line = i; -+ s.membase = port->regs; -+ s.irq = port->irq + 2;//FIXME? -+ s.uartclk = port->baud_base; -+ s.flags = ASYNC_BOOT_AUTOCONF; -+ s.iotype = SERIAL_IO_MEM; -+ s.regshift = port->reg_shift; -+ -+ early_serial_setup(&s); -+ } -+ cfe_printk("Serial init done.\n"); -+ -+ _machine_restart = bcm47xx_machine_restart; -+ _machine_halt = bcm47xx_machine_halt; -+ pm_power_off = bcm47xx_machine_halt; -+ -+ board_time_init = bcm47xx_time_init;//FIXME move into ssb -+} -+ -diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c ---- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/bcm947xx/time.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,62 @@ -+/* -+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern struct ssb_bus ssb; -+ -+void __init -+bcm47xx_time_init(void) -+{ -+ unsigned long hz; -+ -+ /* -+ * Use deterministic values for initial counter interrupt -+ * so that calibrate delay avoids encountering a counter wrap. -+ */ -+ write_c0_count(0); -+ write_c0_compare(0xffff); -+ -+ hz = ssb_clockspeed(&ssb); -+ if (!hz) -+ hz = 100000000; -+ -+ /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */ -+ mips_hpt_frequency = hz; -+} -+ -+void __init -+plat_timer_setup(struct irqaction *irq) -+{ -+ /* Enable the timer interrupt */ -+ setup_irq(7, irq); -+} -diff -urN linux.old/arch/mips/cfe/cfe.c linux.dev/arch/mips/cfe/cfe.c ---- linux.old/arch/mips/cfe/cfe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/cfe/cfe.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,533 @@ -+/* -+ * Broadcom Common Firmware Environment (CFE) support -+ * -+ * Copyright 2000, 2001, 2002 -+ * Broadcom Corporation. All rights reserved. -+ * -+ * Copyright (C) 2006 Michael Buesch -+ * -+ * Original Authors: Mitch Lichtenberg, Chris Demetriou -+ * -+ * This software is furnished under license and may be used and copied only -+ * in accordance with the following terms and conditions. Subject to these -+ * conditions, you may download, copy, install, use, modify and distribute -+ * modified or unmodified copies of this software in source and/or binary -+ * form. No title or ownership is transferred hereby. -+ * -+ * 1) Any source code used, modified or distributed must reproduce and -+ * retain this copyright notice and list of conditions as they appear in -+ * the source file. -+ * -+ * 2) No right is granted to use any trade name, trademark, or logo of -+ * Broadcom Corporation. The "Broadcom Corporation" name may not be -+ * used to endorse or promote products derived from this software -+ * without the prior written permission of Broadcom Corporation. -+ * -+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR -+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE -+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE -+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "cfe_private.h" -+ -+ -+static cfe_uint_t cfe_handle; -+static int (*cfe_trampoline)(long handle, long iocb); -+ -+ -+#include -+ -+void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1, -+ unsigned long fwarg2, unsigned long fwarg3) -+{ -+ if (fwarg3 == 0x80300000) { -+ /* WRT54G workaround */ -+ fwarg3 = CFE_EPTSEAL; -+ fwarg2 = 0xBFC00500; -+ } -+ if (fwarg3 != CFE_EPTSEAL) { -+ /* We are not booted from CFE */ -+ return; -+ } -+ if (fwarg1 == 0) { -+ /* We are on the boot CPU */ -+ cfe_handle = (cfe_uint_t)fwarg0; -+ cfe_trampoline = CFE_TO_PTR(fwarg2); -+ } -+} -+ -+int cfe_vprintk(const char *fmt, va_list args) -+{ -+ static char buffer[1024]; -+ static DEFINE_SPINLOCK(lock); -+ static const char pfx[] = "CFE-console: "; -+ static const size_t pfx_len = sizeof(pfx) - 1; -+ unsigned long flags; -+ int len, cnt, pos; -+ int handle; -+ int res; -+ -+ if (!cfe_present()) -+ return -ENODEV; -+ -+ spin_lock_irqsave(&lock, flags); -+ handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); -+ if (CFE_ISERR(handle)) { -+ len = -EIO; -+ goto out; -+ } -+ strcpy(buffer, pfx); -+ len = vscnprintf(buffer + pfx_len, -+ sizeof(buffer) - pfx_len - 2, -+ fmt, args); -+ len += pfx_len; -+ /* The CFE console requires CR-LF line-ends. -+ * Add a CR, if we only terminate lines with a LF. -+ * This does only fix CR-LF at the end of the string. -+ * So for multiple lines, use multiple cfe_vprintk calls. -+ */ -+ if (len > 1 && -+ buffer[len - 1] == '\n' && buffer[len - 2] != '\r') { -+ buffer[len - 1] = '\r'; -+ buffer[len] = '\n'; -+ len += 1; -+ } -+ cnt = len; -+ pos = 0; -+ while (cnt > 0) { -+ res = cfe_write(handle, buffer + pos, len - pos); -+ if (CFE_ISERR(res)) { -+ len = -EIO; -+ goto out; -+ } -+ cnt -= res; -+ pos += res; -+ } -+out: -+ spin_unlock_irqrestore(&lock, flags); -+ -+ return len; -+} -+ -+int cfe_printk(const char *fmt, ...) -+{ -+ va_list args; -+ int res; -+ -+ va_start(args, fmt); -+ res = cfe_vprintk(fmt, args); -+ va_end(args); -+ -+ return res; -+} -+ -+static int cfe_iocb_dispatch(struct cfe_iocb *iocb) -+{ -+ if (!cfe_present()) -+ return CFE_ERR_UNSUPPORTED; -+ return cfe_trampoline((long)cfe_handle, (long)iocb); -+} -+ -+int cfe_present(void) -+{ -+ return (cfe_trampoline != NULL); -+} -+ -+int cfe_close(int handle) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_CLOSE; -+ iocb.handle = handle; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_FW_CPUCTL; -+ iocb.psize = sizeof(struct cfe_iocb_cpuctl); -+ iocb.cpuctl.number = cpu; -+ iocb.cpuctl.command = CFE_CPU_CMD_START; -+ iocb.cpuctl.gp = gp; -+ iocb.cpuctl.sp = sp; -+ iocb.cpuctl.a1 = a1; -+ iocb.cpuctl.start_addr = (long)fn; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_cpu_stop(int cpu) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_FW_CPUCTL; -+ iocb.psize = sizeof(struct cfe_iocb_cpuctl); -+ iocb.cpuctl.number = cpu; -+ iocb.cpuctl.command = CFE_CPU_CMD_STOP; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_ENV_ENUM; -+ iocb.psize = sizeof(struct cfe_iocb_envbuf); -+ iocb.envbuf.index = idx; -+ iocb.envbuf.name = PTR_TO_CFE(name); -+ iocb.envbuf.name_len = namelen; -+ iocb.envbuf.val = PTR_TO_CFE(val); -+ iocb.envbuf.val_len = vallen; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_enumdev(int idx, char *name, int namelen) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ -+ iocb.fcode = CFE_CMD_DEV_ENUM; -+ iocb.psize = sizeof(struct cfe_iocb_envbuf); -+ iocb.envbuf.index = idx; -+ iocb.envbuf.name = PTR_TO_CFE(name); -+ iocb.envbuf.name_len = namelen; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_enummem(int idx, int flags, u64 *start, u64 *length, -+ u64 *type) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ -+ iocb.fcode = CFE_CMD_FW_MEMENUM; -+ iocb.flags = flags; -+ iocb.psize = sizeof(struct cfe_iocb_meminfo); -+ iocb.meminfo.index = idx; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (!CFE_ISERR(iocb.status)) { -+ *start = iocb.meminfo.addr; -+ *length = iocb.meminfo.size; -+ *type = iocb.meminfo.type; -+ } -+ -+ return iocb.status; -+} -+ -+int cfe_exit(int warm, int status) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+printk("CFE REBOOT\n"); -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_FW_RESTART; -+ if (warm) -+ iocb.flags = CFE_FLG_WARMSTART; -+ iocb.psize = sizeof(struct cfe_iocb_exitstat); -+ iocb.exitstat.status = status; -+ -+printk("CALL\n"); -+ err = cfe_iocb_dispatch(&iocb); -+printk("DONE\n"); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_flushcache(int flags) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_FW_FLUSHCACHE; -+ iocb.flags = flags; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_getdevinfo(char *name) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_GETINFO; -+ iocb.psize = sizeof(struct cfe_iocb_buf); -+ iocb.buffer.ptr = PTR_TO_CFE(name); -+ iocb.buffer.length = strlen(name); -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ -+ return iocb.buffer.devflags; -+} -+ -+int cfe_getenv(char *name, char *dest, int destlen) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ dest[0] = '\0'; -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_ENV_GET; -+ iocb.psize = sizeof(struct cfe_iocb_envbuf); -+ iocb.envbuf.name = PTR_TO_CFE(name); -+ iocb.envbuf.name_len = strlen(name); -+ iocb.envbuf.val = PTR_TO_CFE(dest); -+ iocb.envbuf.val_len = destlen; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_getfwinfo(struct cfe_fwinfo *info) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_FW_GETINFO; -+ iocb.psize = sizeof(struct cfe_iocb_fwinfo); -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return err; -+ -+ info->version = iocb.fwinfo.version; -+ info->totalmem = iocb.fwinfo.totalmem; -+ info->flags = iocb.fwinfo.flags; -+ info->boardid = iocb.fwinfo.boardid; -+ info->bootarea_va = iocb.fwinfo.bootarea_va; -+ info->bootarea_pa = iocb.fwinfo.bootarea_pa; -+ info->bootarea_size = iocb.fwinfo.bootarea_size; -+ -+ return iocb.status; -+} -+ -+int cfe_getstdhandle(int handletype) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_GETHANDLE; -+ iocb.flags = handletype; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ -+ return iocb.handle; -+} -+ -+int cfe_getticks(s64 *ticks) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_FW_GETTIME; -+ iocb.psize = sizeof(struct cfe_iocb_time); -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (!CFE_ISERR(iocb.status)) -+ *ticks = iocb.time.ticks; -+ -+ return iocb.status; -+} -+ -+int cfe_inpstat(int handle) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_INPSTAT; -+ iocb.handle = handle; -+ iocb.psize = sizeof(struct cfe_iocb_inpstat); -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ -+ return iocb.inpstat.status; -+} -+ -+int cfe_ioctl(int handle, unsigned int ioctlnum, -+ unsigned char *buffer, int length, -+ int *retlen, u64 offset) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_IOCTL; -+ iocb.handle = handle; -+ iocb.psize = sizeof(struct cfe_iocb_buf); -+ iocb.buffer.offset = offset; -+ iocb.buffer.ioctlcmd = ioctlnum; -+ iocb.buffer.ptr = PTR_TO_CFE(buffer); -+ iocb.buffer.length = length; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ if (retlen) -+ *retlen = iocb.buffer.retlen; -+ -+ return iocb.status; -+} -+ -+int cfe_open(char *name) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_OPEN; -+ iocb.psize = sizeof(struct cfe_iocb_buf); -+ iocb.buffer.ptr = PTR_TO_CFE(name); -+ iocb.buffer.length = strlen(name); -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ -+ return iocb.handle; -+} -+ -+int cfe_read(int handle, unsigned char *buffer, int length) -+{ -+ return cfe_readblk(handle, 0, buffer, length); -+} -+ -+int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_READ; -+ iocb.handle = handle; -+ iocb.psize = sizeof(struct cfe_iocb_buf); -+ iocb.buffer.offset = offset; -+ iocb.buffer.ptr = PTR_TO_CFE(buffer); -+ iocb.buffer.length = length; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ -+ return iocb.buffer.retlen; -+} -+ -+int cfe_setenv(char *name, char *val) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_ENV_SET; -+ iocb.psize = sizeof(struct cfe_iocb_envbuf); -+ iocb.envbuf.name = PTR_TO_CFE(name); -+ iocb.envbuf.name_len = strlen(name); -+ iocb.envbuf.val = PTR_TO_CFE(val); -+ iocb.envbuf.val_len = strlen(val); -+ -+ err = cfe_iocb_dispatch(&iocb); -+ -+ return (CFE_ISERR(err)) ? err : iocb.status; -+} -+ -+int cfe_write(int handle, unsigned char *buffer, int length) -+{ -+ return cfe_writeblk(handle, 0, buffer, length); -+} -+ -+int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) -+{ -+ struct cfe_iocb iocb; -+ int err; -+ -+ memset(&iocb, 0, sizeof(iocb)); -+ iocb.fcode = CFE_CMD_DEV_WRITE; -+ iocb.handle = handle; -+ iocb.psize = sizeof(struct cfe_iocb_buf); -+ iocb.buffer.offset = offset; -+ iocb.buffer.ptr = PTR_TO_CFE(buffer); -+ iocb.buffer.length = length; -+ -+ err = cfe_iocb_dispatch(&iocb); -+ if (CFE_ISERR(err)) -+ return err; -+ if (CFE_ISERR(iocb.status)) -+ return iocb.status; -+ -+ return iocb.buffer.retlen; -+} -diff -urN linux.old/arch/mips/cfe/cfe_private.h linux.dev/arch/mips/cfe/cfe_private.h ---- linux.old/arch/mips/cfe/cfe_private.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/cfe/cfe_private.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,176 @@ -+/* -+ * Broadcom Common Firmware Environment (CFE) support -+ * -+ * Copyright 2000, 2001, 2002 -+ * Broadcom Corporation. All rights reserved. -+ * -+ * Copyright (C) 2006 Michael Buesch -+ * -+ * Original Authors: Mitch Lichtenberg, Chris Demetriou -+ * -+ * This software is furnished under license and may be used and copied only -+ * in accordance with the following terms and conditions. Subject to these -+ * conditions, you may download, copy, install, use, modify and distribute -+ * modified or unmodified copies of this software in source and/or binary -+ * form. No title or ownership is transferred hereby. -+ * -+ * 1) Any source code used, modified or distributed must reproduce and -+ * retain this copyright notice and list of conditions as they appear in -+ * the source file. -+ * -+ * 2) No right is granted to use any trade name, trademark, or logo of -+ * Broadcom Corporation. The "Broadcom Corporation" name may not be -+ * used to endorse or promote products derived from this software -+ * without the prior written permission of Broadcom Corporation. -+ * -+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR -+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE -+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE -+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef LINUX_CFE_PRIVATE_H_ -+#define LINUX_CFE_PRIVATE_H_ -+ -+#ifndef __ASSEMBLY__ -+ -+/* Seal indicating CFE's presence, passed to the kernel. */ -+#define CFE_EPTSEAL 0x43464531 -+ -+#define CFE_CMD_FW_GETINFO 0 -+#define CFE_CMD_FW_RESTART 1 -+#define CFE_CMD_FW_BOOT 2 -+#define CFE_CMD_FW_CPUCTL 3 -+#define CFE_CMD_FW_GETTIME 4 -+#define CFE_CMD_FW_MEMENUM 5 -+#define CFE_CMD_FW_FLUSHCACHE 6 -+ -+#define CFE_CMD_DEV_GETHANDLE 9 -+#define CFE_CMD_DEV_ENUM 10 -+#define CFE_CMD_DEV_OPEN 11 -+#define CFE_CMD_DEV_INPSTAT 12 -+#define CFE_CMD_DEV_READ 13 -+#define CFE_CMD_DEV_WRITE 14 -+#define CFE_CMD_DEV_IOCTL 15 -+#define CFE_CMD_DEV_CLOSE 16 -+#define CFE_CMD_DEV_GETINFO 17 -+ -+#define CFE_CMD_ENV_ENUM 20 -+#define CFE_CMD_ENV_GET 22 -+#define CFE_CMD_ENV_SET 23 -+#define CFE_CMD_ENV_DEL 24 -+ -+#define CFE_CMD_MAX 32 -+ -+#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ -+ -+typedef u64 cfe_uint_t; -+typedef s64 cfe_int_t; -+typedef s64 cfe_ptr_t; -+ -+/* Cast a pointer from native to CFE-API pointer and back */ -+#define CFE_TO_PTR(p) ((void *)(unsigned long)(p)) -+#define PTR_TO_CFE(p) ((cfe_ptr_t)(unsigned long)(p)) -+ -+struct cfe_iocb_buf { -+ cfe_uint_t offset; /* offset on device (bytes) */ -+ cfe_ptr_t ptr; /* pointer to a buffer */ -+ cfe_uint_t length; /* length of this buffer */ -+ cfe_uint_t retlen; /* returned length (for read ops) */ -+ union { -+ cfe_uint_t ioctlcmd; /* IOCTL command (used only for IOCTLs) */ -+ cfe_uint_t devflags; /* Returned device info flags */ -+ }; -+}; -+ -+struct cfe_iocb_inpstat { -+ cfe_uint_t status; /* 1 means input available */ -+}; -+ -+struct cfe_iocb_envbuf { -+ cfe_int_t index; /* 0-based enumeration index */ -+ cfe_ptr_t name; /* name string buffer */ -+ cfe_int_t name_len; /* size of name buffer */ -+ cfe_ptr_t val; /* value string buffer */ -+ cfe_int_t val_len; /* size of value string buffer */ -+}; -+ -+struct cfe_iocb_cpuctl { -+ cfe_uint_t number; /* cpu number to control */ -+ cfe_uint_t command; /* command to issue to CPU */ -+ cfe_uint_t start_addr; /* CPU start address */ -+ cfe_uint_t gp; /* starting GP value */ -+ cfe_uint_t sp; /* starting SP value */ -+ cfe_uint_t a1; /* starting A1 value */ -+}; -+ -+struct cfe_iocb_time { -+ cfe_int_t ticks; /* current time in ticks */ -+}; -+ -+struct cfe_iocb_exitstat { -+ cfe_int_t status; -+}; -+ -+struct cfe_iocb_meminfo { -+ cfe_int_t index; /* 0-based enumeration index */ -+ cfe_int_t type; /* type of memory block */ -+ cfe_uint_t addr; /* physical start address */ -+ cfe_uint_t size; /* block size */ -+}; -+ -+struct cfe_iocb_fwinfo { -+ cfe_int_t version; /* major, minor, eco version */ -+ cfe_int_t totalmem; /* total installed mem */ -+ cfe_int_t flags; /* various flags */ -+ cfe_int_t boardid; /* board ID */ -+ cfe_int_t bootarea_va; /* VA of boot area */ -+ cfe_int_t bootarea_pa; /* PA of boot area */ -+ cfe_int_t bootarea_size; /* size of boot area */ -+ cfe_int_t reserved1; -+ cfe_int_t reserved2; -+ cfe_int_t reserved3; -+}; -+ -+/* CFE I/O Control Block */ -+struct cfe_iocb { -+ cfe_uint_t fcode; /* IOCB function code */ -+ cfe_int_t status; /* return status */ -+ cfe_int_t handle; /* file/device handle */ -+ cfe_uint_t flags; /* flags for this IOCB */ -+ cfe_uint_t psize; /* size of parameter list */ -+ union { -+ struct cfe_iocb_buf buffer; /* buffer parameters */ -+ struct cfe_iocb_inpstat inpstat; /* input status parameters */ -+ struct cfe_iocb_envbuf envbuf; /* environment function parameters */ -+ struct cfe_iocb_cpuctl cpuctl; /* CPU control parameters */ -+ struct cfe_iocb_time time; /* timer parameters */ -+ struct cfe_iocb_meminfo meminfo; /* memory arena info parameters */ -+ struct cfe_iocb_fwinfo fwinfo; /* firmware information */ -+ struct cfe_iocb_exitstat exitstat; /* Exit Status */ -+ }; -+}; -+ -+ -+#include -+ -+void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1, -+ unsigned long fwarg2, unsigned long fwarg3); -+ -+#else /* __ASSEMBLY__ */ -+ -+ .macro cfe_early_init -+#ifdef CONFIG_CFE -+ jal cfe_setup -+#endif -+ .endm -+ -+#endif /* __ASSEMBLY__ */ -+#endif /* LINUX_CFE_PRIVATE_H_ */ -diff -urN linux.old/arch/mips/cfe/Makefile linux.dev/arch/mips/cfe/Makefile ---- linux.old/arch/mips/cfe/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/cfe/Makefile 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,5 @@ -+# -+# Makefile for the Broadcom Common Firmware Environment support -+# -+ -+obj-y += cfe.o -diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig ---- linux.old/arch/mips/Kconfig 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/arch/mips/Kconfig 2007-01-03 02:26:02.000000000 +0100 -@@ -4,6 +4,10 @@ - # Horrible source of confusion. Die, die, die ... - select EMBEDDED - -+config CFE -+ bool -+ # Common Firmware Environment -+ - mainmenu "Linux/MIPS Kernel Configuration" - - menu "Machine selection" -@@ -222,6 +226,22 @@ - Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and - Olivetti M700-10 workstations. - -+config BCM947XX -+ bool "Support for BCM947xx based boards" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_LITTLE_ENDIAN -+ select MIPS_CPU_SCACHE -+ select SSB -+ select SSB_DRIVER_MIPS -+ select SSB_DRIVER_EXTIF -+ select CFE -+ help -+ Support for BCM947xx based boards -+ - config LASAT - bool "LASAT Networks platforms" - select DMA_NONCOHERENT -diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c ---- linux.old/arch/mips/kernel/cpu-probe.c 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/arch/mips/kernel/cpu-probe.c 2007-01-03 02:26:02.000000000 +0100 -@@ -723,6 +723,28 @@ - } - - -+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) -+{ -+ decode_config1(c); -+ switch (c->processor_id & 0xff00) { -+ case PRID_IMP_BCM3302: -+ c->cputype = CPU_BCM3302; -+ c->isa_level = MIPS_CPU_ISA_M32R1; -+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | -+ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER; -+ break; -+ case PRID_IMP_BCM4710: -+ c->cputype = CPU_BCM4710; -+ c->isa_level = MIPS_CPU_ISA_M32R1; -+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | -+ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER; -+ break; -+ default: -+ c->cputype = CPU_UNKNOWN; -+ break; -+ } -+} -+ - __init void cpu_probe(void) - { - struct cpuinfo_mips *c = ¤t_cpu_data; -@@ -745,6 +767,9 @@ - case PRID_COMP_SIBYTE: - cpu_probe_sibyte(c); - break; -+ case PRID_COMP_BROADCOM: -+ cpu_probe_broadcom(c); -+ break; - case PRID_COMP_SANDCRAFT: - cpu_probe_sandcraft(c); - break; -diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c ---- linux.old/arch/mips/kernel/proc.c 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/arch/mips/kernel/proc.c 2007-01-03 02:26:02.000000000 +0100 -@@ -83,6 +83,8 @@ - [CPU_VR4181] = "NEC VR4181", - [CPU_VR4181A] = "NEC VR4181A", - [CPU_SR71000] = "Sandcraft SR71000", -+ [CPU_BCM3302] = "Broadcom BCM3302", -+ [CPU_BCM4710] = "Broadcom BCM4710", - [CPU_PR4450] = "Philips PR4450", - }; - -diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile ---- linux.old/arch/mips/Makefile 2007-01-03 02:25:09.000000000 +0100 -+++ linux.dev/arch/mips/Makefile 2007-01-03 02:26:02.000000000 +0100 -@@ -571,6 +571,18 @@ - load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 - - # -+# Broadcom BCM47XX boards -+# -+core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ -+cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx -+load-$(CONFIG_BCM947XX) := 0xffffffff80001000 -+ -+# -+# Common Firmware Environment -+# -+core-$(CONFIG_CFE) += arch/mips/cfe/ -+ -+# - # SNI RM200 PCI - # - core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/ -diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c ---- linux.old/arch/mips/mm/tlbex.c 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/arch/mips/mm/tlbex.c 2007-01-03 02:26:02.000000000 +0100 -@@ -880,6 +880,8 @@ - case CPU_4KSC: - case CPU_20KC: - case CPU_25KF: -+ case CPU_BCM3302: -+ case CPU_BCM4710: - tlbw(p); - break; - -diff -urN linux.old/drivers/Kconfig linux.dev/drivers/Kconfig ---- linux.old/drivers/Kconfig 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/drivers/Kconfig 2007-01-03 02:26:02.000000000 +0100 -@@ -56,6 +56,8 @@ - - source "drivers/hwmon/Kconfig" - -+source "drivers/ssb/Kconfig" -+ - source "drivers/mfd/Kconfig" - - source "drivers/media/Kconfig" -diff -urN linux.old/drivers/Makefile linux.dev/drivers/Makefile ---- linux.old/drivers/Makefile 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/drivers/Makefile 2007-01-03 02:26:02.000000000 +0100 -@@ -77,3 +77,4 @@ - obj-$(CONFIG_SUPERH) += sh/ - obj-$(CONFIG_GENERIC_TIME) += clocksource/ - obj-$(CONFIG_DMA_ENGINE) += dma/ -+obj-$(CONFIG_SSB) += ssb/ -diff -urN linux.old/drivers/ssb/core.c linux.dev/drivers/ssb/core.c ---- linux.old/drivers/ssb/core.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/core.c 2007-01-03 02:29:17.000000000 +0100 -@@ -0,0 +1,677 @@ -+#include "ssb_private.h" -+ -+#include -+#include -+#include -+#include -+ -+ -+MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); -+MODULE_LICENSE("GPL"); -+ -+ -+static LIST_HEAD(attach_queue); -+static LIST_HEAD(buses); -+static int nr_buses; -+static DEFINE_MUTEX(buses_mutex); -+ -+#define ssb_buses_lock() do { \ -+ if (!is_early_boot()) \ -+ mutex_lock(&buses_mutex); \ -+ } while (0) -+ -+#define ssb_buses_unlock() do { \ -+ if (!is_early_boot()) \ -+ mutex_unlock(&buses_mutex); \ -+ } while (0) -+ -+ -+static struct ssb_device * ssb_device_get(struct ssb_device *dev) -+{ -+ if (dev) -+ get_device(&dev->dev); -+ return dev; -+} -+ -+static void ssb_device_put(struct ssb_device *dev) -+{ -+ if (dev) -+ put_device(&dev->dev); -+} -+ -+static int ssb_device_resume(struct device *dev) -+{ -+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); -+ int err = 0; -+ -+ if (ssb_drv && ssb_drv->resume) -+ err = ssb_drv->resume(ssb_dev); -+ -+ return err; -+} -+ -+static int ssb_device_suspend(struct device *dev, pm_message_t state) -+{ -+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); -+ int err = 0; -+ -+ if (ssb_drv && ssb_drv->suspend) -+ err = ssb_drv->suspend(ssb_dev, state); -+ -+ return err; -+} -+ -+static void ssb_device_shutdown(struct device *dev) -+{ -+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); -+ -+ if (ssb_drv && ssb_drv->shutdown) -+ ssb_drv->shutdown(ssb_dev); -+} -+ -+static int ssb_device_remove(struct device *dev) -+{ -+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); -+ -+ if (ssb_drv && ssb_drv->remove) -+ ssb_drv->remove(ssb_dev); -+ ssb_device_put(ssb_dev); -+ -+ return 0; -+} -+ -+static int ssb_device_probe(struct device *dev) -+{ -+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); -+ int err = 0; -+ -+ ssb_device_get(ssb_dev); -+ if (ssb_drv && ssb_drv->probe) -+ err = ssb_drv->probe(ssb_dev, &ssb_dev->id); -+ if (err) -+ ssb_device_put(ssb_dev); -+ -+ return err; -+} -+ -+static int ssb_match_devid(const struct ssb_device_id *tabid, -+ const struct ssb_device_id *devid) -+{ -+ if ((tabid->vendor != devid->vendor) && -+ tabid->vendor != SSB_ANY_VENDOR) -+ return 0; -+ if ((tabid->coreid != devid->coreid) && -+ tabid->coreid != SSB_ANY_ID) -+ return 0; -+ if ((tabid->revision != devid->revision) && -+ tabid->revision != SSB_ANY_REV) -+ return 0; -+ return 1; -+} -+ -+static int ssb_bus_match(struct device *dev, struct device_driver *drv) -+{ -+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); -+ const struct ssb_device_id *id; -+ -+ for (id = ssb_drv->id_table; -+ id->vendor || id->coreid || id->revision; -+ id++) { -+ if (ssb_match_devid(id, &ssb_dev->id)) -+ return 1; /* found */ -+ } -+ -+ return 0; -+} -+ -+struct bus_type ssb_bustype = { -+ .name = NULL, /* Intentionally NULL to indicate early boot */ -+ .match = ssb_bus_match, -+ .probe = ssb_device_probe, -+ .remove = ssb_device_remove, -+ .shutdown = ssb_device_shutdown, -+ .suspend = ssb_device_suspend, -+ .resume = ssb_device_resume, -+}; -+ -+#define is_early_boot() (ssb_bustype.name == NULL) -+ -+void ssb_bus_unregister(struct ssb_bus *bus) -+{ -+ struct ssb_device *dev; -+ int i; -+ -+ ssb_buses_lock(); -+ for (i = bus->nr_devices - 1; i >= 0; i--) { -+ dev = &(bus->devices[i]); -+ device_unregister(&dev->dev); -+ } -+ list_del(&bus->list); -+ ssb_buses_unlock(); -+ -+//TODO chipcommon exit -+ /* Free MMIO */ -+ bus->mapped_device = NULL; -+ if (bus->bustype == SSB_BUSTYPE_SSB) -+ iounmap(bus->mmio); -+ else -+ pci_iounmap(bus->host_pci, bus->mmio); -+ bus->mmio = NULL; -+} -+EXPORT_SYMBOL(ssb_bus_unregister); -+ -+static void ssb_release_dev(struct device *dev) -+{ -+ /* Nothing */ -+} -+ -+/* Needs ssb_buses_lock() */ -+static int ssb_attach_queued_buses(void) -+{ -+ struct ssb_bus *bus, *n; -+ struct ssb_device *dev; -+ int i, err; -+ -+ list_for_each_entry_safe(bus, n, &attach_queue, list) { -+ for (i = 0; i < bus->nr_devices; i++) { -+ dev = &(bus->devices[i]); -+ -+ dev->dev.release = ssb_release_dev; -+ err = device_register(&dev->dev); -+ if (err) { -+ ssb_printk("Could not register %s\n", -+ dev->dev.bus_id); -+ } -+ } -+ list_move_tail(&bus->list, &buses); -+ } -+ return 0; -+} -+ -+static void ssb_get_boardtype(struct ssb_bus *bus) -+{ -+ if (bus->bustype != SSB_BUSTYPE_PCI) { -+ /* Must set board_vendor, board_type and board_rev -+ * before calling ssb_bus_*_register() */ -+ assert(bus->board_vendor && bus->board_type); -+ return; -+ } -+ ssb_pci_get_boardtype(bus); -+} -+ -+static int ssb_bus_register(struct ssb_bus *bus, -+ unsigned long baseaddr) -+{ -+ int err; -+ -+ ssb_printk("Sonics Silicon Backplane found at: "); -+ if (bus->bustype == SSB_BUSTYPE_PCI) -+ ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id); -+ else -+ ssb_printk("Address 0x%08lX\n", baseaddr); -+ -+ spin_lock_init(&bus->bar_lock); -+ INIT_LIST_HEAD(&bus->list); -+ -+ ssb_get_boardtype(bus); -+ /* Powerup the bus */ -+ err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); -+ if (err) -+ goto out; -+ /* Scan for devices (cores) */ -+ err = ssb_bus_scan(bus, baseaddr); -+ if (err) -+ goto err_disable_xtal; -+ if (bus->bustype == SSB_BUSTYPE_PCI) { -+ err = ssb_pci_sprom_get(bus); -+ if (err) -+ goto err_unmap; -+ } -+ /* Initialize basic system devices (if available) */ -+ ssb_chipcommon_init(&bus->chipco); -+ ssb_mipscore_init(&bus->mipscore); -+ //TODO also register drivers for the basic system stuff later? -+ // I think the only purpose would be to show them in sysfs. -+ -+ ssb_buses_lock(); -+ bus->busnumber = nr_buses; -+ /* Queue it for attach */ -+ list_add_tail(&bus->list, &attach_queue); -+ if (!is_early_boot()) { -+ /* This is not early boot, so we must attach the bus now */ -+ err = ssb_attach_queued_buses(); -+ if (err) -+ goto err_dequeue; -+ } -+ nr_buses++; -+ ssb_buses_unlock(); -+ -+out: -+ return err; -+ -+err_dequeue: -+ list_del(&bus->list); -+ ssb_buses_unlock(); -+err_unmap: -+ bus->mapped_device = NULL; -+ if (bus->bustype == SSB_BUSTYPE_SSB) -+ iounmap(bus->mmio); -+ else -+ pci_iounmap(bus->host_pci, bus->mmio); -+ bus->mmio = NULL; -+err_disable_xtal: -+ ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); -+ goto out; -+} -+ -+int ssb_bus_pcibus_register(struct ssb_bus *bus, -+ struct pci_dev *host_pci) -+{ -+ int err; -+ -+ bus->bustype = SSB_BUSTYPE_PCI; -+ bus->host_pci = host_pci; -+ -+ err = ssb_bus_register(bus, 0); -+ -+ return err; -+} -+EXPORT_SYMBOL(ssb_bus_pcibus_register); -+ -+int ssb_bus_ssbbus_register(struct ssb_bus *bus, -+ unsigned long baseaddr, -+ void (*fill_sprom)(struct ssb_sprom *sprom)) -+{ -+ int err; -+ -+ bus->bustype = SSB_BUSTYPE_SSB; -+ fill_sprom(&bus->sprom); -+ err = ssb_bus_register(bus, baseaddr); -+ -+ return err; -+} -+ -+static inline -+int do_select_core(struct ssb_bus *bus, -+ struct ssb_device *dev, -+ u16 *offset) -+{ -+ int err = 0; -+ -+ switch (bus->bustype) { -+ case SSB_BUSTYPE_PCI: -+ if (unlikely(dev != bus->mapped_device)) -+ err = ssb_pci_switch_core(bus, dev); -+ break; -+ case SSB_BUSTYPE_SSB: -+ *offset += dev->core_index * SSB_CORE_SIZE; -+ break; -+ } -+ -+ return err; -+} -+ -+u16 ssb_read16(struct ssb_device *dev, u16 offset) -+{ -+ struct ssb_bus *bus = dev->bus; -+ -+ if (unlikely(do_select_core(bus, dev, &offset))) -+ return 0xFFFF; -+ return ssb_raw_read16(bus, offset); -+} -+EXPORT_SYMBOL(ssb_read16); -+ -+u32 ssb_read32(struct ssb_device *dev, u16 offset) -+{ -+ struct ssb_bus *bus = dev->bus; -+ -+ if (unlikely(do_select_core(bus, dev, &offset))) -+ return 0xFFFFFFFF; -+ return ssb_raw_read32(bus, offset); -+} -+EXPORT_SYMBOL(ssb_read32); -+ -+void ssb_write16(struct ssb_device *dev, u16 offset, u16 value) -+{ -+ struct ssb_bus *bus = dev->bus; -+ -+ if (unlikely(do_select_core(bus, dev, &offset))) -+ return; -+ ssb_raw_write16(bus, offset, value); -+} -+EXPORT_SYMBOL(ssb_write16); -+ -+void ssb_write32(struct ssb_device *dev, u16 offset, u32 value) -+{ -+ struct ssb_bus *bus = dev->bus; -+ -+ if (unlikely(do_select_core(bus, dev, &offset))) -+ return; -+ ssb_raw_write32(bus, offset, value); -+} -+EXPORT_SYMBOL(ssb_write32); -+ -+int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) -+{ -+ drv->drv.name = drv->name; -+ drv->drv.bus = &ssb_bustype; -+ drv->drv.owner = owner; -+ -+ return driver_register(&drv->drv); -+} -+EXPORT_SYMBOL(__ssb_driver_register); -+ -+void ssb_driver_unregister(struct ssb_driver *drv) -+{ -+ driver_unregister(&drv->drv); -+} -+EXPORT_SYMBOL(ssb_driver_unregister); -+ -+void ssb_set_devtypedata(struct ssb_device *dev, void *data) -+{ -+ struct ssb_bus *bus = dev->bus; -+ struct ssb_device *ent; -+ int i; -+ -+ for (i = 0; i < bus->nr_devices; i++) { -+ ent = &(bus->devices[i]); -+ if (ent->id.vendor != dev->id.vendor) -+ continue; -+ if (ent->id.coreid != dev->id.coreid) -+ continue; -+ -+ ent->devtypedata = data; -+ } -+} -+EXPORT_SYMBOL(ssb_set_devtypedata); -+ -+static u32 clkfactor_f6_resolve(u32 v) -+{ -+ /* map the magic values */ -+ switch (v) { -+ case SSB_CHIPCO_CLK_F6_2: -+ return 2; -+ case SSB_CHIPCO_CLK_F6_3: -+ return 3; -+ case SSB_CHIPCO_CLK_F6_4: -+ return 4; -+ case SSB_CHIPCO_CLK_F6_5: -+ return 5; -+ case SSB_CHIPCO_CLK_F6_6: -+ return 6; -+ case SSB_CHIPCO_CLK_F6_7: -+ return 7; -+ } -+ return 0; -+} -+ -+/* Calculate the speed the backplane would run at a given set of clockcontrol values */ -+u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) -+{ -+ u32 n1, n2, clock, m1, m2, m3, mc; -+ -+ n1 = (n & SSB_CHIPCO_CLK_N1); -+ n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); -+ -+ switch (plltype) { -+ case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ -+ if (m & SSB_CHIPCO_CLK_T6_MMASK) -+ return SSB_CHIPCO_CLK_T6_M0; -+ return SSB_CHIPCO_CLK_T6_M1; -+ case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ -+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ -+ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ -+ case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ -+ n1 = clkfactor_f6_resolve(n1); -+ n2 += SSB_CHIPCO_CLK_F5_BIAS; -+ break; -+ case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ -+ n1 += SSB_CHIPCO_CLK_T2_BIAS; -+ n2 += SSB_CHIPCO_CLK_T2_BIAS; -+ assert((n1 >= 2) && (n1 <= 7)); -+ assert((n2 >= 5) && (n2 <= 23)); -+ break; -+ case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ -+ return 100000000; -+ default: -+ assert(0); -+ } -+ -+ switch (plltype) { -+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ -+ case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ -+ clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; -+ break; -+ default: -+ clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; -+ } -+ if (!clock) -+ return 0; -+ -+ m1 = (m & SSB_CHIPCO_CLK_M1); -+ m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); -+ m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); -+ mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); -+ -+ switch (plltype) { -+ case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ -+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ -+ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ -+ case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ -+ m1 = clkfactor_f6_resolve(m1); -+ if ((plltype == SSB_PLLTYPE_1) || -+ (plltype == SSB_PLLTYPE_3)) -+ m2 += SSB_CHIPCO_CLK_F5_BIAS; -+ else -+ m2 = clkfactor_f6_resolve(m2); -+ m3 = clkfactor_f6_resolve(m3); -+ -+ switch (mc) { -+ case SSB_CHIPCO_CLK_MC_BYPASS: -+ return clock; -+ case SSB_CHIPCO_CLK_MC_M1: -+ return (clock / m1); -+ case SSB_CHIPCO_CLK_MC_M1M2: -+ return (clock / (m1 * m2)); -+ case SSB_CHIPCO_CLK_MC_M1M2M3: -+ return (clock / (m1 * m2 * m3)); -+ case SSB_CHIPCO_CLK_MC_M1M3: -+ return (clock / (m1 * m3)); -+ } -+ return 0; -+ case SSB_PLLTYPE_2: -+ m1 += SSB_CHIPCO_CLK_T2_BIAS; -+ m2 += SSB_CHIPCO_CLK_T2M2_BIAS; -+ m3 += SSB_CHIPCO_CLK_T2_BIAS; -+ assert((m1 >= 2) && (m1 <= 7)); -+ assert((m2 >= 3) && (m2 <= 10)); -+ assert((m3 >= 2) && (m3 <= 7)); -+ -+ if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) -+ clock /= m1; -+ if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) -+ clock /= m2; -+ if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) -+ clock /= m3; -+ return clock; -+ default: -+ assert(0); -+ } -+ return 0; -+} -+ -+/* Get the current speed the backplane is running at */ -+u32 ssb_clockspeed(struct ssb_bus *bus) -+{ -+ u32 rate; -+ u32 plltype; -+ u32 clkctl_n, clkctl_m; -+ -+ //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb -+ -+ if (bus->chipco.dev) { -+ ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, -+ &clkctl_n, &clkctl_m); -+ } else -+ return 0; -+ -+ if (bus->chip_id == 0x5365) { -+ rate = 100000000; -+ } else { -+ rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); -+ if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ -+ rate /= 2; -+ } -+ -+ return rate; -+} -+ -+int ssb_device_is_enabled(struct ssb_device *dev) -+{ -+ u32 val; -+ -+ val = ssb_read32(dev, SSB_TMSLOW); -+ val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT; -+ -+ return (val == SSB_TMSLOW_CLOCK); -+} -+EXPORT_SYMBOL(ssb_device_is_enabled); -+ -+void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) -+{ -+ u32 val; -+ -+ ssb_device_disable(dev, core_specific_flags); -+ ssb_write32(dev, SSB_TMSLOW, -+ SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | -+ SSB_TMSLOW_FGC | core_specific_flags); -+ /* flush */ -+ ssb_read32(dev, SSB_TMSLOW); -+ udelay(1); -+ -+ /* Clear SERR if set. This is a hw bug workaround. */ -+ if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) -+ ssb_write32(dev, SSB_TMSHIGH, 0); -+ -+ val = ssb_read32(dev, SSB_IMSTATE); -+ if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { -+ val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); -+ ssb_write32(dev, SSB_IMSTATE, val); -+ } -+ -+ ssb_write32(dev, SSB_TMSLOW, -+ SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | -+ core_specific_flags); -+ /* flush */ -+ ssb_read32(dev, SSB_TMSLOW); -+ udelay(1); -+ -+ ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | -+ core_specific_flags); -+ /* flush */ -+ ssb_read32(dev, SSB_TMSLOW); -+ udelay(1); -+} -+EXPORT_SYMBOL(ssb_device_enable); -+ -+static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, -+ int timeout, int set) -+{ -+ int i; -+ u32 val; -+ -+ for (i = 0; i < timeout; i++) { -+ val = ssb_read32(dev, reg); -+ if (set) { -+ if (val & bitmask) -+ return 0; -+ } else { -+ if (!(val & bitmask)) -+ return 0; -+ } -+ udelay(10); -+ } -+ printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " -+ "register %04X to %s.\n", -+ bitmask, reg, (set ? "set" : "clear")); -+ -+ return -ETIMEDOUT; -+} -+ -+void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) -+{ -+ if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) -+ return; -+ -+ ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK); -+ ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1); -+ ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); -+ ssb_write32(dev, SSB_TMSLOW, -+ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | -+ SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET | -+ core_specific_flags); -+ /* flush */ -+ ssb_read32(dev, SSB_TMSLOW); -+ udelay(1); -+ -+ ssb_write32(dev, SSB_TMSLOW, -+ SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET | -+ core_specific_flags); -+ /* flush */ -+ ssb_read32(dev, SSB_TMSLOW); -+ udelay(1); -+} -+EXPORT_SYMBOL(ssb_device_disable); -+ -+int __ssb_printk(const char *fmt, ...) -+{ -+ va_list args; -+ int res; -+ -+ va_start(args, fmt); -+#ifdef CONFIG_CFE -+ if (is_early_boot() && cfe_present()) { -+ res = cfe_vprintk(fmt, args); -+ } else -+#endif -+ { -+ printk(KERN_INFO); -+ res = vprintk(fmt, args); -+ } -+ va_end(args); -+ -+ return res; -+} -+ -+ -+static int ssb_modinit(void) -+{ -+ int err; -+ -+ ssb_bustype.name = "ssb"; -+ err = bus_register(&ssb_bustype); -+ if (err) -+ return err; -+ -+ /* Maybe we already registered some buses at early boot. -+ * Check for this and attach them -+ */ -+ ssb_buses_lock(); -+ err = ssb_attach_queued_buses(); -+ ssb_buses_unlock(); -+ -+ return err; -+} -+subsys_initcall(ssb_modinit); -+ -+static void __exit ssb_modexit(void) -+{ -+ bus_unregister(&ssb_bustype); -+} -+module_exit(ssb_modexit) -diff -urN linux.old/drivers/ssb/driver_chipcommon/chipcommon.c linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c ---- linux.old/drivers/ssb/driver_chipcommon/chipcommon.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c 2007-01-03 02:29:17.000000000 +0100 -@@ -0,0 +1,384 @@ -+#include -+#include -+#include -+ -+#include "../ssb_private.h" -+ -+ -+/* Clock sources */ -+enum { -+ /* PCI clock */ -+ SSB_CHIPCO_CLKSRC_PCI, -+ /* Crystal slow clock oscillator */ -+ SSB_CHIPCO_CLKSRC_XTALOS, -+ /* Low power oscillator */ -+ SSB_CHIPCO_CLKSRC_LOPWROS, -+}; -+ -+ -+static inline u32 chipco_read32(struct ssb_chipcommon *cc, -+ u16 offset) -+{ -+ return ssb_read32(cc->dev, offset); -+} -+ -+static inline void chipco_write32(struct ssb_chipcommon *cc, -+ u16 offset, -+ u32 value) -+{ -+ ssb_write32(cc->dev, offset, value); -+} -+ -+void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, -+ enum ssb_clkmode mode) -+{ -+ struct ssb_device *ccdev = cc->dev; -+ struct ssb_bus *bus; -+ u32 tmp; -+ -+ if (!ccdev) -+ return; -+ bus = ccdev->bus; -+ /* chipcommon cores prior to rev6 don't support dynamic clock control */ -+ if (ccdev->id.revision < 6) -+ return; -+ /* chipcommon cores rev10 are a whole new ball game */ -+ if (ccdev->id.revision >= 10) -+ return; -+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) -+ return; -+ -+ switch (mode) { -+ case SSB_CLKMODE_SLOW: -+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); -+ tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; -+ chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); -+ break; -+ case SSB_CLKMODE_FAST: -+ ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ -+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); -+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; -+ tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; -+ chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); -+ break; -+ case SSB_CLKMODE_DYNAMIC: -+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); -+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; -+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; -+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; -+ if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) -+ tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; -+ chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); -+ -+ /* for dynamic control, we have to release our xtal_pu "force on" */ -+ if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) -+ ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); -+ break; -+ default: -+ assert(0); -+ } -+} -+EXPORT_SYMBOL(ssb_chipco_set_clockmode); -+ -+/* Get the Slow Clock Source */ -+static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) -+{ -+ struct ssb_bus *bus = cc->dev->bus; -+ u32 tmp = 0; -+ -+ if (cc->dev->id.revision < 6) { -+ if (bus->bustype == SSB_BUSTYPE_SSB /*TODO || -+ bus->bustype == SSB_BUSTYPE_PCMCIA*/) -+ return SSB_CHIPCO_CLKSRC_XTALOS; -+ if (bus->bustype == SSB_BUSTYPE_PCI) { -+ pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); -+ if (tmp & 0x10) -+ return SSB_CHIPCO_CLKSRC_PCI; -+ return SSB_CHIPCO_CLKSRC_XTALOS; -+ } -+ } -+ if (cc->dev->id.revision < 10) { -+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); -+ tmp &= 0x7; -+ if (tmp == 0) -+ return SSB_CHIPCO_CLKSRC_LOPWROS; -+ if (tmp == 1) -+ return SSB_CHIPCO_CLKSRC_XTALOS; -+ if (tmp == 2) -+ return SSB_CHIPCO_CLKSRC_PCI; -+ } -+ -+ return SSB_CHIPCO_CLKSRC_XTALOS; -+} -+ -+/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ -+static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) -+{ -+ int limit; -+ int clocksrc; -+ int divisor; -+ u32 tmp; -+ -+ clocksrc = chipco_pctl_get_slowclksrc(cc); -+ if (cc->dev->id.revision < 6) { -+ switch (clocksrc) { -+ case SSB_CHIPCO_CLKSRC_PCI: -+ divisor = 64; -+ break; -+ case SSB_CHIPCO_CLKSRC_XTALOS: -+ divisor = 32; -+ break; -+ default: -+ assert(0); -+ divisor = 1; -+ } -+ } else if (cc->dev->id.revision < 10) { -+ switch (clocksrc) { -+ case SSB_CHIPCO_CLKSRC_LOPWROS: -+ divisor = 1; -+ break; -+ case SSB_CHIPCO_CLKSRC_XTALOS: -+ case SSB_CHIPCO_CLKSRC_PCI: -+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); -+ divisor = (tmp >> 16) + 1; -+ divisor *= 4; -+ break; -+ default: -+ assert(0); -+ divisor = 1; -+ } -+ } else { -+ tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); -+ divisor = (tmp >> 16) + 1; -+ divisor *= 4; -+ } -+ -+ switch (clocksrc) { -+ case SSB_CHIPCO_CLKSRC_LOPWROS: -+ if (get_max) -+ limit = 43000; -+ else -+ limit = 25000; -+ break; -+ case SSB_CHIPCO_CLKSRC_XTALOS: -+ if (get_max) -+ limit = 20200000; -+ else -+ limit = 19800000; -+ break; -+ case SSB_CHIPCO_CLKSRC_PCI: -+ if (get_max) -+ limit = 34000000; -+ else -+ limit = 25000000; -+ break; -+ default: -+ assert(0); -+ limit = 0; -+ } -+ limit /= divisor; -+ -+ return limit; -+} -+ -+static void chipco_powercontrol_init(struct ssb_chipcommon *cc) -+{ -+ struct ssb_bus *bus = cc->dev->bus; -+ -+ if (bus->chip_id == 0x4321) { -+ if (bus->chip_rev == 0) -+ chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); -+ else if (bus->chip_rev == 1) -+ chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); -+ } -+ -+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) -+ return; -+ -+ if (cc->dev->id.revision >= 10) { -+ /* Set Idle Power clock rate to 1Mhz */ -+ chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, -+ (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & -+ 0x0000FFFF) | 0x00040000); -+ } else { -+ int maxfreq; -+ -+ maxfreq = chipco_pctl_clockfreqlimit(cc, 1); -+ chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, -+ (maxfreq * 150 + 999999) / 1000000); -+ chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, -+ (maxfreq * 15 + 999999) / 1000000); -+ } -+} -+ -+static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) -+{ -+ struct ssb_bus *bus = cc->dev->bus; -+ int minfreq; -+ unsigned int tmp; -+ u32 pll_on_delay; -+ -+ if (bus->bustype != SSB_BUSTYPE_PCI) -+ return; -+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) -+ return; -+ -+ minfreq = chipco_pctl_clockfreqlimit(cc, 0); -+ pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); -+ tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; -+ assert((tmp & ~0xFFFF) == 0); -+ -+ cc->fast_pwrup_delay = tmp; -+} -+ -+void ssb_chipcommon_init(struct ssb_chipcommon *cc) -+{ -+ if (!cc->dev) -+ return; /* We don't have a ChipCommon */ -+ ssb_dprintk("Initializing Chipcommon...\n"); -+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); -+ chipco_powercontrol_init(cc); -+ calc_fast_powerup_delay(cc); -+} -+ -+void ssb_chipcommon_exit(struct ssb_chipcommon *cc) -+{ -+ //TODO -+} -+ -+void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, -+ u32 *plltype, u32 *n, u32 *m) -+{ -+ *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); -+ *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); -+ switch (*plltype) { -+ case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ -+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); -+ break; -+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ -+ if (cc->dev->bus->chip_id != 0x5365) { -+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); -+ break; -+ } -+ /* Fallthough */ -+ default: -+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); -+ } -+} -+ -+void ssb_chipco_timing_init(struct ssb_chipcommon *cc, -+ unsigned long ns) -+{ -+ struct ssb_device *dev = cc->dev; -+ struct ssb_bus *bus = dev->bus; -+ u32 tmp; -+ -+ /* set register for external IO to control LED. */ -+ chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); -+ tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ -+ tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ -+ tmp |= ceildiv(240, ns); /* Waitcount-0 = 240ns */ -+ chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ -+ -+ /* Set timing for the flash */ -+ tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ -+ tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ -+ tmp |= ceildiv(120, ns); /* Waitcount-0 = 120nS */ -+ if ((bus->chip_id == 0x5365) || -+ (dev->id.revision < 9)) -+ chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); -+ if ((bus->chip_id == 0x5365) || -+ (dev->id.revision < 9) || -+ ((bus->chip_id == 0x5350) && (bus->chip_rev == 0))) -+ chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); -+ -+ if (bus->chip_id == 0x5350) { -+ /* Enable EXTIF */ -+ tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ -+ tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ -+ tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ -+ tmp |= ceildiv(120, ns); /* Waitcount-0 = 120ns */ -+ chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ -+ } -+} -+ -+ -+#ifdef CONFIG_SSB_SERIAL -+int ssb_chipco_serial_init(struct ssb_chipcommon *cc, -+ struct ssb_serial_port *ports) -+{ -+ struct ssb_bus *bus = cc->dev->bus; -+ int nr_ports = 0; -+ u32 plltype; -+ unsigned int irq; -+ u32 baud_base, div; -+ u32 i, n; -+ -+ plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); -+ irq = ssb_mips_irq(cc->dev); -+ -+ if (plltype == SSB_PLLTYPE_1) { -+ /* PLL clock */ -+ baud_base = ssb_calc_clock_rate(plltype, -+ chipco_read32(cc, SSB_CHIPCO_CLOCK_N), -+ chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); -+ div = 1; -+ } else { -+ if (cc->dev->id.revision >= 11) { -+ /* Fixed ALP clock */ -+ baud_base = 20000000; -+ div = 1; -+ /* Set the override bit so we don't divide it */ -+ chipco_write32(cc, SSB_CHIPCO_CORECTL, -+ SSB_CHIPCO_CORECTL_UARTCLK0); -+ } else if (cc->dev->id.revision >= 3) { -+ /* Internal backplane clock */ -+ baud_base = ssb_clockspeed(bus); -+ div = 2; /* Minimum divisor */ -+ chipco_write32(cc, SSB_CHIPCO_CLKDIV, -+ (chipco_read32(cc, SSB_CHIPCO_CLKDIV) -+ & ~SSB_CHIPCO_CLKDIV_UART) | div); -+ } else { -+ /* Fixed internal backplane clock */ -+ baud_base = 88000000; -+ div = 48; -+ } -+ -+ /* Clock source depends on strapping if UartClkOverride is unset */ -+ if ((cc->dev->id.revision > 0) && -+ !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { -+ if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == -+ SSB_CHIPCO_CAP_UARTCLK_INT) { -+ /* Internal divided backplane clock */ -+ baud_base /= div; -+ } else { -+ /* Assume external clock of 1.8432 MHz */ -+ baud_base = 1843200; -+ } -+ } -+ } -+ -+ /* Determine the registers of the UARTs */ -+ n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); -+ for (i = 0; i < n; i++) { -+ void __iomem *cc_mmio; -+ void __iomem *uart_regs; -+ -+ cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); -+ uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; -+ /* Offset changed at after rev 0 */ -+ if (cc->dev->id.revision == 0) -+ uart_regs += (i * 8); -+ else -+ uart_regs += (i * 256); -+ -+ nr_ports++; -+ ports[i].regs = uart_regs; -+ ports[i].irq = irq; -+ ports[i].baud_base = baud_base; -+ ports[i].reg_shift = 0; -+ } -+ -+ return nr_ports; -+} -+#endif /* CONFIG_SSB_SERIAL */ -diff -urN linux.old/drivers/ssb/driver_chipcommon/Makefile linux.dev/drivers/ssb/driver_chipcommon/Makefile ---- linux.old/drivers/ssb/driver_chipcommon/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/driver_chipcommon/Makefile 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1 @@ -+obj-y += chipcommon.o -diff -urN linux.old/drivers/ssb/driver_mips/Makefile linux.dev/drivers/ssb/driver_mips/Makefile ---- linux.old/drivers/ssb/driver_mips/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/driver_mips/Makefile 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1 @@ -+obj-y += mips.o -diff -urN linux.old/drivers/ssb/driver_mips/mips.c linux.dev/drivers/ssb/driver_mips/mips.c ---- linux.old/drivers/ssb/driver_mips/mips.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/driver_mips/mips.c 2007-01-03 02:29:17.000000000 +0100 -@@ -0,0 +1,246 @@ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "../ssb_private.h" -+ -+ -+static inline u32 mips_read32(struct ssb_mipscore *mcore, -+ u16 offset) -+{ -+ return ssb_read32(mcore->dev, offset); -+} -+ -+static inline void mips_write32(struct ssb_mipscore *mcore, -+ u16 offset, -+ u32 value) -+{ -+ ssb_write32(mcore->dev, offset, value); -+} -+ -+static const u32 ipsflag_irq_mask[] = { -+ 0, -+ SSB_IPSFLAG_IRQ1, -+ SSB_IPSFLAG_IRQ2, -+ SSB_IPSFLAG_IRQ3, -+ SSB_IPSFLAG_IRQ4, -+}; -+ -+static const u32 ipsflag_irq_shift[] = { -+ 0, -+ SSB_IPSFLAG_IRQ1_SHIFT, -+ SSB_IPSFLAG_IRQ2_SHIFT, -+ SSB_IPSFLAG_IRQ3_SHIFT, -+ SSB_IPSFLAG_IRQ4_SHIFT, -+}; -+ -+static inline u32 ssb_irqflag(struct ssb_device *dev) -+{ -+ return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG; -+} -+ -+/* Get the MIPS IRQ assignment for a specified device. -+ * If unassigned, 0 is returned. -+ */ -+unsigned int ssb_mips_irq(struct ssb_device *dev) -+{ -+ struct ssb_bus *bus = dev->bus; -+ u32 irqflag; -+ u32 ipsflag; -+ u32 tmp; -+ unsigned int irq; -+ -+ irqflag = ssb_irqflag(dev); -+ ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG); -+ for (irq = 1; irq <= 4; irq++) { -+ tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]); -+ if (tmp == irqflag) -+ break; -+ } -+ if (irq == 5) -+ irq = 0; -+ -+ return irq; -+} -+ -+static void clear_irq(struct ssb_bus *bus, unsigned int irq) -+{ -+ struct ssb_device *dev = bus->mipscore.dev; -+ -+ /* Clear the IRQ in the MIPScore backplane registers */ -+ if (irq == 0) { -+ ssb_write32(dev, SSB_INTVEC, 0); -+ } else { -+ ssb_write32(dev, SSB_IPSFLAG, -+ ssb_read32(dev, SSB_IPSFLAG) | -+ ipsflag_irq_mask[irq]); -+ } -+} -+ -+static void set_irq(struct ssb_device *dev, unsigned int irq) -+{ -+ unsigned int oldirq = ssb_mips_irq(dev); -+ struct ssb_bus *bus = dev->bus; -+ struct ssb_device *mdev = bus->mipscore.dev; -+ u32 irqflag = ssb_irqflag(dev); -+ -+ dev->irq = irq + 2; -+ -+ ssb_dprintk("set_irq: core 0x%04x, irq %d => %d\n", dev->id.coreid, oldirq, irq); -+ /* clear the old irq */ -+ if (oldirq == 0) -+ ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))); -+ else -+ clear_irq(bus, oldirq); -+ -+ /* assign the new one */ -+ if (irq == 0) -+ ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))); -+ -+ irqflag <<= ipsflag_irq_shift[irq]; -+ irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]); -+ ssb_write32(mdev, SSB_IPSFLAG, irqflag); -+} -+ -+/* XXX: leave here or move into separate extif driver? */ -+static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports) -+{ -+ -+} -+ -+ -+static void ssb_mips_serial_init(struct ssb_mipscore *mcore) -+{ -+ struct ssb_bus *bus = mcore->dev->bus; -+ -+ //TODO if (EXTIF available -+#if 0 -+ extifregs_t *eir = (extifregs_t *) regs; -+ sbconfig_t *sb; -+ -+ /* Determine external UART register base */ -+ sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF); -+ base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1))); -+ -+ /* Determine IRQ */ -+ irq = sb_irq(sbh); -+ -+ /* Disable GPIO interrupt initially */ -+ W_REG(&eir->gpiointpolarity, 0); -+ W_REG(&eir->gpiointmask, 0); -+ -+ /* Search for external UARTs */ -+ n = 2; -+ for (i = 0; i < 2; i++) { -+ regs = (void *) REG_MAP(base + (i * 8), 8); -+ if (BCMINIT(serial_exists)(regs)) { -+ /* Set GPIO 1 to be the external UART IRQ */ -+ W_REG(&eir->gpiointmask, 2); -+ if (add) -+ add(regs, irq, 13500000, 0); -+ } -+ } -+ -+ /* Add internal UART if enabled */ -+ if (R_REG(&eir->corecontrol) & CC_UE) -+ if (add) -+ add((void *) &eir->uartdata, irq, sb_clock(sbh), 2); -+ -+#endif -+ if (bus->extif.dev) -+ mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports); -+ else if (bus->chipco.dev) -+ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports); -+ else -+ mcore->nr_serial_ports = 0; -+} -+ -+static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) -+{ -+ struct ssb_bus *bus = mcore->dev->bus; -+ -+ if (bus->chipco.dev) { -+ mcore->flash_window = 0x1c000000; -+ mcore->flash_window_size = 0x800000; -+ } else { -+ mcore->flash_window = 0x1fc00000; -+ mcore->flash_window_size = 0x400000; -+ } -+} -+ -+ -+static void ssb_cpu_clock(struct ssb_mipscore *mcore) -+{ -+} -+ -+void ssb_mipscore_init(struct ssb_mipscore *mcore) -+{ -+ struct ssb_bus *bus = mcore->dev->bus; -+ struct ssb_device *dev; -+ unsigned long hz, ns; -+ unsigned int irq, i; -+ -+ if (!mcore->dev) -+ return; /* We don't have a MIPS core */ -+ -+ ssb_dprintk("Initializing MIPS core...\n"); -+ -+ hz = ssb_clockspeed(bus); -+ if (!hz) -+ hz = 100000000; -+ ns = 1000000000 / hz; -+ -+//TODO -+#if 0 -+ if (have EXTIF) { -+ /* Initialize extif so we can get to the LEDs and external UART */ -+ W_REG(&eir->prog_config, CF_EN); -+ -+ /* Set timing for the flash */ -+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */ -+ tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */ -+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */ -+ W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */ -+ -+ /* Set programmable interface timing for external uart */ -+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */ -+ tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */ -+ tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */ -+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */ -+ W_REG(&eir->prog_waitcount, tmp); -+ } -+ else... chipcommon -+#endif -+ if (bus->chipco.dev) -+ ssb_chipco_timing_init(&bus->chipco, ns); -+ -+ /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */ -+ for (irq = 2, i = 0; i < bus->nr_devices; i++) { -+ dev = &(bus->devices[i]); -+ dev->irq = ssb_mips_irq(dev) + 2; -+ switch(dev->id.coreid) { -+ case SSB_DEV_USB11_HOST: -+ /* shouldn't need a separate irq line for non-4710, most of them have a proper -+ * external usb controller on the pci */ -+ if ((bus->chip_id == 0x4710) && (irq <= 4)) { -+ set_irq(dev, irq++); -+ break; -+ } -+ case SSB_DEV_PCI: -+ case SSB_DEV_ETHERNET: -+ case SSB_DEV_80211: -+ case SSB_DEV_USB20_HOST: -+ /* These devices get their own IRQ line if available, the rest goes on IRQ0 */ -+ if (irq <= 4) { -+ set_irq(dev, irq++); -+ break; -+ } -+ } -+ } -+ -+ ssb_mips_serial_init(mcore); -+ ssb_mips_flash_detect(mcore); -+} -diff -urN linux.old/drivers/ssb/Kconfig linux.dev/drivers/ssb/Kconfig ---- linux.old/drivers/ssb/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/Kconfig 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,59 @@ -+menu "Sonics Silicon Backplane" -+ -+config SSB -+ tristate "Sonics Silicon Backplane support" -+ depends on PCI -+ help -+ Support for the Sonics Silicon Backplane bus -+ -+ The module will be called ssb -+ -+ If unsure, say m -+ -+config SSB_SILENT -+ bool "No SSB kernel messages" -+ depends on SSB -+ help -+ This option turns off all Sonics Silicon Backplane printks. -+ Note that you won't be able to identify problems, once -+ messages are turned off. -+ This might only be desired for production kernels on -+ embedded devices. -+ -+ Say n -+ -+config SSB_DEBUG -+ bool "SSB debugging" -+ depends on SSB && !SSB_SILENT -+ # TODO: Default y for now, but change to n later -+ default y -+ help -+ This turns on additional runtime checks and debugging -+ messages. Turn this on for SSB troubleshooting. -+ -+ If unsure, say n -+ -+config SSB_SERIAL -+ bool -+ depends on SSB -+ # ChipCommon and ExtIf serial support routines. -+ -+config SSB_DRIVER_EXTIF -+ bool "SSB Broadcom EXTIF core driver" -+ help -+ Driver for the Sonics Silicon Backplane attached -+ Broadcom EXTIF core -+ -+ If unsure, say n -+ -+config SSB_DRIVER_MIPS -+ bool "SSB Broadcom MIPS core driver" -+ depends on SSB -+ select SSB_SERIAL -+ help -+ Driver for the Sonics Silicon Backplane attached -+ Broadcom MIPS core -+ -+ If unsure, say n -+ -+endmenu -diff -urN linux.old/drivers/ssb/Makefile linux.dev/drivers/ssb/Makefile ---- linux.old/drivers/ssb/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/Makefile 2007-01-03 02:40:36.000000000 +0100 -@@ -0,0 +1,8 @@ -+ssb-driver-chipcommon-y := driver_chipcommon/chipcommon.o -+ssb-driver-mips-$(CONFIG_SSB_DRIVER_MIPS) := driver_mips/mips.o -+ -+obj-$(CONFIG_SSB) += ssb.o -+ -+ssb-objs := core.o pci.o scan.o \ -+ $(ssb-driver-chipcommon-y) \ -+ $(ssb-driver-mips-y) -diff -urN linux.old/drivers/ssb/pci.c linux.dev/drivers/ssb/pci.c ---- linux.old/drivers/ssb/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/pci.c 2007-01-03 02:29:17.000000000 +0100 -@@ -0,0 +1,417 @@ -+/* -+ * Sonics Silicon Backplane PCI-Hostbus related functions. -+ * -+ * Copyright (C) 2005-2006 Michael Buesch -+ * Copyright (C) 2005 Martin Langer -+ * Copyright (C) 2005 Stefano Brivio -+ * Copyright (C) 2005 Danny van Dyk -+ * Copyright (C) 2005 Andreas Jaggi -+ * -+ * Derived from the Broadcom 4400 device driver. -+ * Copyright (C) 2002 David S. Miller (davem@redhat.com) -+ * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) -+ * Copyright (C) 2006 Broadcom Corporation. -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "ssb_private.h" -+ -+ -+int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx) -+{ -+ int err; -+ int attempts = 0; -+ u32 cur_core; -+ -+ while (1) { -+ err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN, -+ (coreidx * SSB_CORE_SIZE) -+ + SSB_ENUM_BASE); -+ if (err) -+ goto error; -+ err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN, -+ &cur_core); -+ if (err) -+ goto error; -+ cur_core = (cur_core - SSB_ENUM_BASE) -+ / SSB_CORE_SIZE; -+ if (cur_core == coreidx) -+ break; -+ -+ if (attempts++ > SSB_BAR0_MAX_RETRIES) -+ goto error; -+ udelay(10); -+ } -+ return 0; -+error: -+ printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); -+ return -ENODEV; -+} -+ -+int ssb_pci_switch_core(struct ssb_bus *bus, -+ struct ssb_device *dev) -+{ -+ int err; -+ unsigned long flags; -+ -+ ssb_dprintk("Switching to core %d\n", -+ dev->core_index); -+ -+ spin_lock_irqsave(&bus->bar_lock, flags); -+ err = ssb_pci_switch_coreidx(bus, dev->core_index); -+ if (!err) -+ bus->mapped_device = dev; -+ spin_unlock_irqrestore(&bus->bar_lock, flags); -+ -+ return err; -+} -+ -+int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on) -+{ -+ int err; -+ u32 in, out, outenable; -+ u16 pci_status; -+ -+ if (bus->bustype != SSB_BUSTYPE_PCI) -+ return 0; -+ -+ err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in); -+ if (err) -+ goto err_pci; -+ err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out); -+ if (err) -+ goto err_pci; -+ err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable); -+ if (err) -+ goto err_pci; -+ -+ outenable |= what; -+ -+ if (turn_on) { -+ /* Avoid glitching the clock if GPRS is already using it. -+ * We can't actually read the state of the PLLPD so we infer it -+ * by the value of XTAL_PU which *is* readable via gpioin. -+ */ -+ if (!(in & SSB_GPIO_XTAL)) { -+ if (what & SSB_GPIO_XTAL) { -+ /* Turn the crystal on */ -+ out |= SSB_GPIO_XTAL; -+ if (what & SSB_GPIO_PLL) -+ out |= SSB_GPIO_PLL; -+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out); -+ if (err) -+ goto err_pci; -+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, -+ outenable); -+ if (err) -+ goto err_pci; -+ msleep(1); -+ } -+ if (what & SSB_GPIO_PLL) { -+ /* Turn the PLL on */ -+ out &= ~SSB_GPIO_PLL; -+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out); -+ if (err) -+ goto err_pci; -+ msleep(2); -+ } -+ } -+ -+ err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status); -+ if (err) -+ goto err_pci; -+ pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT; -+ err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status); -+ if (err) -+ goto err_pci; -+ } else { -+ if (what & SSB_GPIO_XTAL) { -+ /* Turn the crystal off */ -+ out &= ~SSB_GPIO_XTAL; -+ } -+ if (what & SSB_GPIO_PLL) { -+ /* Turn the PLL off */ -+ out |= SSB_GPIO_PLL; -+ } -+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out); -+ if (err) -+ goto err_pci; -+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable); -+ if (err) -+ goto err_pci; -+ } -+ -+out: -+ return err; -+ -+err_pci: -+ printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n"); -+ err = -EBUSY; -+ goto out; -+} -+ -+#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16)) -+#define SPEX(_outvar, _offset, _mask, _shift) \ -+ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) -+ -+static inline u8 ssb_crc8(u8 crc, u8 data) -+{ -+ /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */ -+ static const u8 t[] = { -+ 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B, -+ 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21, -+ 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF, -+ 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5, -+ 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14, -+ 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E, -+ 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80, -+ 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA, -+ 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95, -+ 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF, -+ 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01, -+ 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B, -+ 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA, -+ 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0, -+ 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E, -+ 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34, -+ 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0, -+ 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A, -+ 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54, -+ 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E, -+ 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF, -+ 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5, -+ 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B, -+ 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61, -+ 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E, -+ 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74, -+ 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA, -+ 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0, -+ 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41, -+ 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B, -+ 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5, -+ 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F, -+ }; -+ return t[crc ^ data]; -+} -+ -+static u8 ssb_sprom_crc(const u16 *sprom) -+{ -+ int word; -+ u8 crc = 0xFF; -+ -+ for (word = 0; word < SSB_SPROMSIZE_WORDS - 1; word++) { -+ crc = ssb_crc8(crc, sprom[word] & 0x00FF); -+ crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8); -+ } -+ crc = ssb_crc8(crc, sprom[SPOFF(SSB_SPROM_REVISION)] & 0x00FF); -+ crc ^= 0xFF; -+ -+ return crc; -+} -+ -+static int sprom_check_crc(const u16 *sprom) -+{ -+ u8 crc; -+ u8 expected_crc; -+ u16 tmp; -+ -+ crc = ssb_sprom_crc(sprom); -+ tmp = sprom[SPOFF(SSB_SPROM_REVISION)] & SSB_SPROM_REVISION_CRC; -+ expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT; -+ if (crc != expected_crc) -+ return -EPROTO; -+ -+ return 0; -+} -+ -+static void sprom_do_read(struct ssb_bus *bus, u16 *sprom) -+{ -+ int i; -+ -+ for (i = 0; i < SSB_SPROMSIZE_WORDS; i++) -+ sprom[i] = ssb_raw_read16(bus, SSB_SPROM_BASE + (i * 2)); -+} -+ -+static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in) -+{ -+ int i; -+ u16 v; -+ -+ SPEX(pci_spid, SSB_SPROM1_SPID, 0xFFFF, 0); -+ SPEX(pci_svid, SSB_SPROM1_SVID, 0xFFFF, 0); -+ SPEX(pci_pid, SSB_SPROM1_PID, 0xFFFF, 0); -+ for (i = 0; i < 3; i++) { -+ v = in[SPOFF(SSB_SPROM1_IL0MAC) + i]; -+ *(((u16 *)out->il0mac) + i) = cpu_to_be16(v); -+ } -+ for (i = 0; i < 3; i++) { -+ v = in[SPOFF(SSB_SPROM1_ET0MAC) + i]; -+ *(((u16 *)out->et0mac) + i) = cpu_to_be16(v); -+ } -+ for (i = 0; i < 3; i++) { -+ v = in[SPOFF(SSB_SPROM1_ET1MAC) + i]; -+ *(((u16 *)out->et1mac) + i) = cpu_to_be16(v); -+ } -+ SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0); -+ SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A, -+ SSB_SPROM1_ETHPHY_ET1A_SHIFT); -+ SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); -+ SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); -+ SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); -+ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE, -+ SSB_SPROM1_BINF_CCODE_SHIFT); -+ SPEX(antenna_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA, -+ SSB_SPROM1_BINF_ANTA_SHIFT); -+ SPEX(antenna_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG, -+ SSB_SPROM1_BINF_ANTBG_SHIFT); -+ SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0); -+ SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0); -+ SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0); -+ SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0); -+ SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0); -+ SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0); -+ SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0); -+ SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1, -+ SSB_SPROM1_GPIOA_P1_SHIFT); -+ SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0); -+ SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3, -+ SSB_SPROM1_GPIOB_P3_SHIFT); -+ SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, 0); -+ SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, -+ SSB_SPROM1_MAXPWR_BG_SHIFT); -+ SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, 0); -+ SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, -+ SSB_SPROM1_ITSSI_BG_SHIFT); -+ SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); -+ SPEX(antenna_gain_a, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_A, 0); -+ SPEX(antenna_gain_bg, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_BG, -+ SSB_SPROM1_AGAIN_BG_SHIFT); -+ for (i = 0; i < 4; i++) { -+ v = in[SPOFF(SSB_SPROM1_OEM) + i]; -+ *(((u16 *)out->oem) + i) = cpu_to_le16(v); -+ } -+} -+ -+static void sprom_extract_r2(struct ssb_sprom_r2 *out, const u16 *in) -+{ -+ int i; -+ u16 v; -+ -+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); -+ SPEX(maxpwr_a_hi, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); -+ SPEX(maxpwr_a_lo, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, -+ SSB_SPROM2_MAXP_A_LO_SHIFT); -+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); -+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); -+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); -+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); -+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); -+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); -+ SPEX(ofdm_pwr_off, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); -+ for (i = 0; i < 4; i++) { -+ v = in[SPOFF(SSB_SPROM2_CCODE) + i]; -+ *(((u16 *)out->country_str) + i) = cpu_to_le16(v); -+ } -+} -+ -+static void sprom_extract_r3(struct ssb_sprom_r3 *out, const u16 *in) -+{ -+ out->ofdmapo = (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0xFF00) >> 8; -+ out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0x00FF) << 8; -+ out->ofdmapo <<= 16; -+ out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0xFF00) >> 8; -+ out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0x00FF) << 8; -+ -+ out->ofdmalpo = (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0xFF00) >> 8; -+ out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0x00FF) << 8; -+ out->ofdmalpo <<= 16; -+ out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0xFF00) >> 8; -+ out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0x00FF) << 8; -+ -+ out->ofdmahpo = (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0xFF00) >> 8; -+ out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0x00FF) << 8; -+ out->ofdmahpo <<= 16; -+ out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0xFF00) >> 8; -+ out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0x00FF) << 8; -+ -+ SPEX(gpioldc_on_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_ON, -+ SSB_SPROM3_GPIOLDC_ON_SHIFT); -+ SPEX(gpioldc_off_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_OFF, -+ SSB_SPROM3_GPIOLDC_OFF_SHIFT); -+ SPEX(cckpo_1M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_1M, 0); -+ SPEX(cckpo_2M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_2M, -+ SSB_SPROM3_CCKPO_2M_SHIFT); -+ SPEX(cckpo_55M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_55M, -+ SSB_SPROM3_CCKPO_55M_SHIFT); -+ SPEX(cckpo_11M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_11M, -+ SSB_SPROM3_CCKPO_11M_SHIFT); -+ -+ out->ofdmgpo = (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0xFF00) >> 8; -+ out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0x00FF) << 8; -+ out->ofdmgpo <<= 16; -+ out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0xFF00) >> 8; -+ out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0x00FF) << 8; -+} -+ -+static int sprom_extract(struct ssb_sprom *out, const u16 *in) -+{ -+ memset(out, 0, sizeof(*out)); -+ -+ SPEX(revision, SSB_SPROM_REVISION, SSB_SPROM_REVISION_REV, 0); -+ SPEX(crc, SSB_SPROM_REVISION, SSB_SPROM_REVISION_CRC, -+ SSB_SPROM_REVISION_CRC_SHIFT); -+ -+ if (out->revision == 0) -+ goto err_unsup; -+ if (out->revision >= 1 && out->revision <= 3) -+ sprom_extract_r1(&out->r1, in); -+ if (out->revision >= 2 && out->revision <= 3) -+ sprom_extract_r2(&out->r2, in); -+ if (out->revision == 3) -+ sprom_extract_r3(&out->r3, in); -+ if (out->revision >= 4) -+ goto err_unsup; -+ -+ return 0; -+err_unsup: -+ ssb_printk("ERROR: Unsupported SPROM revision %d\n", -+ out->revision); -+ return -EOPNOTSUPP; -+} -+ -+int ssb_pci_sprom_get(struct ssb_bus *bus) -+{ -+ int err = -ENOMEM; -+ u16 *buf; -+ -+ assert(bus->bustype == SSB_BUSTYPE_PCI); -+ -+ buf = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL); -+ if (!buf) -+ goto out; -+ sprom_do_read(bus, buf); -+ err = sprom_check_crc(buf); -+ if (err) -+ ssb_printk("WARNING: Invalid SPROM CRC (corrupt SPROM)\n"); -+ err = sprom_extract(&bus->sprom, buf); -+ -+ kfree(buf); -+out: -+ return err; -+} -+ -+void ssb_pci_get_boardtype(struct ssb_bus *bus) -+{ -+ pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID, -+ &bus->board_vendor); -+ pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID, -+ &bus->board_type); -+ pci_read_config_word(bus->host_pci, PCI_REVISION_ID, -+ &bus->board_rev); -+} -diff -urN linux.old/drivers/ssb/scan.c linux.dev/drivers/ssb/scan.c ---- linux.old/drivers/ssb/scan.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/scan.c 2007-01-03 02:29:17.000000000 +0100 -@@ -0,0 +1,296 @@ -+#include -+#include -+#include -+#include -+ -+#include "ssb_private.h" -+ -+ -+static const char * ssb_core_name(u16 coreid) -+{ -+ switch (coreid) { -+ case SSB_DEV_CHIPCOMMON: -+ return "ChipCommon"; -+ case SSB_DEV_ILINE20: -+ return "ILine 20"; -+ case SSB_DEV_SDRAM: -+ return "SDRAM"; -+ case SSB_DEV_PCI: -+ return "PCI"; -+ case SSB_DEV_MIPS: -+ return "MIPS"; -+ case SSB_DEV_ETHERNET: -+ return "Fast Ethernet"; -+ case SSB_DEV_V90: -+ return "V90"; -+ case SSB_DEV_USB11_HOSTDEV: -+ return "USB 1.1 Hostdev"; -+ case SSB_DEV_ADSL: -+ return "ADSL"; -+ case SSB_DEV_ILINE100: -+ return "ILine 100"; -+ case SSB_DEV_IPSEC: -+ return "IPSEC"; -+ case SSB_DEV_PCMCIA: -+ return "PCMCIA"; -+ case SSB_DEV_INTERNAL_MEM: -+ return "Internal Memory"; -+ case SSB_DEV_MEMC_SDRAM: -+ return "MEMC SDRAM"; -+ case SSB_DEV_EXTIF: -+ return "EXTIF"; -+ case SSB_DEV_80211: -+ return "IEEE 802.11"; -+ case SSB_DEV_MIPS_3302: -+ return "MIPS 3302"; -+ case SSB_DEV_USB11_HOST: -+ return "USB 1.1 Host"; -+ case SSB_DEV_USB11_DEV: -+ return "USB 1.1 Device"; -+ case SSB_DEV_USB20_HOST: -+ return "USB 2.0 Host"; -+ case SSB_DEV_USB20_DEV: -+ return "USB 2.0 Device"; -+ case SSB_DEV_SDIO_HOST: -+ return "SDIO Host"; -+ case SSB_DEV_ROBOSWITCH: -+ return "Roboswitch"; -+ case SSB_DEV_PARA_ATA: -+ return "PATA"; -+ case SSB_DEV_SATA_XORDMA: -+ return "SATA XOR-DMA"; -+ case SSB_DEV_ETHERNET_GBIT: -+ return "GBit Ethernet"; -+ case SSB_DEV_PCIE: -+ return "PCI-E"; -+ case SSB_DEV_MIMO_PHY: -+ return "MIMO PHY"; -+ case SSB_DEV_SRAM_CTRLR: -+ return "SRAM Controller"; -+ case SSB_DEV_MINI_MACPHY: -+ return "Mini MACPHY"; -+ case SSB_DEV_ARM_1176: -+ return "ARM 1176"; -+ case SSB_DEV_ARM_7TDMI: -+ return "ARM 7TDMI"; -+ } -+ return "Unknown CoreID"; -+} -+ -+static u16 pcidev_to_chipid(struct pci_dev *pci_dev) -+{ -+ u16 chipid_fallback = 0; -+ -+ switch (pci_dev->device) { -+ case 0x4301: -+ chipid_fallback = 0x4301; -+ break; -+ case 0x4305 ... 0x4307: -+ chipid_fallback = 0x4307; -+ break; -+ case 0x4402 ... 0x4403: -+ chipid_fallback = 0x4402; -+ break; -+ case 0x4610 ... 0x4615: -+ chipid_fallback = 0x4610; -+ break; -+ case 0x4710 ... 0x4715: -+ chipid_fallback = 0x4710; -+ break; -+ case 0x4320 ... 0x4325: -+ chipid_fallback = 0x4309; -+ break; -+ default: -+ ssb_printk("PCI-ID not in fallback list\n"); -+ } -+ -+ return chipid_fallback; -+} -+ -+static u8 chipid_to_nrcores(u16 chipid) -+{ -+ switch (chipid) { -+ case 0x5365: -+ return 7; -+ case 0x4306: -+ return 6; -+ case 0x4310: -+ return 8; -+ case 0x4307: -+ case 0x4301: -+ return 5; -+ case 0x4402: -+ return 3; -+ case 0x4710: -+ case 0x4610: -+ case 0x4704: -+ return 9; -+ default: -+ ssb_printk("CHIPID not found in nrcores fallback list\n"); -+ } -+ return 1; -+} -+ -+static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx, -+ u16 offset) -+{ -+ if (bus->bustype == SSB_BUSTYPE_SSB) -+ offset += current_coreidx * SSB_CORE_SIZE; -+ return ssb_raw_read32(bus, offset); -+} -+ -+static int scan_switchcore(struct ssb_bus *bus, u8 coreidx) -+{ -+ switch (bus->bustype) { -+ case SSB_BUSTYPE_SSB: -+ break; -+ case SSB_BUSTYPE_PCI: -+ return ssb_pci_switch_coreidx(bus, coreidx); -+ default: -+ assert(0); -+ } -+ return 0; -+} -+ -+int ssb_bus_scan(struct ssb_bus *bus, -+ unsigned long baseaddr) -+{ -+ int err = -ENOMEM; -+ void __iomem *mmio; -+ u32 idhi, cc, rev, tmp; -+ int i; -+ struct ssb_device *dev; -+ -+ if (bus->bustype == SSB_BUSTYPE_SSB) { -+ /* Only map the first core for now. */ -+ mmio = ioremap(baseaddr, SSB_CORE_SIZE); -+ } else { -+ assert(bus->host_pci); -+ mmio = pci_iomap(bus->host_pci, 0, ~0UL); -+ } -+ if (!mmio) -+ goto out; -+ bus->mmio = mmio; -+ -+ err = scan_switchcore(bus, 0); /* Switch to first core */ -+ if (err) -+ goto err_unmap; -+ -+ idhi = scan_read32(bus, 0, SSB_IDHIGH); -+ cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; -+ rev = (idhi & SSB_IDHIGH_RCLO); -+ rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; -+ -+ bus->nr_devices = 0; -+ if (cc == SSB_DEV_CHIPCOMMON) { -+ tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID); -+ -+ bus->chip_id = (tmp & SSB_CHIPCO_IDMASK); -+ bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >> -+ SSB_CHIPCO_REVSHIFT; -+ bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >> -+ SSB_CHIPCO_PACKSHIFT; -+ if (rev >= 4) { -+ bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >> -+ SSB_CHIPCO_NRCORESSHIFT; -+ } -+ tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP); -+ bus->chipco.capabilities = tmp; -+ } else { -+ if (bus->bustype == SSB_BUSTYPE_SSB) { -+ bus->chip_id = 0x4710; -+ bus->chip_rev = 0; -+ bus->chip_package = 0; -+ } else { -+ bus->chip_id = pcidev_to_chipid(bus->host_pci); -+ pci_read_config_word(bus->host_pci, PCI_REVISION_ID, -+ &bus->chip_rev); -+ bus->chip_package = 0; -+ } -+ } -+ if (!bus->nr_devices) -+ bus->nr_devices = chipid_to_nrcores(bus->chip_id); -+ if (bus->nr_devices > ARRAY_SIZE(bus->devices)) { -+ ssb_printk("ERR: More than %d ssb cores found (%d)\n", -+ SSB_MAX_NR_CORES, bus->nr_devices); -+ goto err_unmap; -+ } -+ if (bus->bustype == SSB_BUSTYPE_SSB) { -+ /* Now that we know the number of cores, -+ * remap the whole IO space for all cores. -+ */ -+ err = -ENOMEM; -+ iounmap(mmio); -+ mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices); -+ if (!mmio) -+ goto out; -+ bus->mmio = mmio; -+ } -+ -+ /* Fetch basic information about each core/device */ -+ for (i = 0; i < bus->nr_devices; i++) { -+ err = scan_switchcore(bus, i); -+ if (err) -+ goto err_unmap; -+ dev = &(bus->devices[i]); -+ -+ idhi = scan_read32(bus, i, SSB_IDHIGH); -+ dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; -+ dev->id.revision = (idhi & SSB_IDHIGH_RCLO); -+ dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; -+ dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT; -+ dev->core_index = i; -+ dev->bus = bus; -+ if ((dev->bus->bustype == SSB_BUSTYPE_PCI) && (bus->host_pci)) -+ dev->irq = bus->host_pci->irq; -+ -+ ssb_printk("Core %d found: %s " -+ "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", -+ i, ssb_core_name(dev->id.coreid), -+ dev->id.coreid, dev->id.revision, dev->id.vendor); -+ -+ dev->dev.bus = &ssb_bustype; -+ snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id), -+ "ssb%02x:%02x", bus->busnumber, i); -+ -+ switch (dev->id.coreid) { -+ case SSB_DEV_EXTIF: -+#ifdef CONFIG_SSB_DRIVER_EXTIF -+ if (bus->extif.dev) { -+ ssb_printk("WARNING: Multiple EXTIFs found\n"); -+ break; -+ } -+ bus->extif.dev = dev; -+#endif /* CONFIG_SSB_DRIVER_EXTIF */ -+ break; -+ case SSB_DEV_CHIPCOMMON: -+ if (bus->chipco.dev) { -+ ssb_printk("WARNING: Multiple Chipcommon found\n"); -+ break; -+ } -+ bus->chipco.dev = dev; -+ break; -+ case SSB_DEV_MIPS: -+ case SSB_DEV_MIPS_3302: -+#ifdef CONFIG_SSB_DRIVER_MIPS -+ if (bus->mipscore.dev) { -+ ssb_printk("WARNING: Multiple MIPS cores found\n"); -+ break; -+ } -+ bus->mipscore.dev = dev; -+#endif /* CONFIG_SSB_DRIVER_MIPS */ -+ break; -+ default: -+ break; -+ } -+ } -+ err = 0; -+out: -+ return err; -+err_unmap: -+ if (bus->bustype == SSB_BUSTYPE_SSB) -+ iounmap(mmio); -+ else -+ pci_iounmap(bus->host_pci, mmio); -+ goto out; -+} -diff -urN linux.old/drivers/ssb/sprom.c linux.dev/drivers/ssb/sprom.c ---- linux.old/drivers/ssb/sprom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/sprom.c 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1 @@ -+ -diff -urN linux.old/drivers/ssb/ssb_private.h linux.dev/drivers/ssb/ssb_private.h ---- linux.old/drivers/ssb/ssb_private.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/drivers/ssb/ssb_private.h 2007-01-03 02:29:17.000000000 +0100 -@@ -0,0 +1,107 @@ -+#ifndef LINUX_SSB_PRIVATE_H_ -+#define LINUX_SSB_PRIVATE_H_ -+ -+#include -+#include -+#include -+ -+#ifdef CONFIG_CFE -+# include -+#endif -+ -+ -+#define PFX "ssb: " -+ -+#ifdef CONFIG_SSB_SILENT -+# define ssb_printk(fmt, x...) do { /* nothing */ } while (0) -+#else -+/* SSB specific printk. If CFE is available, this can be used in early boot. -+ * But it does not harm otherwise. It just does not print anything. -+ */ -+int __ssb_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2))); -+# define ssb_printk(fmt, x...) __ssb_printk(PFX fmt ,##x) -+#endif /* CONFIG_SSB_SILENT */ -+ -+/* dprintk: Debugging printk; vanishes for non-debug compilation */ -+#ifdef CONFIG_SSB_DEBUG -+# define ssb_dprintk(fmt, x...) ssb_printk(fmt ,##x) -+#else -+# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0) -+#endif -+ -+/* printkl: Rate limited printk */ -+#define ssb_printkl(fmt, x...) do { \ -+ if (printk_ratelimit()) \ -+ ssb_printk(fmt ,##x); \ -+ } while (0) -+ -+/* dprintkl: Rate limited debugging printk */ -+#ifdef CONFIG_SSB_DEBUG -+# define ssb_dprintkl ssb_printkl -+#else -+# define ssb_dprintkl(fmt, x...) do { /* nothing */ } while (0) -+#endif -+ -+#define assert(cond) do { \ -+ if (unlikely(!(cond))) { \ -+ ssb_dprintk(KERN_ERR PFX "BUG: Assertion failed (%s) " \ -+ "at: %s:%d:%s()\n", \ -+ #cond, __FILE__, __LINE__, __func__); \ -+ } \ -+ } while (0) -+ -+ -+extern struct bus_type ssb_bustype; -+ -+/* pci.c */ -+extern int ssb_pci_switch_core(struct ssb_bus *bus, -+ struct ssb_device *dev); -+extern int ssb_pci_switch_coreidx(struct ssb_bus *bus, -+ u8 coreidx); -+extern int ssb_pci_xtal(struct ssb_bus *bus, u32 what, -+ int turn_on); -+extern int ssb_pci_sprom_get(struct ssb_bus *bus); -+extern void ssb_pci_get_boardtype(struct ssb_bus *bus); -+ -+ -+/* scan.c */ -+extern int ssb_bus_scan(struct ssb_bus *bus, -+ unsigned long baseaddr); -+ -+ -+/* core.c */ -+extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m); -+ -+static inline -+u16 ssb_raw_read16(struct ssb_bus *bus, u16 offset) -+{ -+ return readw(bus->mmio + offset); -+} -+ -+static inline -+u32 ssb_raw_read32(struct ssb_bus *bus, u16 offset) -+{ -+ return readl(bus->mmio + offset); -+} -+ -+static inline -+void ssb_raw_write16(struct ssb_bus *bus, u16 offset, u16 value) -+{ -+ writew(value, bus->mmio + offset); -+} -+ -+static inline -+void ssb_raw_write32(struct ssb_bus *bus, u16 offset, u32 value) -+{ -+ writel(value, bus->mmio + offset); -+} -+ -+ -+static inline -+unsigned long ceildiv(unsigned long x, unsigned long y) -+{ -+ return ((x + (y - 1)) / y); -+} -+ -+ -+#endif /* LINUX_SSB_PRIVATE_H_ */ -diff -urN linux.old/include/asm-mips/asm-offsets.h linux.dev/include/asm-mips/asm-offsets.h ---- linux.old/include/asm-mips/asm-offsets.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/asm-offsets.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,214 @@ -+#ifndef __ASM_OFFSETS_H__ -+#define __ASM_OFFSETS_H__ -+/* -+ * DO NOT MODIFY. -+ * -+ * This file was generated by Kbuild -+ * -+ */ -+ -+/* MIPS pt_regs offsets. */ -+#define PT_R0 24 -+#define PT_R1 28 -+#define PT_R2 32 -+#define PT_R3 36 -+#define PT_R4 40 -+#define PT_R5 44 -+#define PT_R6 48 -+#define PT_R7 52 -+#define PT_R8 56 -+#define PT_R9 60 -+#define PT_R10 64 -+#define PT_R11 68 -+#define PT_R12 72 -+#define PT_R13 76 -+#define PT_R14 80 -+#define PT_R15 84 -+#define PT_R16 88 -+#define PT_R17 92 -+#define PT_R18 96 -+#define PT_R19 100 -+#define PT_R20 104 -+#define PT_R21 108 -+#define PT_R22 112 -+#define PT_R23 116 -+#define PT_R24 120 -+#define PT_R25 124 -+#define PT_R26 128 -+#define PT_R27 132 -+#define PT_R28 136 -+#define PT_R29 140 -+#define PT_R30 144 -+#define PT_R31 148 -+#define PT_LO 160 -+#define PT_HI 156 -+#define PT_EPC 172 -+#define PT_BVADDR 164 -+#define PT_STATUS 152 -+#define PT_CAUSE 168 -+#define PT_SIZE 176 -+ -+/* MIPS task_struct offsets. */ -+#define TASK_STATE 0 -+#define TASK_THREAD_INFO 4 -+#define TASK_FLAGS 12 -+#define TASK_MM 132 -+#define TASK_PID 168 -+#define TASK_STRUCT_SIZE 1048 -+ -+/* MIPS thread_info offsets. */ -+#define TI_TASK 0 -+#define TI_EXEC_DOMAIN 4 -+#define TI_FLAGS 8 -+#define TI_TP_VALUE 12 -+#define TI_CPU 16 -+#define TI_PRE_COUNT 20 -+#define TI_ADDR_LIMIT 24 -+#define TI_RESTART_BLOCK 28 -+#define TI_REGS 48 -+#define _THREAD_SIZE_ORDER 0x1 -+#define _THREAD_SIZE 0x2000 -+#define _THREAD_MASK 0x1fff -+ -+/* MIPS specific thread_struct offsets. */ -+#define THREAD_REG16 432 -+#define THREAD_REG17 436 -+#define THREAD_REG18 440 -+#define THREAD_REG19 444 -+#define THREAD_REG20 448 -+#define THREAD_REG21 452 -+#define THREAD_REG22 456 -+#define THREAD_REG23 460 -+#define THREAD_REG29 464 -+#define THREAD_REG30 468 -+#define THREAD_REG31 472 -+#define THREAD_STATUS 476 -+#define THREAD_FPU 480 -+#define THREAD_BVADDR 772 -+#define THREAD_BUADDR 776 -+#define THREAD_ECODE 780 -+#define THREAD_TRAPNO 784 -+#define THREAD_MFLAGS 788 -+#define THREAD_TRAMP 792 -+#define THREAD_OLDCTX 796 -+ -+#define THREAD_FPR0 480 -+#define THREAD_FPR1 488 -+#define THREAD_FPR2 496 -+#define THREAD_FPR3 504 -+#define THREAD_FPR4 512 -+#define THREAD_FPR5 520 -+#define THREAD_FPR6 528 -+#define THREAD_FPR7 536 -+#define THREAD_FPR8 544 -+#define THREAD_FPR9 552 -+#define THREAD_FPR10 560 -+#define THREAD_FPR11 568 -+#define THREAD_FPR12 576 -+#define THREAD_FPR13 584 -+#define THREAD_FPR14 592 -+#define THREAD_FPR15 600 -+#define THREAD_FPR16 608 -+#define THREAD_FPR17 616 -+#define THREAD_FPR18 624 -+#define THREAD_FPR19 632 -+#define THREAD_FPR20 640 -+#define THREAD_FPR21 648 -+#define THREAD_FPR22 656 -+#define THREAD_FPR23 664 -+#define THREAD_FPR24 672 -+#define THREAD_FPR25 680 -+#define THREAD_FPR26 688 -+#define THREAD_FPR27 696 -+#define THREAD_FPR28 704 -+#define THREAD_FPR29 712 -+#define THREAD_FPR30 720 -+#define THREAD_FPR31 728 -+#define THREAD_FCR31 736 -+ -+/* Linux sigcontext offsets. */ -+#define SC_REGS 16 -+#define SC_FPREGS 272 -+#define SC_MDHI 552 -+#define SC_MDLO 560 -+#define SC_PC 8 -+#define SC_STATUS 4 -+#define SC_FPC_CSR 532 -+#define SC_FPC_EIR 536 -+#define SC_HI1 568 -+#define SC_LO1 572 -+#define SC_HI2 576 -+#define SC_LO2 580 -+#define SC_HI3 584 -+#define SC_LO3 588 -+ -+/* Linux signal numbers. */ -+#define _SIGHUP 0x1 -+#define _SIGINT 0x2 -+#define _SIGQUIT 0x3 -+#define _SIGILL 0x4 -+#define _SIGTRAP 0x5 -+#define _SIGIOT 0x6 -+#define _SIGABRT 0x6 -+#define _SIGEMT 0x7 -+#define _SIGFPE 0x8 -+#define _SIGKILL 0x9 -+#define _SIGBUS 0xa -+#define _SIGSEGV 0xb -+#define _SIGSYS 0xc -+#define _SIGPIPE 0xd -+#define _SIGALRM 0xe -+#define _SIGTERM 0xf -+#define _SIGUSR1 0x10 -+#define _SIGUSR2 0x11 -+#define _SIGCHLD 0x12 -+#define _SIGPWR 0x13 -+#define _SIGWINCH 0x14 -+#define _SIGURG 0x15 -+#define _SIGIO 0x16 -+#define _SIGSTOP 0x17 -+#define _SIGTSTP 0x18 -+#define _SIGCONT 0x19 -+#define _SIGTTIN 0x1a -+#define _SIGTTOU 0x1b -+#define _SIGVTALRM 0x1c -+#define _SIGPROF 0x1d -+#define _SIGXCPU 0x1e -+#define _SIGXFSZ 0x1f -+ -+/* Linux irq_cpustat_t offsets. */ -+#define IC_SOFTIRQ_PENDING 0 -+#define IC_IRQ_CPUSTAT_T 32 -+ -+/* Size of struct page */ -+#define STRUCT_PAGE_SIZE 32 -+ -+/* Linux mm_struct offsets. */ -+#define MM_USERS 40 -+#define MM_PGD 36 -+#define MM_CONTEXT 348 -+ -+#define _PAGE_SIZE 0x1000 -+#define _PAGE_SHIFT 0xc -+ -+#define _PGD_T_SIZE 0x4 -+#define _PMD_T_SIZE 0x4 -+#define _PTE_T_SIZE 0x4 -+ -+#define _PGD_T_LOG2 $2 -+#define _PMD_T_LOG2 $2 -+#define _PTE_T_LOG2 $2 -+ -+#define _PMD_SHIFT 0x16 -+#define _PGDIR_SHIFT 0x16 -+ -+#define _PGD_ORDER 0x0 -+#define _PMD_ORDER 0x1 -+#define _PTE_ORDER 0x0 -+ -+#define _PTRS_PER_PGD 0x400 -+#define _PTRS_PER_PMD 0x1 -+#define _PTRS_PER_PTE 0x400 -+ -+ -+#endif -diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h ---- linux.old/include/asm-mips/bootinfo.h 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/include/asm-mips/bootinfo.h 2007-01-03 02:26:02.000000000 +0100 -@@ -212,6 +212,12 @@ - #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ - #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ - -+/* -+ * Valid machtype for group Broadcom -+ */ -+#define MACH_GROUP_BRCM 23 /* Broadcom */ -+#define MACH_BCM47XX 1 /* Broadcom BCM47xx */ -+ - #define CL_SIZE COMMAND_LINE_SIZE - - const char *get_system_type(void); -diff -urN linux.old/include/asm-mips/cfe.h linux.dev/include/asm-mips/cfe.h ---- linux.old/include/asm-mips/cfe.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/cfe.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,189 @@ -+/* -+ * Broadcom Common Firmware Environment (CFE) support -+ * -+ * Copyright 2000, 2001, 2002 -+ * Broadcom Corporation. All rights reserved. -+ * -+ * Copyright (C) 2006 Michael Buesch -+ * -+ * Original Authors: Mitch Lichtenberg, Chris Demetriou -+ * -+ * This software is furnished under license and may be used and copied only -+ * in accordance with the following terms and conditions. Subject to these -+ * conditions, you may download, copy, install, use, modify and distribute -+ * modified or unmodified copies of this software in source and/or binary -+ * form. No title or ownership is transferred hereby. -+ * -+ * 1) Any source code used, modified or distributed must reproduce and -+ * retain this copyright notice and list of conditions as they appear in -+ * the source file. -+ * -+ * 2) No right is granted to use any trade name, trademark, or logo of -+ * Broadcom Corporation. The "Broadcom Corporation" name may not be -+ * used to endorse or promote products derived from this software -+ * without the prior written permission of Broadcom Corporation. -+ * -+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR -+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE -+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE -+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef LINUX_CFE_API_H_ -+#define LINUX_CFE_API_H_ -+ -+#include -+ -+ -+#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ -+#define CFE_MI_AVAILABLE 1 /* memory is available */ -+ -+#define CFE_FLG_WARMSTART 0x00000001 -+#define CFE_FLG_FULL_ARENA 0x00000001 -+#define CFE_FLG_ENV_PERMANENT 0x00000001 -+ -+#define CFE_CPU_CMD_START 1 -+#define CFE_CPU_CMD_STOP 0 -+ -+#define CFE_STDHANDLE_CONSOLE 0 -+ -+#define CFE_DEV_NETWORK 1 -+#define CFE_DEV_DISK 2 -+#define CFE_DEV_FLASH 3 -+#define CFE_DEV_SERIAL 4 -+#define CFE_DEV_CPU 5 -+#define CFE_DEV_NVRAM 6 -+#define CFE_DEV_CLOCK 7 -+#define CFE_DEV_OTHER 8 -+#define CFE_DEV_MASK 0x0F -+ -+#define CFE_CACHE_FLUSH_D 1 -+#define CFE_CACHE_INVAL_I 2 -+#define CFE_CACHE_INVAL_D 4 -+#define CFE_CACHE_INVAL_L2 8 -+ -+#define CFE_FWI_64BIT 0x00000001 -+#define CFE_FWI_32BIT 0x00000002 -+#define CFE_FWI_RELOC 0x00000004 -+#define CFE_FWI_UNCACHED 0x00000008 -+#define CFE_FWI_MULTICPU 0x00000010 -+#define CFE_FWI_FUNCSIM 0x00000020 -+#define CFE_FWI_RTLSIM 0x00000040 -+ -+struct cfe_fwinfo { -+ s64 version; /* major, minor, eco version */ -+ s64 totalmem; /* total installed mem */ -+ s64 flags; /* various flags */ -+ s64 boardid; /* board ID */ -+ s64 bootarea_va; /* VA of boot area */ -+ s64 bootarea_pa; /* PA of boot area */ -+ s64 bootarea_size; /* size of boot area */ -+}; -+ -+ -+/* The public CFE API */ -+ -+int cfe_present(void); /* Check if we booted from CFE. Returns bool */ -+ -+int cfe_getticks(s64 *ticks); -+int cfe_close(int handle); -+int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1); -+int cfe_cpu_stop(int cpu); -+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); -+int cfe_enumdev(int idx, char *name, int namelen); -+int cfe_enummem(int idx, int flags, u64 *start, u64 *length, -+ u64 *type); -+int cfe_exit(int warm, int status); -+int cfe_flushcache(int flags); -+int cfe_getdevinfo(char *name); -+int cfe_getenv(char *name, char *dest, int destlen); -+int cfe_getfwinfo(struct cfe_fwinfo *info); -+int cfe_getstdhandle(int handletype); -+int cfe_inpstat(int handle); -+int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, -+ int length, int *retlen, u64 offset); -+int cfe_open(char *name); -+int cfe_read(int handle, unsigned char *buffer, int length); -+int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length); -+int cfe_setenv(char *name, char *val); -+int cfe_write(int handle, unsigned char *buffer, int length); -+int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, -+ int length); -+ -+ -+/* High level API */ -+ -+/* Print some information to CFE's console (most likely serial line) */ -+int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2))); -+int cfe_vprintk(const char *fmt, va_list args); -+ -+ -+ -+/* Error codes returned by the low API functions */ -+ -+#define CFE_ISERR(errcode) (errcode < 0) -+ -+#define CFE_OK 0 -+#define CFE_ERR -1 /* generic error */ -+#define CFE_ERR_INV_COMMAND -2 -+#define CFE_ERR_EOF -3 -+#define CFE_ERR_IOERR -4 -+#define CFE_ERR_NOMEM -5 -+#define CFE_ERR_DEVNOTFOUND -6 -+#define CFE_ERR_DEVOPEN -7 -+#define CFE_ERR_INV_PARAM -8 -+#define CFE_ERR_ENVNOTFOUND -9 -+#define CFE_ERR_ENVREADONLY -10 -+ -+#define CFE_ERR_NOTELF -11 -+#define CFE_ERR_NOT32BIT -12 -+#define CFE_ERR_WRONGENDIAN -13 -+#define CFE_ERR_BADELFVERS -14 -+#define CFE_ERR_NOTMIPS -15 -+#define CFE_ERR_BADELFFMT -16 -+#define CFE_ERR_BADADDR -17 -+ -+#define CFE_ERR_FILENOTFOUND -18 -+#define CFE_ERR_UNSUPPORTED -19 -+ -+#define CFE_ERR_HOSTUNKNOWN -20 -+ -+#define CFE_ERR_TIMEOUT -21 -+ -+#define CFE_ERR_PROTOCOLERR -22 -+ -+#define CFE_ERR_NETDOWN -23 -+#define CFE_ERR_NONAMESERVER -24 -+ -+#define CFE_ERR_NOHANDLES -25 -+#define CFE_ERR_ALREADYBOUND -26 -+ -+#define CFE_ERR_CANNOTSET -27 -+#define CFE_ERR_NOMORE -28 -+#define CFE_ERR_BADFILESYS -29 -+#define CFE_ERR_FSNOTAVAIL -30 -+ -+#define CFE_ERR_INVBOOTBLOCK -31 -+#define CFE_ERR_WRONGDEVTYPE -32 -+#define CFE_ERR_BBCHECKSUM -33 -+#define CFE_ERR_BOOTPROGCHKSUM -34 -+ -+#define CFE_ERR_LDRNOTAVAIL -35 -+ -+#define CFE_ERR_NOTREADY -36 -+ -+#define CFE_ERR_GETMEM -37 -+#define CFE_ERR_SETMEM -38 -+ -+#define CFE_ERR_NOTCONN -39 -+#define CFE_ERR_ADDRINUSE -40 -+ -+ -+#endif /* LINUX_CFE_API_H_ */ -diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h ---- linux.old/include/asm-mips/cpu.h 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/include/asm-mips/cpu.h 2007-01-03 02:26:02.000000000 +0100 -@@ -104,6 +104,13 @@ - #define PRID_IMP_SR71000 0x0400 - - /* -+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM -+ */ -+ -+#define PRID_IMP_BCM4710 0x4000 -+#define PRID_IMP_BCM3302 0x9000 -+ -+/* - * Definitions for 7:0 on legacy processors - */ - -@@ -200,7 +207,9 @@ - #define CPU_SB1A 62 - #define CPU_74K 63 - #define CPU_R14000 64 --#define CPU_LAST 64 -+#define CPU_BCM3302 65 -+#define CPU_BCM4710 66 -+#define CPU_LAST 66 - - /* - * ISA Level encodings -diff -urN linux.old/include/asm-mips/mach-bcm947xx/kernel-entry-init.h linux.dev/include/asm-mips/mach-bcm947xx/kernel-entry-init.h ---- linux.old/include/asm-mips/mach-bcm947xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/mach-bcm947xx/kernel-entry-init.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,26 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2005 Embedded Alley Solutions, Inc -+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) -+ * Copyright (C) 2006 Michael Buesch -+ */ -+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H -+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H -+ -+/* Intentionally empty macro, used in head.S. Override in -+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary. -+ */ -+ .macro kernel_entry_setup -+ .endm -+ -+/* -+ * Do SMP slave processor setup necessary before we can savely execute C code. -+ */ -+ .macro smp_slave_setup -+ .endm -+ -+ -+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */ -diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h ---- linux.old/include/linux/pci_ids.h 2006-12-11 20:32:53.000000000 +0100 -+++ linux.dev/include/linux/pci_ids.h 2007-01-03 02:26:02.000000000 +0100 -@@ -1950,6 +1950,7 @@ - #define PCI_DEVICE_ID_TIGON3_5906M 0x1713 - #define PCI_DEVICE_ID_BCM4401 0x4401 - #define PCI_DEVICE_ID_BCM4401B0 0x4402 -+#define PCI_DEVICE_ID_BCM4713 0x4713 - - #define PCI_VENDOR_ID_TOPIC 0x151f - #define PCI_DEVICE_ID_TOPIC_TP560 0x0000 -diff -urN linux.old/include/linux/pci_ids.h.orig linux.dev/include/linux/pci_ids.h.orig ---- linux.old/include/linux/pci_ids.h.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/pci_ids.h.orig 2006-12-11 20:32:53.000000000 +0100 -@@ -0,0 +1,2356 @@ -+/* -+ * PCI Class, Vendor and Device IDs -+ * -+ * Please keep sorted. -+ */ -+ -+/* Device classes and subclasses */ -+ -+#define PCI_CLASS_NOT_DEFINED 0x0000 -+#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 -+ -+#define PCI_BASE_CLASS_STORAGE 0x01 -+#define PCI_CLASS_STORAGE_SCSI 0x0100 -+#define PCI_CLASS_STORAGE_IDE 0x0101 -+#define PCI_CLASS_STORAGE_FLOPPY 0x0102 -+#define PCI_CLASS_STORAGE_IPI 0x0103 -+#define PCI_CLASS_STORAGE_RAID 0x0104 -+#define PCI_CLASS_STORAGE_SAS 0x0107 -+#define PCI_CLASS_STORAGE_OTHER 0x0180 -+ -+#define PCI_BASE_CLASS_NETWORK 0x02 -+#define PCI_CLASS_NETWORK_ETHERNET 0x0200 -+#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 -+#define PCI_CLASS_NETWORK_FDDI 0x0202 -+#define PCI_CLASS_NETWORK_ATM 0x0203 -+#define PCI_CLASS_NETWORK_OTHER 0x0280 -+ -+#define PCI_BASE_CLASS_DISPLAY 0x03 -+#define PCI_CLASS_DISPLAY_VGA 0x0300 -+#define PCI_CLASS_DISPLAY_XGA 0x0301 -+#define PCI_CLASS_DISPLAY_3D 0x0302 -+#define PCI_CLASS_DISPLAY_OTHER 0x0380 -+ -+#define PCI_BASE_CLASS_MULTIMEDIA 0x04 -+#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 -+#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 -+#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 -+#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 -+ -+#define PCI_BASE_CLASS_MEMORY 0x05 -+#define PCI_CLASS_MEMORY_RAM 0x0500 -+#define PCI_CLASS_MEMORY_FLASH 0x0501 -+#define PCI_CLASS_MEMORY_OTHER 0x0580 -+ -+#define PCI_BASE_CLASS_BRIDGE 0x06 -+#define PCI_CLASS_BRIDGE_HOST 0x0600 -+#define PCI_CLASS_BRIDGE_ISA 0x0601 -+#define PCI_CLASS_BRIDGE_EISA 0x0602 -+#define PCI_CLASS_BRIDGE_MC 0x0603 -+#define PCI_CLASS_BRIDGE_PCI 0x0604 -+#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 -+#define PCI_CLASS_BRIDGE_NUBUS 0x0606 -+#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 -+#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 -+#define PCI_CLASS_BRIDGE_OTHER 0x0680 -+ -+#define PCI_BASE_CLASS_COMMUNICATION 0x07 -+#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 -+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 -+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 -+#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 -+#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 -+ -+#define PCI_BASE_CLASS_SYSTEM 0x08 -+#define PCI_CLASS_SYSTEM_PIC 0x0800 -+#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 -+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 -+#define PCI_CLASS_SYSTEM_DMA 0x0801 -+#define PCI_CLASS_SYSTEM_TIMER 0x0802 -+#define PCI_CLASS_SYSTEM_RTC 0x0803 -+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 -+#define PCI_CLASS_SYSTEM_SDHCI 0x0805 -+#define PCI_CLASS_SYSTEM_OTHER 0x0880 -+ -+#define PCI_BASE_CLASS_INPUT 0x09 -+#define PCI_CLASS_INPUT_KEYBOARD 0x0900 -+#define PCI_CLASS_INPUT_PEN 0x0901 -+#define PCI_CLASS_INPUT_MOUSE 0x0902 -+#define PCI_CLASS_INPUT_SCANNER 0x0903 -+#define PCI_CLASS_INPUT_GAMEPORT 0x0904 -+#define PCI_CLASS_INPUT_OTHER 0x0980 -+ -+#define PCI_BASE_CLASS_DOCKING 0x0a -+#define PCI_CLASS_DOCKING_GENERIC 0x0a00 -+#define PCI_CLASS_DOCKING_OTHER 0x0a80 -+ -+#define PCI_BASE_CLASS_PROCESSOR 0x0b -+#define PCI_CLASS_PROCESSOR_386 0x0b00 -+#define PCI_CLASS_PROCESSOR_486 0x0b01 -+#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 -+#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 -+#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 -+#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 -+#define PCI_CLASS_PROCESSOR_CO 0x0b40 -+ -+#define PCI_BASE_CLASS_SERIAL 0x0c -+#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 -+#define PCI_CLASS_SERIAL_ACCESS 0x0c01 -+#define PCI_CLASS_SERIAL_SSA 0x0c02 -+#define PCI_CLASS_SERIAL_USB 0x0c03 -+#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 -+#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 -+#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 -+#define PCI_CLASS_SERIAL_FIBER 0x0c04 -+#define PCI_CLASS_SERIAL_SMBUS 0x0c05 -+ -+#define PCI_BASE_CLASS_INTELLIGENT 0x0e -+#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 -+ -+#define PCI_BASE_CLASS_SATELLITE 0x0f -+#define PCI_CLASS_SATELLITE_TV 0x0f00 -+#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 -+#define PCI_CLASS_SATELLITE_VOICE 0x0f03 -+#define PCI_CLASS_SATELLITE_DATA 0x0f04 -+ -+#define PCI_BASE_CLASS_CRYPT 0x10 -+#define PCI_CLASS_CRYPT_NETWORK 0x1000 -+#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 -+#define PCI_CLASS_CRYPT_OTHER 0x1080 -+ -+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 -+#define PCI_CLASS_SP_DPIO 0x1100 -+#define PCI_CLASS_SP_OTHER 0x1180 -+ -+#define PCI_CLASS_OTHERS 0xff -+ -+/* Vendors and devices. Sort key: vendor first, device next. */ -+ -+#define PCI_VENDOR_ID_DYNALINK 0x0675 -+#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 -+ -+#define PCI_VENDOR_ID_BERKOM 0x0871 -+#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 -+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 -+#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 -+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 -+ -+#define PCI_VENDOR_ID_COMPAQ 0x0e11 -+#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 -+#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc -+#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 -+#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 -+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 -+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 -+#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 -+#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 -+#define PCI_DEVICE_ID_COMPAQ_CISSC 0x46 -+#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 -+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 -+ -+#define PCI_VENDOR_ID_NCR 0x1000 -+#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 -+#define PCI_DEVICE_ID_NCR_53C810 0x0001 -+#define PCI_DEVICE_ID_NCR_53C820 0x0002 -+#define PCI_DEVICE_ID_NCR_53C825 0x0003 -+#define PCI_DEVICE_ID_NCR_53C815 0x0004 -+#define PCI_DEVICE_ID_LSI_53C810AP 0x0005 -+#define PCI_DEVICE_ID_NCR_53C860 0x0006 -+#define PCI_DEVICE_ID_LSI_53C1510 0x000a -+#define PCI_DEVICE_ID_NCR_53C896 0x000b -+#define PCI_DEVICE_ID_NCR_53C895 0x000c -+#define PCI_DEVICE_ID_NCR_53C885 0x000d -+#define PCI_DEVICE_ID_NCR_53C875 0x000f -+#define PCI_DEVICE_ID_NCR_53C1510 0x0010 -+#define PCI_DEVICE_ID_LSI_53C895A 0x0012 -+#define PCI_DEVICE_ID_LSI_53C875A 0x0013 -+#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020 -+#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021 -+#define PCI_DEVICE_ID_LSI_53C1030 0x0030 -+#define PCI_DEVICE_ID_LSI_1030_53C1035 0x0032 -+#define PCI_DEVICE_ID_LSI_53C1035 0x0040 -+#define PCI_DEVICE_ID_NCR_53C875J 0x008f -+#define PCI_DEVICE_ID_LSI_FC909 0x0621 -+#define PCI_DEVICE_ID_LSI_FC929 0x0622 -+#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 -+#define PCI_DEVICE_ID_LSI_FC919 0x0624 -+#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 -+#define PCI_DEVICE_ID_LSI_FC929X 0x0626 -+#define PCI_DEVICE_ID_LSI_FC939X 0x0642 -+#define PCI_DEVICE_ID_LSI_FC949X 0x0640 -+#define PCI_DEVICE_ID_LSI_FC949ES 0x0646 -+#define PCI_DEVICE_ID_LSI_FC919X 0x0628 -+#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 -+#define PCI_DEVICE_ID_LSI_61C102 0x0901 -+#define PCI_DEVICE_ID_LSI_63C815 0x1000 -+#define PCI_DEVICE_ID_LSI_SAS1064 0x0050 -+#define PCI_DEVICE_ID_LSI_SAS1064R 0x0411 -+#define PCI_DEVICE_ID_LSI_SAS1066 0x005E -+#define PCI_DEVICE_ID_LSI_SAS1068 0x0054 -+#define PCI_DEVICE_ID_LSI_SAS1064A 0x005C -+#define PCI_DEVICE_ID_LSI_SAS1064E 0x0056 -+#define PCI_DEVICE_ID_LSI_SAS1066E 0x005A -+#define PCI_DEVICE_ID_LSI_SAS1068E 0x0058 -+#define PCI_DEVICE_ID_LSI_SAS1078 0x0060 -+ -+#define PCI_VENDOR_ID_ATI 0x1002 -+/* Mach64 */ -+#define PCI_DEVICE_ID_ATI_68800 0x4158 -+#define PCI_DEVICE_ID_ATI_215CT222 0x4354 -+#define PCI_DEVICE_ID_ATI_210888CX 0x4358 -+#define PCI_DEVICE_ID_ATI_215ET222 0x4554 -+/* Mach64 / Rage */ -+#define PCI_DEVICE_ID_ATI_215GB 0x4742 -+#define PCI_DEVICE_ID_ATI_215GD 0x4744 -+#define PCI_DEVICE_ID_ATI_215GI 0x4749 -+#define PCI_DEVICE_ID_ATI_215GP 0x4750 -+#define PCI_DEVICE_ID_ATI_215GQ 0x4751 -+#define PCI_DEVICE_ID_ATI_215XL 0x4752 -+#define PCI_DEVICE_ID_ATI_215GT 0x4754 -+#define PCI_DEVICE_ID_ATI_215GTB 0x4755 -+#define PCI_DEVICE_ID_ATI_215_IV 0x4756 -+#define PCI_DEVICE_ID_ATI_215_IW 0x4757 -+#define PCI_DEVICE_ID_ATI_215_IZ 0x475A -+#define PCI_DEVICE_ID_ATI_210888GX 0x4758 -+#define PCI_DEVICE_ID_ATI_215_LB 0x4c42 -+#define PCI_DEVICE_ID_ATI_215_LD 0x4c44 -+#define PCI_DEVICE_ID_ATI_215_LG 0x4c47 -+#define PCI_DEVICE_ID_ATI_215_LI 0x4c49 -+#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D -+#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E -+#define PCI_DEVICE_ID_ATI_215_LR 0x4c52 -+#define PCI_DEVICE_ID_ATI_215_LS 0x4c53 -+#define PCI_DEVICE_ID_ATI_264_LT 0x4c54 -+/* Mach64 VT */ -+#define PCI_DEVICE_ID_ATI_264VT 0x5654 -+#define PCI_DEVICE_ID_ATI_264VU 0x5655 -+#define PCI_DEVICE_ID_ATI_264VV 0x5656 -+/* Rage128 GL */ -+#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 -+#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 -+#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x5247 -+/* Rage128 VR */ -+#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b -+#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c -+#define PCI_DEVICE_ID_ATI_RAGE128_SE 0x5345 -+#define PCI_DEVICE_ID_ATI_RAGE128_SF 0x5346 -+#define PCI_DEVICE_ID_ATI_RAGE128_SG 0x5347 -+#define PCI_DEVICE_ID_ATI_RAGE128_SH 0x5348 -+#define PCI_DEVICE_ID_ATI_RAGE128_SK 0x534b -+#define PCI_DEVICE_ID_ATI_RAGE128_SL 0x534c -+#define PCI_DEVICE_ID_ATI_RAGE128_SM 0x534d -+#define PCI_DEVICE_ID_ATI_RAGE128_SN 0x534e -+/* Rage128 Ultra */ -+#define PCI_DEVICE_ID_ATI_RAGE128_TF 0x5446 -+#define PCI_DEVICE_ID_ATI_RAGE128_TL 0x544c -+#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 -+#define PCI_DEVICE_ID_ATI_RAGE128_TS 0x5453 -+#define PCI_DEVICE_ID_ATI_RAGE128_TT 0x5454 -+#define PCI_DEVICE_ID_ATI_RAGE128_TU 0x5455 -+/* Rage128 M3 */ -+#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 -+#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 -+/* Rage128 M4 */ -+#define PCI_DEVICE_ID_ATI_RAGE128_MF 0x4d46 -+#define PCI_DEVICE_ID_ATI_RAGE128_ML 0x4d4c -+/* Rage128 Pro GL */ -+#define PCI_DEVICE_ID_ATI_RAGE128_PA 0x5041 -+#define PCI_DEVICE_ID_ATI_RAGE128_PB 0x5042 -+#define PCI_DEVICE_ID_ATI_RAGE128_PC 0x5043 -+#define PCI_DEVICE_ID_ATI_RAGE128_PD 0x5044 -+#define PCI_DEVICE_ID_ATI_RAGE128_PE 0x5045 -+#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 -+/* Rage128 Pro VR */ -+#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 -+#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048 -+#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049 -+#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A -+#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B -+#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C -+#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D -+#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E -+#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F -+#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 -+#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 -+#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 -+#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 -+#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 -+#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 -+#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056 -+#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 -+#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 -+/* Rage128 M4 */ -+/* Radeon R100 */ -+#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 -+#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 -+#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146 -+#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147 -+/* Radeon RV100 (VE) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 -+#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a -+/* Radeon R200 (8500) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c -+#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e -+#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f -+#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c -+#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242 -+/* Radeon R200 (9100) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d -+/* Radeon RV200 (7500) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 -+#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 -+/* Radeon NV-100 */ -+/* Radeon RV250 (9000) */ -+#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 -+#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 -+#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 -+#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 -+/* Radeon RV280 (9200) */ -+#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 -+#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 -+/* Radeon R300 (9500) */ -+/* Radeon R300 (9700) */ -+#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 -+#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 -+#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 -+#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 -+/* Radeon R350 (9800) */ -+/* Radeon RV350 (9600) */ -+/* Radeon M6 */ -+#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 -+#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a -+/* Radeon M7 */ -+#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57 -+#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58 -+/* Radeon M9 */ -+#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64 -+#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65 -+#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 -+#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 -+/* Radeon */ -+/* RadeonIGP */ -+#define PCI_DEVICE_ID_ATI_RS100 0xcab0 -+#define PCI_DEVICE_ID_ATI_RS200 0xcab2 -+#define PCI_DEVICE_ID_ATI_RS200_B 0xcbb2 -+#define PCI_DEVICE_ID_ATI_RS250 0xcab3 -+#define PCI_DEVICE_ID_ATI_RS300_100 0x5830 -+#define PCI_DEVICE_ID_ATI_RS300_133 0x5831 -+#define PCI_DEVICE_ID_ATI_RS300_166 0x5832 -+#define PCI_DEVICE_ID_ATI_RS300_200 0x5833 -+#define PCI_DEVICE_ID_ATI_RS350_100 0x7830 -+#define PCI_DEVICE_ID_ATI_RS350_133 0x7831 -+#define PCI_DEVICE_ID_ATI_RS350_166 0x7832 -+#define PCI_DEVICE_ID_ATI_RS350_200 0x7833 -+#define PCI_DEVICE_ID_ATI_RS400_100 0x5a30 -+#define PCI_DEVICE_ID_ATI_RS400_133 0x5a31 -+#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32 -+#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33 -+#define PCI_DEVICE_ID_ATI_RS480 0x5950 -+/* ATI IXP Chipset */ -+#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349 -+#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353 -+#define PCI_DEVICE_ID_ATI_IXP300_SMBUS 0x4363 -+#define PCI_DEVICE_ID_ATI_IXP300_IDE 0x4369 -+#define PCI_DEVICE_ID_ATI_IXP300_SATA 0x436e -+#define PCI_DEVICE_ID_ATI_IXP400_SMBUS 0x4372 -+#define PCI_DEVICE_ID_ATI_IXP400_IDE 0x4376 -+#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379 -+#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a -+#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380 -+#define PCI_DEVICE_ID_ATI_IXP600_SRAID 0x4381 -+#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c -+ -+#define PCI_VENDOR_ID_VLSI 0x1004 -+#define PCI_DEVICE_ID_VLSI_82C592 0x0005 -+#define PCI_DEVICE_ID_VLSI_82C593 0x0006 -+#define PCI_DEVICE_ID_VLSI_82C594 0x0007 -+#define PCI_DEVICE_ID_VLSI_82C597 0x0009 -+#define PCI_DEVICE_ID_VLSI_82C541 0x000c -+#define PCI_DEVICE_ID_VLSI_82C543 0x000d -+#define PCI_DEVICE_ID_VLSI_82C532 0x0101 -+#define PCI_DEVICE_ID_VLSI_82C534 0x0102 -+#define PCI_DEVICE_ID_VLSI_82C535 0x0104 -+#define PCI_DEVICE_ID_VLSI_82C147 0x0105 -+#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 -+ -+#define PCI_VENDOR_ID_ADL 0x1005 -+#define PCI_DEVICE_ID_ADL_2301 0x2301 -+ -+#define PCI_VENDOR_ID_NS 0x100b -+#define PCI_DEVICE_ID_NS_87415 0x0002 -+#define PCI_DEVICE_ID_NS_87560_LIO 0x000e -+#define PCI_DEVICE_ID_NS_87560_USB 0x0012 -+#define PCI_DEVICE_ID_NS_83815 0x0020 -+#define PCI_DEVICE_ID_NS_83820 0x0022 -+#define PCI_DEVICE_ID_NS_CS5535_ISA 0x002b -+#define PCI_DEVICE_ID_NS_CS5535_IDE 0x002d -+#define PCI_DEVICE_ID_NS_CS5535_AUDIO 0x002e -+#define PCI_DEVICE_ID_NS_CS5535_USB 0x002f -+#define PCI_DEVICE_ID_NS_CS5535_VIDEO 0x0030 -+#define PCI_DEVICE_ID_NS_SATURN 0x0035 -+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 -+#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 -+#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 -+#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 -+#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 -+#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 -+#define PCI_DEVICE_ID_NS_SC1100_BRIDGE 0x0510 -+#define PCI_DEVICE_ID_NS_SC1100_SMI 0x0511 -+#define PCI_DEVICE_ID_NS_SC1100_XBUS 0x0515 -+#define PCI_DEVICE_ID_NS_87410 0xd001 -+ -+#define PCI_DEVICE_ID_NS_CS5535_HOST_BRIDGE 0x0028 -+#define PCI_DEVICE_ID_NS_CS5535_ISA_BRIDGE 0x002b -+ -+#define PCI_VENDOR_ID_TSENG 0x100c -+#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 -+#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 -+#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 -+#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 -+#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 -+ -+#define PCI_VENDOR_ID_WEITEK 0x100e -+#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 -+#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 -+ -+#define PCI_VENDOR_ID_DEC 0x1011 -+#define PCI_DEVICE_ID_DEC_BRD 0x0001 -+#define PCI_DEVICE_ID_DEC_TULIP 0x0002 -+#define PCI_DEVICE_ID_DEC_TGA 0x0004 -+#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 -+#define PCI_DEVICE_ID_DEC_TGA2 0x000D -+#define PCI_DEVICE_ID_DEC_FDDI 0x000F -+#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 -+#define PCI_DEVICE_ID_DEC_21142 0x0019 -+#define PCI_DEVICE_ID_DEC_21052 0x0021 -+#define PCI_DEVICE_ID_DEC_21150 0x0022 -+#define PCI_DEVICE_ID_DEC_21152 0x0024 -+#define PCI_DEVICE_ID_DEC_21153 0x0025 -+#define PCI_DEVICE_ID_DEC_21154 0x0026 -+#define PCI_DEVICE_ID_DEC_21285 0x1065 -+#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 -+ -+#define PCI_VENDOR_ID_CIRRUS 0x1013 -+#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 -+#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 -+#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 -+#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 -+#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac -+#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 -+#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc -+#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 -+#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 -+#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 -+#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 -+#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 -+#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 -+#define PCI_DEVICE_ID_CIRRUS_4610 0x6001 -+#define PCI_DEVICE_ID_CIRRUS_4612 0x6003 -+#define PCI_DEVICE_ID_CIRRUS_4615 0x6004 -+ -+#define PCI_VENDOR_ID_IBM 0x1014 -+#define PCI_DEVICE_ID_IBM_TR 0x0018 -+#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e -+#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc -+#define PCI_DEVICE_ID_IBM_SNIPE 0x0180 -+#define PCI_DEVICE_ID_IBM_CITRINE 0x028C -+#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166 -+#define PCI_DEVICE_ID_IBM_OBSIDIAN 0x02BD -+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031 -+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219 -+#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A -+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251 -+#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 -+ -+#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */ -+#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 -+ -+#define PCI_VENDOR_ID_WD 0x101c -+#define PCI_DEVICE_ID_WD_90C 0xc24a -+ -+#define PCI_VENDOR_ID_AMI 0x101e -+#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 -+#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 -+#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 -+ -+#define PCI_VENDOR_ID_AMD 0x1022 -+#define PCI_DEVICE_ID_AMD_K8_NB 0x1100 -+#define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103 -+#define PCI_DEVICE_ID_AMD_LANCE 0x2000 -+#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 -+#define PCI_DEVICE_ID_AMD_SCSI 0x2020 -+#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 -+#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 -+#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 -+#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C -+#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E -+#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 -+#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 -+#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B -+#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 -+#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 -+#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 -+#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440 -+#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 -+#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 -+#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443 -+#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445 -+#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468 -+#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 -+#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a -+#define PCI_DEVICE_ID_AMD_8111_SMBUS 0x746b -+#define PCI_DEVICE_ID_AMD_8111_AUDIO 0x746d -+#define PCI_DEVICE_ID_AMD_8151_0 0x7454 -+#define PCI_DEVICE_ID_AMD_8131_BRIDGE 0x7450 -+#define PCI_DEVICE_ID_AMD_8131_APIC 0x7451 -+#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458 -+#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 -+#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 -+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093 -+#define PCI_DEVICE_ID_AMD_CS5536_OHC 0x2094 -+#define PCI_DEVICE_ID_AMD_CS5536_EHC 0x2095 -+#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096 -+#define PCI_DEVICE_ID_AMD_CS5536_UOC 0x2097 -+#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A -+ -+#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081 -+#define PCI_DEVICE_ID_AMD_LX_AES 0x2082 -+ -+#define PCI_VENDOR_ID_TRIDENT 0x1023 -+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 -+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 -+#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 -+#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 -+#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 -+#define PCI_DEVICE_ID_TRIDENT_939A 0x939A -+#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 -+#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 -+#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 -+#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 -+#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 -+#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 -+#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 -+#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 -+#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 -+#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 -+#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 -+ -+#define PCI_VENDOR_ID_AI 0x1025 -+#define PCI_DEVICE_ID_AI_M1435 0x1435 -+ -+#define PCI_VENDOR_ID_DELL 0x1028 -+#define PCI_DEVICE_ID_DELL_RACIII 0x0008 -+#define PCI_DEVICE_ID_DELL_RAC4 0x0012 -+#define PCI_DEVICE_ID_DELL_PERC5 0x0015 -+ -+#define PCI_VENDOR_ID_MATROX 0x102B -+#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 -+#define PCI_DEVICE_ID_MATROX_MIL 0x0519 -+#define PCI_DEVICE_ID_MATROX_MYS 0x051A -+#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b -+#define PCI_DEVICE_ID_MATROX_MYS_AGP 0x051e -+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f -+#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 -+#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 -+#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 -+#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 -+#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 -+#define PCI_DEVICE_ID_MATROX_G400 0x0525 -+#define PCI_DEVICE_ID_MATROX_G550 0x2527 -+#define PCI_DEVICE_ID_MATROX_VIA 0x4536 -+ -+#define PCI_VENDOR_ID_CT 0x102c -+#define PCI_DEVICE_ID_CT_69000 0x00c0 -+#define PCI_DEVICE_ID_CT_65545 0x00d8 -+#define PCI_DEVICE_ID_CT_65548 0x00dc -+#define PCI_DEVICE_ID_CT_65550 0x00e0 -+#define PCI_DEVICE_ID_CT_65554 0x00e4 -+#define PCI_DEVICE_ID_CT_65555 0x00e5 -+ -+#define PCI_VENDOR_ID_MIRO 0x1031 -+#define PCI_DEVICE_ID_MIRO_36050 0x5601 -+#define PCI_DEVICE_ID_MIRO_DC10PLUS 0x7efe -+#define PCI_DEVICE_ID_MIRO_DC30PLUS 0xd801 -+ -+#define PCI_VENDOR_ID_NEC 0x1033 -+#define PCI_DEVICE_ID_NEC_CBUS_1 0x0001 /* PCI-Cbus Bridge */ -+#define PCI_DEVICE_ID_NEC_LOCAL 0x0002 /* Local Bridge */ -+#define PCI_DEVICE_ID_NEC_ATM 0x0003 /* ATM LAN Controller */ -+#define PCI_DEVICE_ID_NEC_R4000 0x0004 /* R4000 Bridge */ -+#define PCI_DEVICE_ID_NEC_486 0x0005 /* 486 Like Peripheral Bus Bridge */ -+#define PCI_DEVICE_ID_NEC_ACCEL_1 0x0006 /* Graphic Accelerator */ -+#define PCI_DEVICE_ID_NEC_UXBUS 0x0007 /* UX-Bus Bridge */ -+#define PCI_DEVICE_ID_NEC_ACCEL_2 0x0008 /* Graphic Accelerator */ -+#define PCI_DEVICE_ID_NEC_GRAPH 0x0009 /* PCI-CoreGraph Bridge */ -+#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */ -+#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */ -+#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */ -+#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */ -+#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b -+#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e -+#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ -+#define PCI_DEVICE_ID_NEC_NILE4 0x005a -+#define PCI_DEVICE_ID_NEC_VRC5476 0x009b -+#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 -+#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 -+#define PCI_DEVICE_ID_NEC_PC9821CS01 0x800c /* PC-9821-CS01 */ -+#define PCI_DEVICE_ID_NEC_PC9821NRB06 0x800d /* PC-9821NR-B06 */ -+ -+#define PCI_VENDOR_ID_FD 0x1036 -+#define PCI_DEVICE_ID_FD_36C70 0x0000 -+ -+#define PCI_VENDOR_ID_SI 0x1039 -+#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 -+#define PCI_DEVICE_ID_SI_6202 0x0002 -+#define PCI_DEVICE_ID_SI_503 0x0008 -+#define PCI_DEVICE_ID_SI_ACPI 0x0009 -+#define PCI_DEVICE_ID_SI_SMBUS 0x0016 -+#define PCI_DEVICE_ID_SI_LPC 0x0018 -+#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 -+#define PCI_DEVICE_ID_SI_6205 0x0205 -+#define PCI_DEVICE_ID_SI_501 0x0406 -+#define PCI_DEVICE_ID_SI_496 0x0496 -+#define PCI_DEVICE_ID_SI_300 0x0300 -+#define PCI_DEVICE_ID_SI_315H 0x0310 -+#define PCI_DEVICE_ID_SI_315 0x0315 -+#define PCI_DEVICE_ID_SI_315PRO 0x0325 -+#define PCI_DEVICE_ID_SI_530 0x0530 -+#define PCI_DEVICE_ID_SI_540 0x0540 -+#define PCI_DEVICE_ID_SI_550 0x0550 -+#define PCI_DEVICE_ID_SI_540_VGA 0x5300 -+#define PCI_DEVICE_ID_SI_550_VGA 0x5315 -+#define PCI_DEVICE_ID_SI_620 0x0620 -+#define PCI_DEVICE_ID_SI_630 0x0630 -+#define PCI_DEVICE_ID_SI_633 0x0633 -+#define PCI_DEVICE_ID_SI_635 0x0635 -+#define PCI_DEVICE_ID_SI_640 0x0640 -+#define PCI_DEVICE_ID_SI_645 0x0645 -+#define PCI_DEVICE_ID_SI_646 0x0646 -+#define PCI_DEVICE_ID_SI_648 0x0648 -+#define PCI_DEVICE_ID_SI_650 0x0650 -+#define PCI_DEVICE_ID_SI_651 0x0651 -+#define PCI_DEVICE_ID_SI_655 0x0655 -+#define PCI_DEVICE_ID_SI_661 0x0661 -+#define PCI_DEVICE_ID_SI_730 0x0730 -+#define PCI_DEVICE_ID_SI_733 0x0733 -+#define PCI_DEVICE_ID_SI_630_VGA 0x6300 -+#define PCI_DEVICE_ID_SI_735 0x0735 -+#define PCI_DEVICE_ID_SI_740 0x0740 -+#define PCI_DEVICE_ID_SI_741 0x0741 -+#define PCI_DEVICE_ID_SI_745 0x0745 -+#define PCI_DEVICE_ID_SI_746 0x0746 -+#define PCI_DEVICE_ID_SI_755 0x0755 -+#define PCI_DEVICE_ID_SI_760 0x0760 -+#define PCI_DEVICE_ID_SI_900 0x0900 -+#define PCI_DEVICE_ID_SI_961 0x0961 -+#define PCI_DEVICE_ID_SI_962 0x0962 -+#define PCI_DEVICE_ID_SI_963 0x0963 -+#define PCI_DEVICE_ID_SI_965 0x0965 -+#define PCI_DEVICE_ID_SI_966 0x0966 -+#define PCI_DEVICE_ID_SI_968 0x0968 -+#define PCI_DEVICE_ID_SI_5511 0x5511 -+#define PCI_DEVICE_ID_SI_5513 0x5513 -+#define PCI_DEVICE_ID_SI_5517 0x5517 -+#define PCI_DEVICE_ID_SI_5518 0x5518 -+#define PCI_DEVICE_ID_SI_5571 0x5571 -+#define PCI_DEVICE_ID_SI_5581 0x5581 -+#define PCI_DEVICE_ID_SI_5582 0x5582 -+#define PCI_DEVICE_ID_SI_5591 0x5591 -+#define PCI_DEVICE_ID_SI_5596 0x5596 -+#define PCI_DEVICE_ID_SI_5597 0x5597 -+#define PCI_DEVICE_ID_SI_5598 0x5598 -+#define PCI_DEVICE_ID_SI_5600 0x5600 -+#define PCI_DEVICE_ID_SI_7012 0x7012 -+#define PCI_DEVICE_ID_SI_7013 0x7013 -+#define PCI_DEVICE_ID_SI_7016 0x7016 -+#define PCI_DEVICE_ID_SI_7018 0x7018 -+ -+#define PCI_VENDOR_ID_HP 0x103c -+#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FX2 0x100a -+#define PCI_DEVICE_ID_HP_TACHYON 0x1028 -+#define PCI_DEVICE_ID_HP_TACHLITE 0x1029 -+#define PCI_DEVICE_ID_HP_J2585A 0x1030 -+#define PCI_DEVICE_ID_HP_J2585B 0x1031 -+#define PCI_DEVICE_ID_HP_J2973A 0x1040 -+#define PCI_DEVICE_ID_HP_J2970A 0x1042 -+#define PCI_DEVICE_ID_HP_DIVA 0x1048 -+#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 -+#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A -+#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B -+#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b -+#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 -+#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 -+#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 -+#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a -+#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e -+#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c -+#define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282 -+#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 -+#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 -+#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a -+#define PCI_DEVICE_ID_HP_CISSA 0x3220 -+#define PCI_DEVICE_ID_HP_CISSC 0x3230 -+#define PCI_DEVICE_ID_HP_CISSD 0x3238 -+#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 -+ -+#define PCI_VENDOR_ID_PCTECH 0x1042 -+#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 -+#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 -+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 -+ -+#define PCI_VENDOR_ID_ASUSTEK 0x1043 -+#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 -+ -+#define PCI_VENDOR_ID_DPT 0x1044 -+#define PCI_DEVICE_ID_DPT 0xa400 -+ -+#define PCI_VENDOR_ID_OPTI 0x1045 -+#define PCI_DEVICE_ID_OPTI_82C558 0xc558 -+#define PCI_DEVICE_ID_OPTI_82C621 0xc621 -+#define PCI_DEVICE_ID_OPTI_82C700 0xc700 -+#define PCI_DEVICE_ID_OPTI_82C825 0xd568 -+ -+#define PCI_VENDOR_ID_ELSA 0x1048 -+#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 -+#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 -+ -+ -+#define PCI_VENDOR_ID_BUSLOGIC 0x104B -+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 -+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 -+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 -+ -+#define PCI_VENDOR_ID_TI 0x104c -+#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 -+#define PCI_DEVICE_ID_TI_4450 0x8011 -+#define PCI_DEVICE_ID_TI_XX21_XX11 0x8031 -+#define PCI_DEVICE_ID_TI_XX21_XX11_SD 0x8034 -+#define PCI_DEVICE_ID_TI_X515 0x8036 -+#define PCI_DEVICE_ID_TI_XX12 0x8039 -+#define PCI_DEVICE_ID_TI_1130 0xac12 -+#define PCI_DEVICE_ID_TI_1031 0xac13 -+#define PCI_DEVICE_ID_TI_1131 0xac15 -+#define PCI_DEVICE_ID_TI_1250 0xac16 -+#define PCI_DEVICE_ID_TI_1220 0xac17 -+#define PCI_DEVICE_ID_TI_1221 0xac19 -+#define PCI_DEVICE_ID_TI_1210 0xac1a -+#define PCI_DEVICE_ID_TI_1450 0xac1b -+#define PCI_DEVICE_ID_TI_1225 0xac1c -+#define PCI_DEVICE_ID_TI_1251A 0xac1d -+#define PCI_DEVICE_ID_TI_1211 0xac1e -+#define PCI_DEVICE_ID_TI_1251B 0xac1f -+#define PCI_DEVICE_ID_TI_4410 0xac41 -+#define PCI_DEVICE_ID_TI_4451 0xac42 -+#define PCI_DEVICE_ID_TI_4510 0xac44 -+#define PCI_DEVICE_ID_TI_4520 0xac46 -+#define PCI_DEVICE_ID_TI_7510 0xac47 -+#define PCI_DEVICE_ID_TI_7610 0xac48 -+#define PCI_DEVICE_ID_TI_7410 0xac49 -+#define PCI_DEVICE_ID_TI_1410 0xac50 -+#define PCI_DEVICE_ID_TI_1420 0xac51 -+#define PCI_DEVICE_ID_TI_1451A 0xac52 -+#define PCI_DEVICE_ID_TI_1620 0xac54 -+#define PCI_DEVICE_ID_TI_1520 0xac55 -+#define PCI_DEVICE_ID_TI_1510 0xac56 -+#define PCI_DEVICE_ID_TI_X620 0xac8d -+#define PCI_DEVICE_ID_TI_X420 0xac8e -+ -+#define PCI_VENDOR_ID_SONY 0x104d -+ -+ -+/* Winbond have two vendor IDs! See 0x10ad as well */ -+#define PCI_VENDOR_ID_WINBOND2 0x1050 -+#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a -+#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 -+ -+#define PCI_VENDOR_ID_ANIGMA 0x1051 -+#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 -+ -+#define PCI_VENDOR_ID_EFAR 0x1055 -+#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 -+#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 -+ -+#define PCI_VENDOR_ID_MOTOROLA 0x1057 -+#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 -+#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 -+#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 -+#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 -+#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 -+#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 -+#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b -+#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803 -+#define PCI_DEVICE_ID_MOTOROLA_MPC5200B 0x5809 -+ -+#define PCI_VENDOR_ID_PROMISE 0x105a -+#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 -+#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 -+#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 -+#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 -+#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 -+#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 -+#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 -+#define PCI_DEVICE_ID_PROMISE_20270 0x6268 -+#define PCI_DEVICE_ID_PROMISE_20271 0x6269 -+#define PCI_DEVICE_ID_PROMISE_20275 0x1275 -+#define PCI_DEVICE_ID_PROMISE_20276 0x5275 -+#define PCI_DEVICE_ID_PROMISE_20277 0x7275 -+ -+ -+#define PCI_VENDOR_ID_UMC 0x1060 -+#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 -+#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a -+#define PCI_DEVICE_ID_UMC_UM8886A 0x886a -+ -+ -+#define PCI_VENDOR_ID_MYLEX 0x1069 -+#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 -+#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 -+#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 -+#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 -+#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 -+#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 -+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 -+ -+ -+#define PCI_VENDOR_ID_APPLE 0x106b -+#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 -+#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e -+#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 -+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 -+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d -+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e -+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032 -+#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034 -+#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b -+#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043 -+#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b -+#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c -+#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050 -+#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051 -+#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058 -+#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059 -+#define PCI_DEVICE_ID_APPLE_IPID2_AGP 0x0066 -+#define PCI_DEVICE_ID_APPLE_IPID2_ATA 0x0069 -+#define PCI_DEVICE_ID_APPLE_IPID2_FW 0x006a -+#define PCI_DEVICE_ID_APPLE_IPID2_GMAC 0x006b -+#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 -+ -+#define PCI_VENDOR_ID_YAMAHA 0x1073 -+#define PCI_DEVICE_ID_YAMAHA_724 0x0004 -+#define PCI_DEVICE_ID_YAMAHA_724F 0x000d -+#define PCI_DEVICE_ID_YAMAHA_740 0x000a -+#define PCI_DEVICE_ID_YAMAHA_740C 0x000c -+#define PCI_DEVICE_ID_YAMAHA_744 0x0010 -+#define PCI_DEVICE_ID_YAMAHA_754 0x0012 -+ -+ -+#define PCI_VENDOR_ID_QLOGIC 0x1077 -+#define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016 -+#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 -+#define PCI_DEVICE_ID_QLOGIC_ISP1080 0x1080 -+#define PCI_DEVICE_ID_QLOGIC_ISP12160 0x1216 -+#define PCI_DEVICE_ID_QLOGIC_ISP1240 0x1240 -+#define PCI_DEVICE_ID_QLOGIC_ISP1280 0x1280 -+#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 -+#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 -+#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300 -+#define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312 -+#define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322 -+#define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312 -+#define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322 -+#define PCI_DEVICE_ID_QLOGIC_ISP2422 0x2422 -+#define PCI_DEVICE_ID_QLOGIC_ISP2432 0x2432 -+#define PCI_DEVICE_ID_QLOGIC_ISP2512 0x2512 -+#define PCI_DEVICE_ID_QLOGIC_ISP2522 0x2522 -+#define PCI_DEVICE_ID_QLOGIC_ISP5422 0x5422 -+#define PCI_DEVICE_ID_QLOGIC_ISP5432 0x5432 -+ -+#define PCI_VENDOR_ID_CYRIX 0x1078 -+#define PCI_DEVICE_ID_CYRIX_5510 0x0000 -+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 -+#define PCI_DEVICE_ID_CYRIX_5520 0x0002 -+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 -+#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 -+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 -+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 -+ -+ -+ -+#define PCI_VENDOR_ID_CONTAQ 0x1080 -+#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 -+ -+ -+#define PCI_VENDOR_ID_OLICOM 0x108d -+#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 -+#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 -+#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 -+ -+#define PCI_VENDOR_ID_SUN 0x108e -+#define PCI_DEVICE_ID_SUN_EBUS 0x1000 -+#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 -+#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100 -+#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101 -+#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102 -+#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103 -+#define PCI_DEVICE_ID_SUN_GEM 0x2bad -+#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 -+#define PCI_DEVICE_ID_SUN_PBM 0x8000 -+#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001 -+#define PCI_DEVICE_ID_SUN_SABRE 0xa000 -+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001 -+#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801 -+#define PCI_DEVICE_ID_SUN_CASSINI 0xabba -+ -+#define PCI_VENDOR_ID_CMD 0x1095 -+#define PCI_DEVICE_ID_CMD_643 0x0643 -+#define PCI_DEVICE_ID_CMD_646 0x0646 -+#define PCI_DEVICE_ID_CMD_648 0x0648 -+#define PCI_DEVICE_ID_CMD_649 0x0649 -+ -+#define PCI_DEVICE_ID_SII_680 0x0680 -+#define PCI_DEVICE_ID_SII_3112 0x3112 -+#define PCI_DEVICE_ID_SII_1210SA 0x0240 -+ -+ -+#define PCI_VENDOR_ID_BROOKTREE 0x109e -+#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 -+#define PCI_DEVICE_ID_BROOKTREE_879 0x0879 -+ -+ -+#define PCI_VENDOR_ID_SGI 0x10a9 -+#define PCI_DEVICE_ID_SGI_IOC3 0x0003 -+#define PCI_DEVICE_ID_SGI_IOC4 0x100a -+#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 -+ -+ -+#define PCI_VENDOR_ID_WINBOND 0x10ad -+#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 -+#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 -+ -+ -+#define PCI_VENDOR_ID_PLX 0x10b5 -+#define PCI_DEVICE_ID_PLX_R685 0x1030 -+#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a -+#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 -+#define PCI_DEVICE_ID_PLX_1077 0x1077 -+#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 -+#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 -+#define PCI_DEVICE_ID_PLX_R753 0x1152 -+#define PCI_DEVICE_ID_PLX_OLITEC 0x1187 -+#define PCI_DEVICE_ID_PLX_PCI200SYN 0x3196 -+#define PCI_DEVICE_ID_PLX_9050 0x9050 -+#define PCI_DEVICE_ID_PLX_9080 0x9080 -+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 -+ -+#define PCI_VENDOR_ID_MADGE 0x10b6 -+#define PCI_DEVICE_ID_MADGE_MK2 0x0002 -+ -+#define PCI_VENDOR_ID_3COM 0x10b7 -+#define PCI_DEVICE_ID_3COM_3C985 0x0001 -+#define PCI_DEVICE_ID_3COM_3C940 0x1700 -+#define PCI_DEVICE_ID_3COM_3C339 0x3390 -+#define PCI_DEVICE_ID_3COM_3C359 0x3590 -+#define PCI_DEVICE_ID_3COM_3C940B 0x80eb -+#define PCI_DEVICE_ID_3COM_3CR990 0x9900 -+#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 -+#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 -+#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 -+#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 -+#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 -+#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 -+#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a -+ -+ -+#define PCI_VENDOR_ID_AL 0x10b9 -+#define PCI_DEVICE_ID_AL_M1533 0x1533 -+#define PCI_DEVICE_ID_AL_M1535 0x1535 -+#define PCI_DEVICE_ID_AL_M1541 0x1541 -+#define PCI_DEVICE_ID_AL_M1563 0x1563 -+#define PCI_DEVICE_ID_AL_M1621 0x1621 -+#define PCI_DEVICE_ID_AL_M1631 0x1631 -+#define PCI_DEVICE_ID_AL_M1632 0x1632 -+#define PCI_DEVICE_ID_AL_M1641 0x1641 -+#define PCI_DEVICE_ID_AL_M1644 0x1644 -+#define PCI_DEVICE_ID_AL_M1647 0x1647 -+#define PCI_DEVICE_ID_AL_M1651 0x1651 -+#define PCI_DEVICE_ID_AL_M1671 0x1671 -+#define PCI_DEVICE_ID_AL_M1681 0x1681 -+#define PCI_DEVICE_ID_AL_M1683 0x1683 -+#define PCI_DEVICE_ID_AL_M1689 0x1689 -+#define PCI_DEVICE_ID_AL_M5219 0x5219 -+#define PCI_DEVICE_ID_AL_M5228 0x5228 -+#define PCI_DEVICE_ID_AL_M5229 0x5229 -+#define PCI_DEVICE_ID_AL_M5451 0x5451 -+#define PCI_DEVICE_ID_AL_M7101 0x7101 -+ -+ -+ -+#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 -+#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005 -+#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006 -+#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016 -+ -+ -+#define PCI_VENDOR_ID_TCONRAD 0x10da -+#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 -+ -+ -+#define PCI_VENDOR_ID_NVIDIA 0x10de -+#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 -+#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 -+#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 -+#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN 0x002a -+#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C -+#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS 0x0034 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE 0x0035 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA 0x0036 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2 0x003e -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800 0x0041 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE 0x0042 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x0045 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000 0x004E -+#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS 0x0052 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE 0x0053 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA 0x0054 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2 0x0055 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057 -+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 -+#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005d -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS 0x0064 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066 -+#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069 -+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS 0x0084 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086 -+#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089 -+#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a -+#define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT 0x0090 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX 0x0091 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800 0x0098 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099 -+#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 -+#define PCI_DEVICE_ID_GEFORCE_6800A 0x00c1 -+#define PCI_DEVICE_ID_GEFORCE_6800A_LE 0x00c2 -+#define PCI_DEVICE_ID_GEFORCE_GO_6800 0x00c8 -+#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA 0x00c9 -+#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc -+#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6 -+#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9 -+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da -+#define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS 0x00e4 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6 -+#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee -+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0 -+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1 -+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2 -+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3 -+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x00f9 -+#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280 0x00fd -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT 0x0140 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600 0x0141 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL 0x0145 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540 0x014E -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200 0x014F -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200 0x0164 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250 0x0166 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1 0x0167 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1 0x0168 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE 0x0173 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO 0x0177 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000 0x0185 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC 0x0189 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B -+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4 -+#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 0x01b1 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS 0x01b4 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc -+#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM 0x01c1 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B 0x0211 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE 0x0212 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT 0x0215 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600 0x0250 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400 0x0251 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200 0x0253 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS 0x0264 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE 0x0265 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS 0x0368 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE 0x036E -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA 0x037E -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2 0x037F -+#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO 0x0286 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL 0x0288 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL 0x0289 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL 0x028C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA 0x0301 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA 0x0311 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA 0x0321 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1 0x0322 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500 0x0326 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100 0x0327 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32 0x0328 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200 0x0329 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA 0x0330 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA 0x0333 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT 0x0334 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700 0x033F -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA 0x0341 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1 0x0347 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2 0x0348 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E -+#define PCI_DEVICE_ID_NVIDIA_NVENET_14 0x0372 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA 0x03E7 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE 0x03EC -+#define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE -+#define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2 0x03F6 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3 0x03F7 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE 0x0448 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_22 0x0452 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE 0x0560 -+ -+#define PCI_VENDOR_ID_IMS 0x10e0 -+#define PCI_DEVICE_ID_IMS_TT128 0x9128 -+#define PCI_DEVICE_ID_IMS_TT3D 0x9135 -+ -+ -+ -+ -+#define PCI_VENDOR_ID_INTERG 0x10ea -+#define PCI_DEVICE_ID_INTERG_1682 0x1682 -+#define PCI_DEVICE_ID_INTERG_2000 0x2000 -+#define PCI_DEVICE_ID_INTERG_2010 0x2010 -+#define PCI_DEVICE_ID_INTERG_5000 0x5000 -+#define PCI_DEVICE_ID_INTERG_5050 0x5050 -+ -+#define PCI_VENDOR_ID_REALTEK 0x10ec -+#define PCI_DEVICE_ID_REALTEK_8139 0x8139 -+ -+#define PCI_VENDOR_ID_XILINX 0x10ee -+#define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 -+#define PCI_DEVICE_ID_RME_DIGI96_8 0x3fc1 -+#define PCI_DEVICE_ID_RME_DIGI96_8_PRO 0x3fc2 -+#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3 -+#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 -+#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 -+ -+ -+#define PCI_VENDOR_ID_INIT 0x1101 -+ -+#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ -+#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 -+ -+#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ -+#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 -+ -+#define PCI_VENDOR_ID_TTI 0x1103 -+#define PCI_DEVICE_ID_TTI_HPT343 0x0003 -+#define PCI_DEVICE_ID_TTI_HPT366 0x0004 -+#define PCI_DEVICE_ID_TTI_HPT372 0x0005 -+#define PCI_DEVICE_ID_TTI_HPT302 0x0006 -+#define PCI_DEVICE_ID_TTI_HPT371 0x0007 -+#define PCI_DEVICE_ID_TTI_HPT374 0x0008 -+#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* apparently a 372N variant? */ -+ -+#define PCI_VENDOR_ID_VIA 0x1106 -+#define PCI_DEVICE_ID_VIA_8763_0 0x0198 -+#define PCI_DEVICE_ID_VIA_8380_0 0x0204 -+#define PCI_DEVICE_ID_VIA_3238_0 0x0238 -+#define PCI_DEVICE_ID_VIA_PT880 0x0258 -+#define PCI_DEVICE_ID_VIA_PT880ULTRA 0x0308 -+#define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259 -+#define PCI_DEVICE_ID_VIA_3269_0 0x0269 -+#define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282 -+#define PCI_DEVICE_ID_VIA_3296_0 0x0296 -+#define PCI_DEVICE_ID_VIA_8363_0 0x0305 -+#define PCI_DEVICE_ID_VIA_P4M800CE 0x0314 -+#define PCI_DEVICE_ID_VIA_8371_0 0x0391 -+#define PCI_DEVICE_ID_VIA_8501_0 0x0501 -+#define PCI_DEVICE_ID_VIA_82C561 0x0561 -+#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 -+#define PCI_DEVICE_ID_VIA_82C576 0x0576 -+#define PCI_DEVICE_ID_VIA_SATA_EIDE 0x0581 -+#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 -+#define PCI_DEVICE_ID_VIA_82C596 0x0596 -+#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 -+#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 -+#define PCI_DEVICE_ID_VIA_8601_0 0x0601 -+#define PCI_DEVICE_ID_VIA_8605_0 0x0605 -+#define PCI_DEVICE_ID_VIA_82C686 0x0686 -+#define PCI_DEVICE_ID_VIA_82C691_0 0x0691 -+#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 -+#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 -+#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 -+#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 -+#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 -+#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 -+#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 -+#define PCI_DEVICE_ID_VIA_8233_5 0x3059 -+#define PCI_DEVICE_ID_VIA_8233_0 0x3074 -+#define PCI_DEVICE_ID_VIA_8633_0 0x3091 -+#define PCI_DEVICE_ID_VIA_8367_0 0x3099 -+#define PCI_DEVICE_ID_VIA_8653_0 0x3101 -+#define PCI_DEVICE_ID_VIA_8622 0x3102 -+#define PCI_DEVICE_ID_VIA_8235_USB_2 0x3104 -+#define PCI_DEVICE_ID_VIA_8233C_0 0x3109 -+#define PCI_DEVICE_ID_VIA_8361 0x3112 -+#define PCI_DEVICE_ID_VIA_XM266 0x3116 -+#define PCI_DEVICE_ID_VIA_612X 0x3119 -+#define PCI_DEVICE_ID_VIA_862X_0 0x3123 -+#define PCI_DEVICE_ID_VIA_8753_0 0x3128 -+#define PCI_DEVICE_ID_VIA_8233A 0x3147 -+#define PCI_DEVICE_ID_VIA_8703_51_0 0x3148 -+#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149 -+#define PCI_DEVICE_ID_VIA_XN266 0x3156 -+#define PCI_DEVICE_ID_VIA_6410 0x3164 -+#define PCI_DEVICE_ID_VIA_8754C_0 0x3168 -+#define PCI_DEVICE_ID_VIA_8235 0x3177 -+#define PCI_DEVICE_ID_VIA_8385_0 0x3188 -+#define PCI_DEVICE_ID_VIA_8377_0 0x3189 -+#define PCI_DEVICE_ID_VIA_8378_0 0x3205 -+#define PCI_DEVICE_ID_VIA_8783_0 0x3208 -+#define PCI_DEVICE_ID_VIA_8237 0x3227 -+#define PCI_DEVICE_ID_VIA_8251 0x3287 -+#define PCI_DEVICE_ID_VIA_8237A 0x3337 -+#define PCI_DEVICE_ID_VIA_8231 0x8231 -+#define PCI_DEVICE_ID_VIA_8231_4 0x8235 -+#define PCI_DEVICE_ID_VIA_8365_1 0x8305 -+#define PCI_DEVICE_ID_VIA_CX700 0x8324 -+#define PCI_DEVICE_ID_VIA_8371_1 0x8391 -+#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 -+#define PCI_DEVICE_ID_VIA_838X_1 0xB188 -+#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198 -+ -+#define PCI_VENDOR_ID_SIEMENS 0x110A -+#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 -+ -+ -+#define PCI_VENDOR_ID_VORTEX 0x1119 -+#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 -+#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 -+#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 -+#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 -+#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 -+#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 -+#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 -+#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 -+#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 -+#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 -+#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a -+#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b -+#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c -+#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d -+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 -+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 -+#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 -+#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 -+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 -+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 -+ -+#define PCI_VENDOR_ID_EF 0x111a -+#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 -+#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 -+#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003 -+#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005 -+ -+#define PCI_VENDOR_ID_IDT 0x111d -+#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 -+ -+#define PCI_VENDOR_ID_FORE 0x1127 -+#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 -+ -+ -+#define PCI_VENDOR_ID_PHILIPS 0x1131 -+#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 -+#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 -+ -+#define PCI_VENDOR_ID_EICON 0x1133 -+#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 -+#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 -+#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 -+#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b -+#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 -+#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 -+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 -+#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 -+ -+#define PCI_VENDOR_ID_ZIATECH 0x1138 -+#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 -+ -+ -+ -+#define PCI_VENDOR_ID_SYSKONNECT 0x1148 -+#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 -+#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 -+#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 -+#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 -+#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 -+ -+ -+#define PCI_VENDOR_ID_DIGI 0x114f -+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 -+#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 -+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 -+#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 -+#define PCI_DEVICE_ID_NEO_2DB9 0x00C8 -+#define PCI_DEVICE_ID_NEO_2DB9PRI 0x00C9 -+#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA -+#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB -+ -+ -+#define PCI_VENDOR_ID_XIRCOM 0x115d -+#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 -+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 -+ -+ -+#define PCI_VENDOR_ID_SERVERWORKS 0x1166 -+#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 -+#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 -+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 -+#define PCI_DEVICE_ID_SERVERWORKS_EPB 0x0103 -+#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132 -+#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 -+#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205 -+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 -+#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227 -+ -+#define PCI_VENDOR_ID_SBE 0x1176 -+#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 -+#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 -+#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 -+ -+#define PCI_VENDOR_ID_TOSHIBA 0x1179 -+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102 -+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0103 -+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0105 -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617 -+ -+#define PCI_VENDOR_ID_TOSHIBA_2 0x102f -+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 -+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 -+#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3 -+ -+#define PCI_VENDOR_ID_RICOH 0x1180 -+#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 -+#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 -+#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 -+#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 -+#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 -+#define PCI_DEVICE_ID_RICOH_R5C822 0x0822 -+ -+#define PCI_VENDOR_ID_DLINK 0x1186 -+#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 -+ -+#define PCI_VENDOR_ID_ARTOP 0x1191 -+#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 -+#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 -+#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 -+#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 -+#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 -+#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 -+#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 -+#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 -+#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 -+#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 -+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 -+#define PCI_DEVICE_ID_ARTOP_8060 0x8060 -+ -+#define PCI_VENDOR_ID_ZEITNET 0x1193 -+#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 -+#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 -+ -+ -+#define PCI_VENDOR_ID_FUJITSU_ME 0x119e -+#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 -+#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 -+ -+#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 -+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 -+ -+#define PCI_VENDOR_ID_MARVELL 0x11ab -+#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 -+#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 -+#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 -+#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480 -+ -+#define PCI_VENDOR_ID_V3 0x11b0 -+#define PCI_DEVICE_ID_V3_V960 0x0001 -+#define PCI_DEVICE_ID_V3_V351 0x0002 -+ -+ -+#define PCI_VENDOR_ID_ATT 0x11c1 -+#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 -+ -+ -+#define PCI_VENDOR_ID_SPECIALIX 0x11cb -+#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 -+#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 -+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 -+ -+ -+#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 -+#define PCI_DEVICE_ID_AD1889JS 0x1889 -+ -+ -+#define PCI_DEVICE_ID_SEGA_BBA 0x1234 -+ -+#define PCI_VENDOR_ID_ZORAN 0x11de -+#define PCI_DEVICE_ID_ZORAN_36057 0x6057 -+#define PCI_DEVICE_ID_ZORAN_36120 0x6120 -+ -+ -+#define PCI_VENDOR_ID_COMPEX 0x11f6 -+#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 -+ -+#define PCI_VENDOR_ID_RP 0x11fe -+#define PCI_DEVICE_ID_RP32INTF 0x0001 -+#define PCI_DEVICE_ID_RP8INTF 0x0002 -+#define PCI_DEVICE_ID_RP16INTF 0x0003 -+#define PCI_DEVICE_ID_RP4QUAD 0x0004 -+#define PCI_DEVICE_ID_RP8OCTA 0x0005 -+#define PCI_DEVICE_ID_RP8J 0x0006 -+#define PCI_DEVICE_ID_RP4J 0x0007 -+#define PCI_DEVICE_ID_RP8SNI 0x0008 -+#define PCI_DEVICE_ID_RP16SNI 0x0009 -+#define PCI_DEVICE_ID_RPP4 0x000A -+#define PCI_DEVICE_ID_RPP8 0x000B -+#define PCI_DEVICE_ID_RP4M 0x000D -+#define PCI_DEVICE_ID_RP2_232 0x000E -+#define PCI_DEVICE_ID_RP2_422 0x000F -+#define PCI_DEVICE_ID_URP32INTF 0x0801 -+#define PCI_DEVICE_ID_URP8INTF 0x0802 -+#define PCI_DEVICE_ID_URP16INTF 0x0803 -+#define PCI_DEVICE_ID_URP8OCTA 0x0805 -+#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C -+#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D -+#define PCI_DEVICE_ID_CRP16INTF 0x0903 -+ -+#define PCI_VENDOR_ID_CYCLADES 0x120e -+#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 -+#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 -+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 -+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 -+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 -+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 -+#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 -+#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 -+#define PCI_DEVICE_ID_PC300_RX_2 0x0300 -+#define PCI_DEVICE_ID_PC300_RX_1 0x0301 -+#define PCI_DEVICE_ID_PC300_TE_2 0x0310 -+#define PCI_DEVICE_ID_PC300_TE_1 0x0311 -+#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320 -+#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321 -+ -+#define PCI_VENDOR_ID_ESSENTIAL 0x120f -+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 -+ -+#define PCI_VENDOR_ID_O2 0x1217 -+#define PCI_DEVICE_ID_O2_6729 0x6729 -+#define PCI_DEVICE_ID_O2_6730 0x673a -+#define PCI_DEVICE_ID_O2_6832 0x6832 -+#define PCI_DEVICE_ID_O2_6836 0x6836 -+ -+#define PCI_VENDOR_ID_3DFX 0x121a -+#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 -+#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 -+#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 -+#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 -+#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 -+ -+ -+ -+#define PCI_VENDOR_ID_AVM 0x1244 -+#define PCI_DEVICE_ID_AVM_B1 0x0700 -+#define PCI_DEVICE_ID_AVM_C4 0x0800 -+#define PCI_DEVICE_ID_AVM_A1 0x0a00 -+#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00 -+#define PCI_DEVICE_ID_AVM_C2 0x1100 -+#define PCI_DEVICE_ID_AVM_T1 0x1200 -+ -+ -+#define PCI_VENDOR_ID_STALLION 0x124d -+ -+/* Allied Telesyn */ -+#define PCI_VENDOR_ID_AT 0x1259 -+#define PCI_SUBDEVICE_ID_AT_2700FX 0x2701 -+#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703 -+ -+#define PCI_VENDOR_ID_ESS 0x125d -+#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 -+#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 -+#define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988 -+#define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989 -+#define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990 -+#define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992 -+#define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998 -+#define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999 -+#define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a -+#define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b -+ -+#define PCI_VENDOR_ID_SATSAGEM 0x1267 -+#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 -+ -+ -+#define PCI_VENDOR_ID_ENSONIQ 0x1274 -+#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 -+#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 -+#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 -+ -+#define PCI_VENDOR_ID_TRANSMETA 0x1279 -+#define PCI_DEVICE_ID_EFFICEON 0x0060 -+ -+#define PCI_VENDOR_ID_ROCKWELL 0x127A -+ -+#define PCI_VENDOR_ID_ITE 0x1283 -+#define PCI_DEVICE_ID_ITE_8211 0x8211 -+#define PCI_DEVICE_ID_ITE_8212 0x8212 -+#define PCI_DEVICE_ID_ITE_8872 0x8872 -+#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 -+ -+/* formerly Platform Tech */ -+#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 -+ -+#define PCI_VENDOR_ID_ALTEON 0x12ae -+ -+ -+#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ 0x000C -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM 0x000D -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI 0x0100 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2 0x0201 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4 0x0202 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232 0x0300 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232 0x0301 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232 0x0302 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1 0x0310 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2 0x0311 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4 0x0312 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2 0x0320 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4 0x0321 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8 0x0322 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485 0x0330 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332 -+ -+ -+#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 -+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 -+ -+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 -+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D -+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 -+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 -+ -+#define PCI_VENDOR_ID_AUREAL 0x12eb -+#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 -+#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 -+#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003 -+ -+#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 -+#define PCI_DEVICE_ID_LML_33R10 0x8a02 -+ -+ -+#define PCI_VENDOR_ID_SIIG 0x131f -+#define PCI_SUBVENDOR_ID_SIIG 0x131f -+#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 -+#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 -+#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 -+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 -+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 -+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 -+#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 -+#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 -+#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 -+#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 -+#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 -+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 -+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 -+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 -+#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 -+#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 -+#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 -+#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 -+#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 -+#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 -+#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 -+#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 -+#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 -+#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 -+#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 -+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 -+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 -+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 -+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 -+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 -+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 -+#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 -+#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 -+#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 -+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 -+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 -+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 -+#define PCI_DEVICE_ID_SIIG_8S_20x_550 0x2080 -+#define PCI_DEVICE_ID_SIIG_8S_20x_650 0x2081 -+#define PCI_DEVICE_ID_SIIG_8S_20x_850 0x2082 -+#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050 -+ -+#define PCI_VENDOR_ID_RADISYS 0x1331 -+ -+#define PCI_VENDOR_ID_DOMEX 0x134a -+#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 -+ -+#define PCI_VENDOR_ID_INTASHIELD 0x135a -+#define PCI_DEVICE_ID_INTASHIELD_IS200 0x0d80 -+ -+#define PCI_VENDOR_ID_QUATECH 0x135C -+#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 -+#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 -+#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 -+#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 -+ -+#define PCI_VENDOR_ID_SEALEVEL 0x135e -+#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 -+#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 -+#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM8 0x7804 -+ -+#define PCI_VENDOR_ID_HYPERCOPE 0x1365 -+#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 -+ -+#define PCI_VENDOR_ID_KAWASAKI 0x136b -+#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 -+ -+#define PCI_VENDOR_ID_CNET 0x1371 -+#define PCI_DEVICE_ID_CNET_GIGACARD 0x434e -+ -+#define PCI_VENDOR_ID_LMC 0x1376 -+#define PCI_DEVICE_ID_LMC_HSSI 0x0003 -+#define PCI_DEVICE_ID_LMC_DS3 0x0004 -+#define PCI_DEVICE_ID_LMC_SSI 0x0005 -+#define PCI_DEVICE_ID_LMC_T1 0x0006 -+ -+ -+#define PCI_VENDOR_ID_NETGEAR 0x1385 -+#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a -+ -+#define PCI_VENDOR_ID_APPLICOM 0x1389 -+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 -+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 -+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 -+ -+#define PCI_VENDOR_ID_MOXA 0x1393 -+#define PCI_DEVICE_ID_MOXA_RC7000 0x0001 -+#define PCI_DEVICE_ID_MOXA_CP102 0x1020 -+#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 -+#define PCI_DEVICE_ID_MOXA_CP102U 0x1022 -+#define PCI_DEVICE_ID_MOXA_C104 0x1040 -+#define PCI_DEVICE_ID_MOXA_CP104U 0x1041 -+#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 -+#define PCI_DEVICE_ID_MOXA_CT114 0x1140 -+#define PCI_DEVICE_ID_MOXA_CP114 0x1141 -+#define PCI_DEVICE_ID_MOXA_CP118U 0x1180 -+#define PCI_DEVICE_ID_MOXA_CP132 0x1320 -+#define PCI_DEVICE_ID_MOXA_CP132U 0x1321 -+#define PCI_DEVICE_ID_MOXA_CP134U 0x1340 -+#define PCI_DEVICE_ID_MOXA_C168 0x1680 -+#define PCI_DEVICE_ID_MOXA_CP168U 0x1681 -+ -+#define PCI_VENDOR_ID_CCD 0x1397 -+#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 -+#define PCI_DEVICE_ID_CCD_B000 0xb000 -+#define PCI_DEVICE_ID_CCD_B006 0xb006 -+#define PCI_DEVICE_ID_CCD_B007 0xb007 -+#define PCI_DEVICE_ID_CCD_B008 0xb008 -+#define PCI_DEVICE_ID_CCD_B009 0xb009 -+#define PCI_DEVICE_ID_CCD_B00A 0xb00a -+#define PCI_DEVICE_ID_CCD_B00B 0xb00b -+#define PCI_DEVICE_ID_CCD_B00C 0xb00c -+#define PCI_DEVICE_ID_CCD_B100 0xb100 -+#define PCI_DEVICE_ID_CCD_B700 0xb700 -+#define PCI_DEVICE_ID_CCD_B701 0xb701 -+ -+#define PCI_VENDOR_ID_EXAR 0x13a8 -+#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 -+#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 -+#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 -+ -+#define PCI_VENDOR_ID_MICROGATE 0x13c0 -+#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 -+#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 -+ -+#define PCI_VENDOR_ID_3WARE 0x13C1 -+#define PCI_DEVICE_ID_3WARE_1000 0x1000 -+#define PCI_DEVICE_ID_3WARE_7000 0x1001 -+#define PCI_DEVICE_ID_3WARE_9000 0x1002 -+ -+#define PCI_VENDOR_ID_IOMEGA 0x13ca -+#define PCI_DEVICE_ID_IOMEGA_BUZ 0x4231 -+ -+#define PCI_VENDOR_ID_ABOCOM 0x13D1 -+#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 -+ -+#define PCI_VENDOR_ID_CMEDIA 0x13f6 -+#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 -+#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 -+#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 -+#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 -+ -+#define PCI_VENDOR_ID_LAVA 0x1407 -+#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ -+#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ -+#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ -+#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ -+#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ -+#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ -+#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 -+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ -+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ -+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 -+ -+#define PCI_VENDOR_ID_TIMEDIA 0x1409 -+#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 -+ -+#define PCI_VENDOR_ID_ICE 0x1412 -+#define PCI_DEVICE_ID_ICE_1712 0x1712 -+#define PCI_DEVICE_ID_VT1724 0x1724 -+ -+#define PCI_VENDOR_ID_OXSEMI 0x1415 -+#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 -+#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 -+#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 -+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 -+#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 -+ -+#define PCI_VENDOR_ID_SAMSUNG 0x144d -+ -+#define PCI_VENDOR_ID_MYRICOM 0x14c1 -+ -+#define PCI_VENDOR_ID_TITAN 0x14D2 -+#define PCI_DEVICE_ID_TITAN_010L 0x8001 -+#define PCI_DEVICE_ID_TITAN_100L 0x8010 -+#define PCI_DEVICE_ID_TITAN_110L 0x8011 -+#define PCI_DEVICE_ID_TITAN_200L 0x8020 -+#define PCI_DEVICE_ID_TITAN_210L 0x8021 -+#define PCI_DEVICE_ID_TITAN_400L 0x8040 -+#define PCI_DEVICE_ID_TITAN_800L 0x8080 -+#define PCI_DEVICE_ID_TITAN_100 0xA001 -+#define PCI_DEVICE_ID_TITAN_200 0xA005 -+#define PCI_DEVICE_ID_TITAN_400 0xA003 -+#define PCI_DEVICE_ID_TITAN_800B 0xA004 -+ -+#define PCI_VENDOR_ID_PANACOM 0x14d4 -+#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 -+#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 -+ -+#define PCI_VENDOR_ID_SIPACKETS 0x14d9 -+#define PCI_DEVICE_ID_SP1011 0x0010 -+ -+#define PCI_VENDOR_ID_AFAVLAB 0x14db -+#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 -+#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 -+#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 -+ -+#define PCI_VENDOR_ID_BROADCOM 0x14e4 -+#define PCI_DEVICE_ID_TIGON3_5752 0x1600 -+#define PCI_DEVICE_ID_TIGON3_5752M 0x1601 -+#define PCI_DEVICE_ID_TIGON3_5700 0x1644 -+#define PCI_DEVICE_ID_TIGON3_5701 0x1645 -+#define PCI_DEVICE_ID_TIGON3_5702 0x1646 -+#define PCI_DEVICE_ID_TIGON3_5703 0x1647 -+#define PCI_DEVICE_ID_TIGON3_5704 0x1648 -+#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 -+#define PCI_DEVICE_ID_NX2_5706 0x164a -+#define PCI_DEVICE_ID_NX2_5708 0x164c -+#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d -+#define PCI_DEVICE_ID_TIGON3_5705 0x1653 -+#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 -+#define PCI_DEVICE_ID_TIGON3_5720 0x1658 -+#define PCI_DEVICE_ID_TIGON3_5721 0x1659 -+#define PCI_DEVICE_ID_TIGON3_5722 0x165a -+#define PCI_DEVICE_ID_TIGON3_5705M 0x165d -+#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e -+#define PCI_DEVICE_ID_TIGON3_5714 0x1668 -+#define PCI_DEVICE_ID_TIGON3_5714S 0x1669 -+#define PCI_DEVICE_ID_TIGON3_5780 0x166a -+#define PCI_DEVICE_ID_TIGON3_5780S 0x166b -+#define PCI_DEVICE_ID_TIGON3_5705F 0x166e -+#define PCI_DEVICE_ID_TIGON3_5754M 0x1672 -+#define PCI_DEVICE_ID_TIGON3_5755M 0x1673 -+#define PCI_DEVICE_ID_TIGON3_5756 0x1674 -+#define PCI_DEVICE_ID_TIGON3_5750 0x1676 -+#define PCI_DEVICE_ID_TIGON3_5751 0x1677 -+#define PCI_DEVICE_ID_TIGON3_5715 0x1678 -+#define PCI_DEVICE_ID_TIGON3_5715S 0x1679 -+#define PCI_DEVICE_ID_TIGON3_5754 0x167a -+#define PCI_DEVICE_ID_TIGON3_5755 0x167b -+#define PCI_DEVICE_ID_TIGON3_5750M 0x167c -+#define PCI_DEVICE_ID_TIGON3_5751M 0x167d -+#define PCI_DEVICE_ID_TIGON3_5751F 0x167e -+#define PCI_DEVICE_ID_TIGON3_5787M 0x1693 -+#define PCI_DEVICE_ID_TIGON3_5782 0x1696 -+#define PCI_DEVICE_ID_TIGON3_5786 0x169a -+#define PCI_DEVICE_ID_TIGON3_5787 0x169b -+#define PCI_DEVICE_ID_TIGON3_5788 0x169c -+#define PCI_DEVICE_ID_TIGON3_5789 0x169d -+#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 -+#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 -+#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 -+#define PCI_DEVICE_ID_NX2_5706S 0x16aa -+#define PCI_DEVICE_ID_NX2_5708S 0x16ac -+#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 -+#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 -+#define PCI_DEVICE_ID_TIGON3_5781 0x16dd -+#define PCI_DEVICE_ID_TIGON3_5753 0x16f7 -+#define PCI_DEVICE_ID_TIGON3_5753M 0x16fd -+#define PCI_DEVICE_ID_TIGON3_5753F 0x16fe -+#define PCI_DEVICE_ID_TIGON3_5901 0x170d -+#define PCI_DEVICE_ID_BCM4401B1 0x170c -+#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e -+#define PCI_DEVICE_ID_TIGON3_5906 0x1712 -+#define PCI_DEVICE_ID_TIGON3_5906M 0x1713 -+#define PCI_DEVICE_ID_BCM4401 0x4401 -+#define PCI_DEVICE_ID_BCM4401B0 0x4402 -+ -+#define PCI_VENDOR_ID_TOPIC 0x151f -+#define PCI_DEVICE_ID_TOPIC_TP560 0x0000 -+ -+#define PCI_VENDOR_ID_ENE 0x1524 -+#define PCI_DEVICE_ID_ENE_1211 0x1211 -+#define PCI_DEVICE_ID_ENE_1225 0x1225 -+#define PCI_DEVICE_ID_ENE_1410 0x1410 -+#define PCI_DEVICE_ID_ENE_710 0x1411 -+#define PCI_DEVICE_ID_ENE_712 0x1412 -+#define PCI_DEVICE_ID_ENE_1420 0x1420 -+#define PCI_DEVICE_ID_ENE_720 0x1421 -+#define PCI_DEVICE_ID_ENE_722 0x1422 -+ -+#define PCI_VENDOR_ID_CHELSIO 0x1425 -+ -+ -+#define PCI_VENDOR_ID_SYBA 0x1592 -+#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 -+#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 -+ -+#define PCI_VENDOR_ID_MORETON 0x15aa -+#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 -+ -+#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 -+#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 -+ -+#define PCI_VENDOR_ID_MELLANOX 0x15b3 -+#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 -+#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 -+#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 -+#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 -+#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c -+#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 -+ -+#define PCI_VENDOR_ID_PDC 0x15e9 -+ -+ -+#define PCI_VENDOR_ID_FARSITE 0x1619 -+#define PCI_DEVICE_ID_FARSITE_T2P 0x0400 -+#define PCI_DEVICE_ID_FARSITE_T4P 0x0440 -+#define PCI_DEVICE_ID_FARSITE_T1U 0x0610 -+#define PCI_DEVICE_ID_FARSITE_T2U 0x0620 -+#define PCI_DEVICE_ID_FARSITE_T4U 0x0640 -+#define PCI_DEVICE_ID_FARSITE_TE1 0x1610 -+#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 -+ -+#define PCI_VENDOR_ID_SIBYTE 0x166d -+#define PCI_DEVICE_ID_BCM1250_PCI 0x0001 -+#define PCI_DEVICE_ID_BCM1250_HT 0x0002 -+ -+#define PCI_VENDOR_ID_NETCELL 0x169c -+#define PCI_DEVICE_ID_REVOLUTION 0x0044 -+ -+#define PCI_VENDOR_ID_VITESSE 0x1725 -+#define PCI_DEVICE_ID_VITESSE_VSC7174 0x7174 -+ -+#define PCI_VENDOR_ID_LINKSYS 0x1737 -+#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 -+ -+#define PCI_VENDOR_ID_ALTIMA 0x173b -+#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 -+#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9 -+#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea -+#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb -+ -+#define PCI_VENDOR_ID_ARECA 0x17d3 -+#define PCI_DEVICE_ID_ARECA_1110 0x1110 -+#define PCI_DEVICE_ID_ARECA_1120 0x1120 -+#define PCI_DEVICE_ID_ARECA_1130 0x1130 -+#define PCI_DEVICE_ID_ARECA_1160 0x1160 -+#define PCI_DEVICE_ID_ARECA_1170 0x1170 -+#define PCI_DEVICE_ID_ARECA_1210 0x1210 -+#define PCI_DEVICE_ID_ARECA_1220 0x1220 -+#define PCI_DEVICE_ID_ARECA_1230 0x1230 -+#define PCI_DEVICE_ID_ARECA_1260 0x1260 -+#define PCI_DEVICE_ID_ARECA_1270 0x1270 -+#define PCI_DEVICE_ID_ARECA_1280 0x1280 -+#define PCI_DEVICE_ID_ARECA_1380 0x1380 -+#define PCI_DEVICE_ID_ARECA_1381 0x1381 -+#define PCI_DEVICE_ID_ARECA_1680 0x1680 -+#define PCI_DEVICE_ID_ARECA_1681 0x1681 -+ -+#define PCI_VENDOR_ID_S2IO 0x17d5 -+#define PCI_DEVICE_ID_S2IO_WIN 0x5731 -+#define PCI_DEVICE_ID_S2IO_UNI 0x5831 -+#define PCI_DEVICE_ID_HERC_WIN 0x5732 -+#define PCI_DEVICE_ID_HERC_UNI 0x5832 -+ -+ -+#define PCI_VENDOR_ID_SITECOM 0x182d -+#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 -+ -+#define PCI_VENDOR_ID_TOPSPIN 0x1867 -+ -+#define PCI_VENDOR_ID_TDI 0x192E -+#define PCI_DEVICE_ID_TDI_EHCI 0x0101 -+ -+#define PCI_VENDOR_ID_JMICRON 0x197B -+#define PCI_DEVICE_ID_JMICRON_JMB360 0x2360 -+#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361 -+#define PCI_DEVICE_ID_JMICRON_JMB363 0x2363 -+#define PCI_DEVICE_ID_JMICRON_JMB365 0x2365 -+#define PCI_DEVICE_ID_JMICRON_JMB366 0x2366 -+#define PCI_DEVICE_ID_JMICRON_JMB368 0x2368 -+ -+#define PCI_VENDOR_ID_TEKRAM 0x1de1 -+#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 -+ -+#define PCI_VENDOR_ID_HINT 0x3388 -+#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 -+ -+#define PCI_VENDOR_ID_3DLABS 0x3d3d -+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 -+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 -+ -+ -+#define PCI_VENDOR_ID_AKS 0x416c -+#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 -+ -+ -+ -+#define PCI_VENDOR_ID_S3 0x5333 -+#define PCI_DEVICE_ID_S3_TRIO 0x8811 -+#define PCI_DEVICE_ID_S3_868 0x8880 -+#define PCI_DEVICE_ID_S3_968 0x88f0 -+#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25 -+#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04 -+#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 -+ -+#define PCI_VENDOR_ID_DUNORD 0x5544 -+#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 -+ -+ -+#define PCI_VENDOR_ID_DCI 0x6666 -+#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 -+#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 -+#define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 -+ -+#define PCI_VENDOR_ID_INTEL 0x8086 -+#define PCI_DEVICE_ID_INTEL_EESSC 0x0008 -+#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 -+#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 -+#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 -+#define PCI_DEVICE_ID_INTEL_PXH_1 0x032A -+#define PCI_DEVICE_ID_INTEL_PXHV 0x032C -+#define PCI_DEVICE_ID_INTEL_82375 0x0482 -+#define PCI_DEVICE_ID_INTEL_82424 0x0483 -+#define PCI_DEVICE_ID_INTEL_82378 0x0484 -+#define PCI_DEVICE_ID_INTEL_I960 0x0960 -+#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 -+#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 -+#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132 -+#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 -+#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 -+#define PCI_DEVICE_ID_INTEL_7205_0 0x255d -+#define PCI_DEVICE_ID_INTEL_82437 0x122d -+#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e -+#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 -+#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 -+#define PCI_DEVICE_ID_INTEL_82441 0x1237 -+#define PCI_DEVICE_ID_INTEL_82380FB 0x124b -+#define PCI_DEVICE_ID_INTEL_82439 0x1250 -+#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 -+#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 -+#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 -+#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38 -+#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 -+#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 -+#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 -+#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 -+#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 -+#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 -+#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 -+#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 -+#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 -+#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 -+#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 -+#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 -+#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 -+#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 -+#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 -+#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 -+#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a -+#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b -+#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c -+#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e -+#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 -+#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b -+#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 -+#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 -+#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 -+#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 -+#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a -+#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b -+#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c -+#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 -+#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1 -+#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 -+#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 -+#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 -+#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9 -+#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca -+#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb -+#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc -+#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 -+#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 -+#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 -+#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 -+#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 -+#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db -+#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd -+#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 -+#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 -+#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 -+#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 -+#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab -+#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500 -+#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501 -+#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 -+#define PCI_DEVICE_ID_INTEL_82860_HB 0x2531 -+#define PCI_DEVICE_ID_INTEL_E7501_MCH 0x254c -+#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 -+#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 -+#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570 -+#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 -+#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578 -+#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580 -+#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 -+#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590 -+#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 -+#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770 -+#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 -+#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0 -+#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 -+#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 -+#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 -+#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642 -+#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a -+#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d -+#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e -+#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f -+#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670 -+#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698 -+#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b -+#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e -+#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 -+#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 -+#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 -+#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd -+#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da -+#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd -+#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de -+#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df -+#define PCI_DEVICE_ID_INTEL_ICH8_0 0x2810 -+#define PCI_DEVICE_ID_INTEL_ICH8_1 0x2811 -+#define PCI_DEVICE_ID_INTEL_ICH8_2 0x2812 -+#define PCI_DEVICE_ID_INTEL_ICH8_3 0x2814 -+#define PCI_DEVICE_ID_INTEL_ICH8_4 0x2815 -+#define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e -+#define PCI_DEVICE_ID_INTEL_ICH8_6 0x2850 -+#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 -+#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 -+#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 -+#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580 -+#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 -+#define PCI_DEVICE_ID_INTEL_E7520_MCH 0x3590 -+#define PCI_DEVICE_ID_INTEL_E7320_MCH 0x3592 -+#define PCI_DEVICE_ID_INTEL_MCH_PA 0x3595 -+#define PCI_DEVICE_ID_INTEL_MCH_PA1 0x3596 -+#define PCI_DEVICE_ID_INTEL_MCH_PB 0x3597 -+#define PCI_DEVICE_ID_INTEL_MCH_PB1 0x3598 -+#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 -+#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a -+#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e -+#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 -+#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 -+#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 -+#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 -+#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 -+#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 -+#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 -+#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 -+#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 -+#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 -+#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 -+#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 -+#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 -+#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 -+#define PCI_DEVICE_ID_INTEL_82810E_IG 0x7125 -+#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 -+#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 -+#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 -+#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 -+#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 -+#define PCI_DEVICE_ID_INTEL_440MX 0x7195 -+#define PCI_DEVICE_ID_INTEL_440MX_6 0x7196 -+#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 -+#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 -+#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b -+#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 -+#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 -+#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 -+#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 -+#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 -+#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca -+#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb -+#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea -+#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 -+#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 -+#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 -+ -+#define PCI_VENDOR_ID_SCALEMP 0x8686 -+#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL 0x1010 -+ -+#define PCI_VENDOR_ID_COMPUTONE 0x8e0e -+#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 -+#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 -+#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e -+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 -+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 -+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 -+ -+#define PCI_VENDOR_ID_KTI 0x8e2e -+ -+#define PCI_VENDOR_ID_ADAPTEC 0x9004 -+#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 -+#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 -+#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 -+#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 -+#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 -+#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 -+#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 -+#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 -+#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 -+#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 -+#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 -+#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 -+#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 -+#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 -+#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 -+#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 -+#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 -+#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 -+#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 -+#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 -+#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 -+#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 -+#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 -+#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 -+ -+#define PCI_VENDOR_ID_ADAPTEC2 0x9005 -+#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 -+#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 -+#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 -+#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f -+#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 -+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 -+#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f -+#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 -+#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 -+#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 -+#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f -+#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 -+#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 -+#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 -+#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf -+#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN 0x0500 -+#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 -+ -+ -+#define PCI_VENDOR_ID_HOLTEK 0x9412 -+#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 -+ -+#define PCI_VENDOR_ID_NETMOS 0x9710 -+#define PCI_DEVICE_ID_NETMOS_9705 0x9705 -+#define PCI_DEVICE_ID_NETMOS_9715 0x9715 -+#define PCI_DEVICE_ID_NETMOS_9735 0x9735 -+#define PCI_DEVICE_ID_NETMOS_9745 0x9745 -+#define PCI_DEVICE_ID_NETMOS_9755 0x9755 -+#define PCI_DEVICE_ID_NETMOS_9805 0x9805 -+#define PCI_DEVICE_ID_NETMOS_9815 0x9815 -+#define PCI_DEVICE_ID_NETMOS_9835 0x9835 -+#define PCI_DEVICE_ID_NETMOS_9845 0x9845 -+#define PCI_DEVICE_ID_NETMOS_9855 0x9855 -+ -+#define PCI_SUBVENDOR_ID_EXSYS 0xd84d -+#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 -+#define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 -+ -+#define PCI_VENDOR_ID_TIGERJET 0xe159 -+#define PCI_DEVICE_ID_TIGERJET_300 0x0001 -+#define PCI_DEVICE_ID_TIGERJET_100 0x0002 -+ -+#define PCI_VENDOR_ID_TTTECH 0x0357 -+#define PCI_DEVICE_ID_TTTECH_MC322 0x000A -+ -+#define PCI_VENDOR_ID_XILINX_RME 0xea60 -+#define PCI_DEVICE_ID_RME_DIGI32 0x9896 -+#define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897 -+#define PCI_DEVICE_ID_RME_DIGI32_8 0x9898 -+ -+#define PCI_VENDOR_ID_QUICKNET 0x15E2 -+#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 -diff -urN linux.old/include/linux/ssb_driver_chipcommon.h linux.dev/include/linux/ssb_driver_chipcommon.h ---- linux.old/include/linux/ssb_driver_chipcommon.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/ssb_driver_chipcommon.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,379 @@ -+#ifndef LINUX_SSB_CHIPCO_H_ -+#define LINUX_SSB_CHIPCO_H_ -+ -+/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions -+ * -+ * The chipcommon core provides chip identification, SB control, -+ * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, -+ * gpio interface, extbus, and support for serial and parallel flashes. -+ * -+ * Copyright 2005, Broadcom Corporation -+ * Copyright 2006, Michael Buesch -+ * -+ * Licensed under the GPL version 2. See COPYING for details. -+ */ -+#ifdef __KERNEL__ -+ -+/** ChipCommon core registers. **/ -+ -+#define SSB_CHIPCO_CHIPID 0x0000 -+#define SSB_CHIPCO_IDMASK 0x0000FFFF -+#define SSB_CHIPCO_REVMASK 0x000F0000 -+#define SSB_CHIPCO_REVSHIFT 16 -+#define SSB_CHIPCO_PACKMASK 0x00F00000 -+#define SSB_CHIPCO_PACKSHIFT 20 -+#define SSB_CHIPCO_NRCORESMASK 0x0F000000 -+#define SSB_CHIPCO_NRCORESSHIFT 24 -+#define SSB_CHIPCO_CAP 0x0004 /* Capabilities */ -+#define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */ -+#define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ -+#define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */ -+#define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ -+#define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ -+#define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */ -+#define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */ -+#define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */ -+#define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */ -+#define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ -+#define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */ -+#define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */ -+#define SSB_PLLTYPE_NONE 0x00000000 -+#define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ -+#define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ -+#define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ -+#define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ -+#define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ -+#define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ -+#define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ -+#define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */ -+#define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */ -+#define SSB_CHIPCO_CAP_OTPS_SHIFT 19 -+#define SSB_CHIPCO_CAP_OTPS_BASE 5 -+#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ -+#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ -+#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ -+#define SSB_CHIPCO_CORECTL 0x0008 -+#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ -+#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ -+#define SSB_CHIPCO_BIST 0x000C -+#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ -+#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 -+#define SSB_CHIPCO_OTPS_PROTECT 0x00000007 -+#define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001 -+#define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002 -+#define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004 -+#define SSB_CHIPCO_OTPC 0x0014 /* OTP control */ -+#define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000 -+#define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00 -+#define SSB_CHIPCO_OTPC_PRW_SHIFT 8 -+#define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038 -+#define SSB_CHIPCO_OTPC_VSEL 0x00000006 -+#define SSB_CHIPCO_OTPC_SELVL 0x00000001 -+#define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */ -+#define SSB_CHIPCO_OTPP_COL 0x000000FF -+#define SSB_CHIPCO_OTPP_ROW 0x0000FF00 -+#define SSB_CHIPCO_OTPP_ROW_SHIFT 8 -+#define SSB_CHIPCO_OTPP_READERR 0x10000000 -+#define SSB_CHIPCO_OTPP_VALUE 0x20000000 -+#define SSB_CHIPCO_OTPP_READ 0x40000000 -+#define SSB_CHIPCO_OTPP_START 0x80000000 -+#define SSB_CHIPCO_OTPP_BUSY 0x80000000 -+#define SSB_CHIPCO_IRQSTAT 0x0020 -+#define SSB_CHIPCO_IRQMASK 0x0024 -+#define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */ -+#define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ -+#define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ -+#define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */ -+#define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */ -+#define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */ -+#define SSB_CHIPCO_JCMD_START 0x80000000 -+#define SSB_CHIPCO_JCMD_BUSY 0x80000000 -+#define SSB_CHIPCO_JCMD_PAUSE 0x40000000 -+#define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000 -+#define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000 -+#define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000 -+#define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000 -+#define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000 -+#define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000 -+#define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000 -+#define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00 -+#define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ -+#define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000 -+#define SSB_CHIPCO_JCMD_ACC_DR 0x00010000 -+#define SSB_CHIPCO_JCMD_ACC_IR 0x00020000 -+#define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000 -+#define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000 -+#define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000 -+#define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00 -+#define SSB_CHIPCO_JCMD_IRW_SHIFT 8 -+#define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F -+#define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */ -+#define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */ -+#define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */ -+#define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */ -+#define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */ -+#define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */ -+#define SSB_CHIPCO_FLASHCTL 0x0040 -+#define SSB_CHIPCO_FLASHCTL_START 0x80000000 -+#define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START -+#define SSB_CHIPCO_FLASHADDR 0x0044 -+#define SSB_CHIPCO_FLASHDATA 0x0048 -+#define SSB_CHIPCO_BCAST_ADDR 0x0050 -+#define SSB_CHIPCO_BCAST_DATA 0x0054 -+#define SSB_CHIPCO_GPIOIN 0x0060 -+#define SSB_CHIPCO_GPIOOUT 0x0064 -+#define SSB_CHIPCO_GPIOOUTEN 0x0068 -+#define SSB_CHIPCO_GPIOCTL 0x006C -+#define SSB_CHIPCO_GPIOPOL 0x0070 -+#define SSB_CHIPCO_GPIOIRQ 0x0074 -+#define SSB_CHIPCO_WATCHDOG 0x0080 -+#define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ -+#define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 -+#define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ -+#define SSB_CHIPCO_CLOCK_N 0x0090 -+#define SSB_CHIPCO_CLOCK_SB 0x0094 -+#define SSB_CHIPCO_CLOCK_PCI 0x0098 -+#define SSB_CHIPCO_CLOCK_M2 0x009C -+#define SSB_CHIPCO_CLOCK_MIPS 0x00A0 -+#define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */ -+#define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000 -+#define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24 -+#define SSB_CHIPCO_CLKDIV_OTP 0x000F0000 -+#define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16 -+#define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00 -+#define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8 -+#define SSB_CHIPCO_CLKDIV_UART 0x000000FF -+#define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */ -+#define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ -+#define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ -+#define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ -+#define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ -+#define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ -+#define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ -+#define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ -+#define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ -+#define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ -+#define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ -+#define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ -+#define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ -+#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ -+#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16 -+#define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ -+#define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ -+#define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ -+#define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ -+#define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ -+#define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ -+#define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ -+#define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16 -+#define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */ -+#define SSB_CHIPCO_PCMCIA_CFG 0x0100 -+#define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104 -+#define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108 -+#define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C -+#define SSB_CHIPCO_IDE_CFG 0x0110 -+#define SSB_CHIPCO_IDE_MEMWAIT 0x0114 -+#define SSB_CHIPCO_IDE_ATTRWAIT 0x0118 -+#define SSB_CHIPCO_IDE_IOWAIT 0x011C -+#define SSB_CHIPCO_PROG_CFG 0x0120 -+#define SSB_CHIPCO_PROG_WAITCNT 0x0124 -+#define SSB_CHIPCO_FLASH_CFG 0x0128 -+#define SSB_CHIPCO_FLASH_WAITCNT 0x012C -+#define SSB_CHIPCO_UART0_DATA 0x0300 -+#define SSB_CHIPCO_UART0_IMR 0x0304 -+#define SSB_CHIPCO_UART0_FCR 0x0308 -+#define SSB_CHIPCO_UART0_LCR 0x030C -+#define SSB_CHIPCO_UART0_MCR 0x0310 -+#define SSB_CHIPCO_UART0_LSR 0x0314 -+#define SSB_CHIPCO_UART0_MSR 0x0318 -+#define SSB_CHIPCO_UART0_SCRATCH 0x031C -+#define SSB_CHIPCO_UART1_DATA 0x0400 -+#define SSB_CHIPCO_UART1_IMR 0x0404 -+#define SSB_CHIPCO_UART1_FCR 0x0408 -+#define SSB_CHIPCO_UART1_LCR 0x040C -+#define SSB_CHIPCO_UART1_MCR 0x0410 -+#define SSB_CHIPCO_UART1_LSR 0x0414 -+#define SSB_CHIPCO_UART1_MSR 0x0418 -+#define SSB_CHIPCO_UART1_SCRATCH 0x041C -+ -+ -+ -+/** Clockcontrol masks and values **/ -+ -+/* SSB_CHIPCO_CLOCK_N */ -+#define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */ -+#define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */ -+#define SSB_CHIPCO_CLK_N2_SHIFT 8 -+#define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */ -+#define SSB_CHIPCO_CLK_PLLC_SHIFT 16 -+ -+/* SSB_CHIPCO_CLOCK_SB/PCI/UART */ -+#define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */ -+#define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */ -+#define SSB_CHIPCO_CLK_M2_SHIFT 8 -+#define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */ -+#define SSB_CHIPCO_CLK_M3_SHIFT 16 -+#define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */ -+#define SSB_CHIPCO_CLK_MC_SHIFT 24 -+ -+/* N3M Clock control magic field values */ -+#define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */ -+#define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */ -+#define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */ -+#define SSB_CHIPCO_CLK_F6_5 0x09 -+#define SSB_CHIPCO_CLK_F6_6 0x11 -+#define SSB_CHIPCO_CLK_F6_7 0x21 -+ -+#define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */ -+ -+#define SSB_CHIPCO_CLK_MC_BYPASS 0x08 -+#define SSB_CHIPCO_CLK_MC_M1 0x04 -+#define SSB_CHIPCO_CLK_MC_M1M2 0x02 -+#define SSB_CHIPCO_CLK_MC_M1M2M3 0x01 -+#define SSB_CHIPCO_CLK_MC_M1M3 0x11 -+ -+/* Type 2 Clock control magic field values */ -+#define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ -+#define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */ -+ -+#define SSB_CHIPCO_CLK_T2MC_M1BYP 1 -+#define SSB_CHIPCO_CLK_T2MC_M2BYP 2 -+#define SSB_CHIPCO_CLK_T2MC_M3BYP 4 -+ -+/* Type 6 Clock control magic field values */ -+#define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */ -+#define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */ -+#define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */ -+#define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb)) -+ -+/* Common clock base */ -+#define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */ -+#define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */ -+ -+/* Clock control values for 200Mhz in 5350 */ -+#define SSB_CHIPCO_CLK_5350_N 0x0311 -+#define SSB_CHIPCO_CLK_5350_M 0x04020009 -+ -+ -+/** Bits in the config registers **/ -+ -+#define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */ -+#define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */ -+#define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */ -+#define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */ -+#define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */ -+#define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */ -+#define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */ -+#define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */ -+#define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */ -+#define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */ -+ -+ -+/** Flash-specific control/status values */ -+ -+/* flashcontrol opcodes for ST flashes */ -+#define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ -+#define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ -+#define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ -+#define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ -+#define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ -+#define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */ -+#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ -+#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ -+#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */ -+#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */ -+ -+/* Status register bits for ST flashes */ -+#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ -+#define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */ -+#define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */ -+#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2 -+#define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */ -+ -+/* flashcontrol opcodes for Atmel flashes */ -+#define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8 -+#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */ -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */ -+#define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */ -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */ -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289 -+#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281 -+#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */ -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */ -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 -+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 -+ -+/* Status register bits for Atmel flashes */ -+#define SSB_CHIPCO_FLASHSTA_AT_READY 0x80 -+#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40 -+#define SSB_CHIPCO_FLASHSTA_AT_ID 0x38 -+#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3 -+ -+ -+/** OTP **/ -+ -+/* OTP regions */ -+#define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT -+#define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT -+#define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT -+ -+/* OTP regions (Byte offsets from otp size) */ -+#define SSB_CHIPCO_OTP_SWLIM_OFF (-8) -+#define SSB_CHIPCO_OTP_CIDBASE_OFF 0 -+#define SSB_CHIPCO_OTP_CIDLIM_OFF 8 -+ -+/* Predefined OTP words (Word offset from otp size) */ -+#define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4) -+#define SSB_CHIPCO_OTP_HWSIGN_OFF (-3) -+#define SSB_CHIPCO_OTP_SWSIGN_OFF (-2) -+#define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1) -+ -+#define SSB_CHIPCO_OTP_CID_OFF 0 -+#define SSB_CHIPCO_OTP_PKG_OFF 1 -+#define SSB_CHIPCO_OTP_FID_OFF 2 -+#define SSB_CHIPCO_OTP_RSV_OFF 3 -+#define SSB_CHIPCO_OTP_LIM_OFF 4 -+ -+#define SSB_CHIPCO_OTP_SIGNATURE 0x578A -+#define SSB_CHIPCO_OTP_MAGIC 0x4E56 -+ -+ -+struct ssb_device; -+struct ssb_serial_port; -+ -+struct ssb_chipcommon { -+ struct ssb_device *dev; -+ u32 capabilities; -+}; -+ -+enum ssb_clkmode { -+ SSB_CLKMODE_SLOW, -+ SSB_CLKMODE_FAST, -+ SSB_CLKMODE_DYNAMIC, -+}; -+ -+extern void ssb_chipcommon_init(struct ssb_chipcommon *cc); -+extern void ssb_chipcommon_exit(struct ssb_chipcommon *cc); -+ -+extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, -+ u32 *plltype, u32 *n, u32 *m); -+extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc, -+ unsigned long ns_per_cycle); -+ -+#ifdef CONFIG_SSB_SERIAL -+extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, -+ struct ssb_serial_port *ports); -+#endif /* CONFIG_SSB_SERIAL */ -+ -+#endif /* __KERNEL__ */ -+#endif /* LINUX_SSB_CHIPCO_H_ */ -diff -urN linux.old/include/linux/ssb_driver_extif.h linux.dev/include/linux/ssb_driver_extif.h ---- linux.old/include/linux/ssb_driver_extif.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/ssb_driver_extif.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,159 @@ +/* -+ * Hardware-specific External Interface I/O core definitions -+ * for the BCM47xx family of SiliconBackplane-based chips. -+ * -+ * The External Interface core supports a total of three external chip selects -+ * supporting external interfaces. One of the external chip selects is -+ * used for Flash, one is used for PCMCIA, and the other may be -+ * programmed to support either a synchronous interface or an -+ * asynchronous interface. The asynchronous interface can be used to -+ * support external devices such as UARTs and the BCM2019 Bluetooth -+ * baseband processor. -+ * The external interface core also contains 2 on-chip 16550 UARTs, clock -+ * frequency control, a watchdog interrupt timer, and a GPIO interface. -+ * -+ * Copyright 2005, Broadcom Corporation -+ * Copyright 2006, Michael Buesch -+ * -+ * Licensed under the GPL version 2. See COPYING for details. -+ */ -+#ifndef LINUX_SSB_EXTIFCORE_H_ -+#define LINUX_SSB_EXTIFCORE_H_ -+ -+#ifdef __KERNEL__ -+ -+/* external interface address space */ -+#define SSB_EXTIF_PCMCIA_MEMBASE(x) (x) -+#define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000) -+#define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000) -+#define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000) -+#define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000) -+ -+#define SSB_EXTIF_NR_GPIOOUT 5 -+/* GPIO NOTE: -+ * The multiple instances of output and output enable registers -+ * are present to allow driver software for multiple cores to control -+ * gpio outputs without needing to share a single register pair. -+ * Use the following helper macro to get a register offset value. -+ */ -+#define SSB_EXTIF_GPIO_OUT(index) ({ \ -+ BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \ -+ SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8); \ -+ }) -+#define SSB_EXTIF_GPIO_OUTEN(index) ({ \ -+ BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \ -+ SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8); \ -+ }) -+ -+/** EXTIF core registers **/ -+ -+#define SSB_EXTIF_CTL 0x0000 -+#define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */ -+#define SSB_EXTIF_EXTSTAT 0x0004 -+#define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */ -+#define SSB_EXTIF_EXTSTAT_EIRQPIN (1 << 1) /* External interrupt pin (ro) */ -+#define SSB_EXTIF_EXTSTAT_GPIOIRQPIN (1 << 2) /* GPIO interrupt pin (ro) */ -+#define SSB_EXTIF_PCMCIA_CFG 0x0010 -+#define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014 -+#define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018 -+#define SSB_EXTIF_PCMCIA_IOWAIT 0x001C -+#define SSB_EXTIF_PROG_CFG 0x0020 -+#define SSB_EXTIF_PROG_WAITCNT 0x0024 -+#define SSB_EXTIF_FLASH_CFG 0x0028 -+#define SSB_EXTIF_FLASH_WAITCNT 0x002C -+#define SSB_EXTIF_WATCHDOG 0x0040 -+#define SSB_EXTIF_CLOCK_N 0x0044 -+#define SSB_EXTIF_CLOCK_SB 0x0048 -+#define SSB_EXTIF_CLOCK_PCI 0x004C -+#define SSB_EXTIF_CLOCK_MII 0x0050 -+#define SSB_EXTIF_GPIO_IN 0x0060 -+#define SSB_EXTIF_GPIO_OUT_BASE 0x0064 -+#define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068 -+#define SSB_EXTIF_EJTAG_OUTEN 0x0090 -+#define SSB_EXTIF_GPIO_INTPOL 0x0094 -+#define SSB_EXTIF_GPIO_INTMASK 0x0098 -+#define SSB_EXTIF_UART_DATA 0x0300 -+#define SSB_EXTIF_UART_TIMER 0x0310 -+#define SSB_EXTIF_UART_FCR 0x0320 -+#define SSB_EXTIF_UART_LCR 0x0330 -+#define SSB_EXTIF_UART_MCR 0x0340 -+#define SSB_EXTIF_UART_LSR 0x0350 -+#define SSB_EXTIF_UART_MSR 0x0360 -+#define SSB_EXTIF_UART_SCRATCH 0x0370 -+ -+ -+ -+ -+/* pcmcia/prog/flash_config */ -+#define SSB_EXTCFG_EN (1 << 0) /* enable */ -+#define SSB_EXTCFG_MODE 0xE /* mode */ -+#define SSB_EXTCFG_MODE_SHIFT 1 -+#define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */ -+#define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */ -+#define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */ -+#define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */ -+#define SSB_EXTCFG_BSWAP (1 << 5) /* byteswap */ -+#define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */ -+#define SSB_EXTCFG_CLKDIV_SHIFT 6 -+#define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */ -+#define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */ -+#define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */ -+#define SSB_EXTCFG_CLKEN (1 << 8) /* clock enable */ -+#define SSB_EXTCFG_STROBE (1 << 9) /* size/bytestrobe (synch only) */ -+ -+/* pcmcia_memwait */ -+#define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */ -+#define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */ -+#define SSB_PCMCIA_MEMW_1_SHIFT 8 -+#define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */ -+#define SSB_PCMCIA_MEMW_2_SHIFT 16 -+#define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */ -+#define SSB_PCMCIA_MEMW_3_SHIFT 24 -+ -+/* pcmcia_attrwait */ -+#define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */ -+#define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */ -+#define SSB_PCMCIA_ATTW_1_SHIFT 8 -+#define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */ -+#define SSB_PCMCIA_ATTW_2_SHIFT 16 -+#define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */ -+#define SSB_PCMCIA_ATTW_3_SHIFT 24 -+ -+/* pcmcia_iowait */ -+#define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */ -+#define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */ -+#define SSB_PCMCIA_IOW_1_SHIFT 8 -+#define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */ -+#define SSB_PCMCIA_IOW_2_SHIFT 16 -+#define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */ -+#define SSB_PCMCIA_IOW_3_SHIFT 24 -+ -+/* prog_waitcount */ -+#define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */ -+#define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */ -+#define SSB_PROG_WCNT_1_SHIFT 8 -+#define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */ -+#define SSB_PROG_WCNT_2_SHIFT 16 -+#define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */ -+#define SSB_PROG_WCNT_3_SHIFT 24 -+ -+#define SSB_PROG_W0 0x0000000C -+#define SSB_PROG_W1 0x00000A00 -+#define SSB_PROG_W2 0x00020000 -+#define SSB_PROG_W3 0x01000000 -+ -+/* flash_waitcount */ -+#define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */ -+#define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */ -+#define SSB_FLASH_WCNT_1_SHIFT 8 -+#define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */ -+#define SSB_FLASH_WCNT_2_SHIFT 16 -+#define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */ -+#define SSB_FLASH_WCNT_3_SHIFT 24 -+ -+/* watchdog */ -+#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ -+ -+ -+#endif /* __KERNEL__ */ -+#endif /* LINUX_SSB_EXTIFCORE_H_ */ -diff -urN linux.old/include/linux/ssb_driver_mips.h linux.dev/include/linux/ssb_driver_mips.h ---- linux.old/include/linux/ssb_driver_mips.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/ssb_driver_mips.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,46 @@ -+#ifndef LINUX_SSB_MIPSCORE_H_ -+#define LINUX_SSB_MIPSCORE_H_ -+ -+#ifdef __KERNEL__ -+ -+#ifdef CONFIG_SSB_DRIVER_MIPS -+ -+struct ssb_device; -+ -+struct ssb_serial_port { -+ void *regs; -+ unsigned int irq; -+ unsigned int baud_base; -+ unsigned int reg_shift; -+}; -+ -+ -+struct ssb_mipscore { -+ struct ssb_device *dev; -+ -+ int nr_serial_ports; -+ struct ssb_serial_port serial_ports[4]; -+ -+ u32 flash_window; -+ u32 flash_window_size; -+}; -+ -+extern void ssb_mipscore_init(struct ssb_mipscore *mcore); -+ -+extern unsigned int ssb_mips_irq(struct ssb_device *dev); -+ -+ -+#else /* CONFIG_SSB_DRIVER_MIPS */ -+ -+struct ssb_mipscore { -+}; -+ -+static inline -+void ssb_mipscore_init(struct ssb_mipscore *mcore) -+{ -+} -+ -+#endif /* CONFIG_SSB_DRIVER_MIPS */ -+ -+#endif /* __KERNEL__ */ -+#endif /* LINUX_SSB_MIPSCORE_H_ */ -diff -urN linux.old/include/linux/ssb_driver_pci.h linux.dev/include/linux/ssb_driver_pci.h ---- linux.old/include/linux/ssb_driver_pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/ssb_driver_pci.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,35 @@ -+#ifndef LINUX_SSB_PCICORE_H_ -+#define LINUX_SSB_PCICORE_H_ -+#ifndef __KERNEL__ -+ -+ -+/* PCI core registers. */ -+#define SSB_PCICORE_CTL 0x0000 /* PCI Control */ -+#define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */ -+#define SSB_PCICORE_ISTAT 0x0020 /* Interrupt status */ -+#define SSB_PCICORE_IMASK 0x0024 /* Interrupt mask */ -+#define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */ -+#define SSB_PCICORE_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */ -+#define SSB_PCICORE_BCAST_DATA 0x0054 /* Backplane Broadcast Data */ -+#define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */ -+#define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */ -+#define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */ -+#define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */ -+#define SSB_PCICORE_TRANS0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */ -+#define SSB_PCICORE_TRANS1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */ -+#define SSB_PCICORE_TRANS2 0x0108 /* Backplane to PCI translation 2 (dbtopci2) */ -+#define SSB_PCICORE_TRANS2_MEM 0x00000000 -+#define SSB_PCICORE_TRANS2_IO 0x00000001 -+#define SSB_PCICORE_TRANS2_CFG0 0x00000002 -+#define SSB_PCICORE_TRANS2_CFG1 0x00000003 -+#define SSB_PCICORE_TRANS2_PREF 0x00000004 /* Prefetch enable */ -+#define SSB_PCICORE_TRANS2_BURST 0x00000008 /* Burst enable */ -+#define SSB_PCICORE_TRANS2_MRM 0x00000020 /* Memory Read Multiple */ -+#define SSB_PCICORE_TRANS2_MASK0 0xfc000000 -+#define SSB_PCICORE_TRANS2_MASK1 0xfc000000 -+#define SSB_PCICORE_TRANS2_MASK2 0xc0000000 -+ -+ -+ -+#endif /* __KERNEL__ */ -+#endif /* LINUX_SSB_PCICORE_H_ */ -diff -urN linux.old/include/linux/ssb.h linux.dev/include/linux/ssb.h ---- linux.old/include/linux/ssb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/ssb.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,263 @@ -+#ifndef LINUX_SSB_H_ -+#define LINUX_SSB_H_ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+ -+struct ssb_bus; -+struct ssb_driver; -+ -+ -+struct ssb_sprom_r1 { -+ u16 pci_spid; /* Subsystem Product ID for PCI */ -+ u16 pci_svid; /* Subsystem Vendor ID for PCI */ -+ u16 pci_pid; /* Product ID for PCI */ -+ u8 il0mac[6]; /* MAC address for 802.11b/g */ -+ u8 et0mac[6]; /* MAC address for Ethernet */ -+ u8 et1mac[6]; /* MAC address for 802.11a */ -+ u8 et0phyaddr:5; /* MII address for enet0 */ -+ u8 et1phyaddr:5; /* MII address for enet1 */ -+ u8 et0mdcport:1; /* MDIO for enet0 */ -+ u8 et1mdcport:1; /* MDIO for enet1 */ -+ u8 board_rev; /* Board revision */ -+ u8 country_code:4; /* Country Code */ -+ u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */ -+ u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */ -+ u16 pa0b0; -+ u16 pa0b1; -+ u16 pa0b2; -+ u16 pa1b0; -+ u16 pa1b1; -+ u16 pa1b2; -+ u8 gpio0; /* GPIO pin 0 */ -+ u8 gpio1; /* GPIO pin 1 */ -+ u8 gpio2; /* GPIO pin 2 */ -+ u8 gpio3; /* GPIO pin 3 */ -+ u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */ -+ u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */ -+ u8 itssi_a; /* Idle TSSI Target for A-PHY */ -+ u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ -+ u16 boardflags_lo; /* Boardflags (low 16 bits) */ -+ u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */ -+ u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */ -+ u8 oem[8]; /* OEM string (rev 1 only) */ -+}; -+ -+struct ssb_sprom_r2 { -+ u16 boardflags_hi; /* Boardflags (high 16 bits) */ -+ u8 maxpwr_a_lo; /* A-PHY Max Power Low */ -+ u8 maxpwr_a_hi; /* A-PHY Max Power High */ -+ u16 pa1lob0; /* A-PHY PA Low Settings */ -+ u16 pa1lob1; /* A-PHY PA Low Settings */ -+ u16 pa1lob2; /* A-PHY PA Low Settings */ -+ u16 pa1hib0; /* A-PHY PA High Settings */ -+ u16 pa1hib1; /* A-PHY PA High Settings */ -+ u16 pa1hib2; /* A-PHY PA High Settings */ -+ u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */ -+ u8 country_str[2]; /* Two char Country Code */ -+}; -+ -+struct ssb_sprom_r3 { -+ u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */ -+ u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */ -+ u32 ofdmahpo; /* A-PHY OFDM High Power Offset */ -+ u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */ -+ u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */ -+ u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */ -+ u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */ -+ u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */ -+ u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */ -+ u32 ofdmgpo; /* G-PHY OFDM Power Offset */ -+}; -+ -+struct ssb_sprom_r4 { -+ /* TODO */ -+}; -+ -+struct ssb_sprom { -+ u8 revision; -+ u8 crc; -+ /* The valid r# fields are selected by the "revision". -+ * Revision 3 and lower inherit from lower revisions. -+ */ -+ union { -+ struct { -+ struct ssb_sprom_r1 r1; -+ struct ssb_sprom_r2 r2; -+ struct ssb_sprom_r3 r3; -+ }; -+ struct ssb_sprom_r4 r4; -+ }; -+}; -+ -+ -+/* Core-ID values. */ -+#define SSB_DEV_CHIPCOMMON 0x800 -+#define SSB_DEV_ILINE20 0x801 -+#define SSB_DEV_SDRAM 0x803 -+#define SSB_DEV_PCI 0x804 -+#define SSB_DEV_MIPS 0x805 -+#define SSB_DEV_ETHERNET 0x806 -+#define SSB_DEV_V90 0x807 -+#define SSB_DEV_USB11_HOSTDEV 0x808 -+#define SSB_DEV_ADSL 0x809 -+#define SSB_DEV_ILINE100 0x80A -+#define SSB_DEV_IPSEC 0x80B -+#define SSB_DEV_PCMCIA 0x80D -+#define SSB_DEV_INTERNAL_MEM 0x80E -+#define SSB_DEV_MEMC_SDRAM 0x80F -+#define SSB_DEV_EXTIF 0x811 -+#define SSB_DEV_80211 0x812 -+#define SSB_DEV_MIPS_3302 0x816 -+#define SSB_DEV_USB11_HOST 0x817 -+#define SSB_DEV_USB11_DEV 0x818 -+#define SSB_DEV_USB20_HOST 0x819 -+#define SSB_DEV_USB20_DEV 0x81A -+#define SSB_DEV_SDIO_HOST 0x81B -+#define SSB_DEV_ROBOSWITCH 0x81C -+#define SSB_DEV_PARA_ATA 0x81D -+#define SSB_DEV_SATA_XORDMA 0x81E -+#define SSB_DEV_ETHERNET_GBIT 0x81F -+#define SSB_DEV_PCIE 0x820 -+#define SSB_DEV_MIMO_PHY 0x821 -+#define SSB_DEV_SRAM_CTRLR 0x822 -+#define SSB_DEV_MINI_MACPHY 0x823 -+#define SSB_DEV_ARM_1176 0x824 -+#define SSB_DEV_ARM_7TDMI 0x825 -+ -+/* Vendor-ID values */ -+#define SSB_VENDOR_BROADCOM 0x4243 -+ -+struct ssb_device_id { -+ u16 vendor; -+ u16 coreid; -+ u8 revision; -+}; -+#define SSB_DEVICE(_vendor, _coreid, _revision) \ -+ { .vendor = _vendor, .coreid = _coreid, .revision = _revision, } -+#define SSB_DEVTABLE_END \ -+ { 0, }, -+ -+#define SSB_ANY_VENDOR 0xFFFF -+#define SSB_ANY_ID 0xFFFF -+#define SSB_ANY_REV 0xFF -+ -+ -+struct ssb_device { -+ struct device dev; -+ struct ssb_bus *bus; -+ struct ssb_device_id id; -+ -+ u8 core_index; -+ u32 dma_routing; //FIXME assign this! move to bus? Use helper function? -+ unsigned int irq; -+ void *drvdata; -+}; -+#define dev_to_ssb_dev(_dev) container_of(_dev, struct ssb_device, dev) -+ -+static inline -+void ssb_set_drvdata(struct ssb_device *dev, void *data) -+{ -+ dev->drvdata = data; -+} -+static inline -+void * ssb_get_drvdata(struct ssb_device *dev) -+{ -+ return dev->drvdata; -+} -+ -+u16 ssb_read16(struct ssb_device *dev, u16 offset); -+u32 ssb_read32(struct ssb_device *dev, u16 offset); -+void ssb_write16(struct ssb_device *dev, u16 offset, u16 value); -+void ssb_write32(struct ssb_device *dev, u16 offset, u32 value); -+ -+ -+struct ssb_driver { -+ const char *name; -+ const struct ssb_device_id *id_table; -+ -+ int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id); -+ void (*remove)(struct ssb_device *dev); -+ int (*suspend)(struct ssb_device *dev, pm_message_t state); -+ int (*resume)(struct ssb_device *dev); -+ void (*shutdown)(struct ssb_device *dev); -+ -+ struct device_driver drv; -+}; -+#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) -+ -+extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); -+static inline int ssb_driver_register(struct ssb_driver *drv) -+{ -+ return __ssb_driver_register(drv, THIS_MODULE); -+} -+extern void ssb_driver_unregister(struct ssb_driver *drv); -+ -+ -+ -+ -+enum ssb_bustype { -+ SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */ -+ SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */ -+ //FIXME JTAG? -+}; -+ -+#include -+#include -+#include -+ -+struct ssb_bus { -+ enum ssb_bustype bustype; -+ struct pci_dev *host_pci; -+ void __iomem *mmio; -+ -+ u16 chip_id; -+ u16 chip_rev; -+ u8 chip_package; -+ struct ssb_sprom sprom; -+ -+ spinlock_t bar_lock; -+ struct ssb_device *mapped_device; -+ int nr_devices; -+ struct ssb_device devices[SSB_MAX_NR_CORES]; /* cores */ -+ -+ struct ssb_chipcommon chipco; -+ struct ssb_mipscore mipscore; -+ -+ int busnumber; -+ struct list_head list; -+}; -+ -+extern int ssb_bus_ssbbus_register(struct ssb_bus *bus, -+ unsigned long baseaddr, -+ void (*fill_sprom)(struct ssb_sprom *sprom)); -+extern int ssb_bus_pcibus_register(struct ssb_bus *bus, -+ struct pci_dev *host_pci); -+extern void ssb_bus_unregister(struct ssb_bus *bus); -+extern u32 ssb_clockspeed(struct ssb_bus *bus); -+ -+int ssb_core_is_enabled(struct ssb_device *dev); -+void ssb_core_enable(struct ssb_device *dev, u32 core_specific_flags); -+void ssb_core_disable(struct ssb_device *dev, u32 core_specific_flags); -+ -+static inline dma_addr_t ssb_dma_offset(struct ssb_device *dev) -+{ -+ switch(dev->bus->bustype) { -+ case SSB_BUSTYPE_SSB: -+ return 0; -+ case SSB_BUSTYPE_PCI: -+ return SSB_PCI_DMA; -+ } -+ return 0; -+} -+ -+ -+ -+#endif /* __KERNEL__ */ -+#endif /* LINUX_SSB_H_ */ -diff -urN linux.old/include/linux/ssb_regs.h linux.dev/include/linux/ssb_regs.h ---- linux.old/include/linux/ssb_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/linux/ssb_regs.h 2007-01-03 02:26:02.000000000 +0100 -@@ -0,0 +1,267 @@ -+#ifndef LINUX_SSB_REGS_H_ -+#define LINUX_SSB_REGS_H_ -+#ifdef __KERNEL__ -+ -+ -+/* SiliconBackplane Address Map. -+ * All regions may not exist on all chips. -+ */ -+#define SSB_SDRAM_BASE 0x00000000 /* Physical SDRAM */ -+#define SSB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ -+#define SSB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ -+#define SSB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -+#define SSB_ENUM_BASE 0x18000000 /* Enumeration space base */ -+#define SSB_ENUM_LIMIT 0x18010000 /* Enumeration space limit */ -+ -+#define SSB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ -+#define SSB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ -+ -+#define SSB_EXTIF_BASE 0x1f000000 /* External Interface region base address */ -+#define SSB_FLASH1 0x1fc00000 /* Flash Region 1 */ -+#define SSB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */ -+ -+#define SSB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ -+#define SSB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ -+#define SSB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */ -+#define SSB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */ -+#define SSB_EUART (SB_EXTIF_BASE + 0x00800000) -+#define SSB_LED (SB_EXTIF_BASE + 0x00900000) -+ -+ -+/* Enumeration space constants */ -+#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */ -+#define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE) -+ -+ -+/* mips address */ -+#define SSB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ -+ -+ -+/* SSB PCI config space registers. */ -+#define SSB_BAR0_WIN 0x80 /* Backplane address space 0 */ -+#define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */ -+#define SSB_SPROMCTL 0x88 /* SPROM control */ -+#define SSB_SPROMCTL_WE 0x10 /* SPROM write enable */ -+#define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */ -+#define SSB_PCI_IRQS 0x90 /* PCI interrupts */ -+#define SSB_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */ -+#define SSB_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */ -+#define SSB_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */ -+#define SSB_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */ -+#define SSB_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */ -+#define SSB_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ -+#define SSB_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ -+#define SSB_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ -+#define SSB_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ -+ -+ -+#define SSB_BAR0_MAX_RETRIES 50 -+ -+/* Silicon backplane configuration register definitions */ -+#define SSB_IPSFLAG 0x0F08 -+#define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */ -+#define SSB_IPSFLAG_IRQ1_SHIFT 0 -+#define SSB_IPSFLAG_IRQ2 0x00003F00 /* which sbflags get routed to mips interrupt 2 */ -+#define SSB_IPSFLAG_IRQ2_SHIFT 8 -+#define SSB_IPSFLAG_IRQ3 0x003F0000 /* which sbflags get routed to mips interrupt 3 */ -+#define SSB_IPSFLAG_IRQ3_SHIFT 16 -+#define SSB_IPSFLAG_IRQ4 0x3F000000 /* which sbflags get routed to mips interrupt 4 */ -+#define SSB_IPSFLAG_IRQ4_SHIFT 24 -+#define SSB_TPSFLAG 0x0F18 -+#define SSB_TPSFLAG_BPFLAG 0x0000003F /* Backplane flag # */ -+#define SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */ -+#define SSB_TMERRLOGA 0x0F48 -+#define SSB_TMERRLOG 0x0F50 -+#define SSB_ADMATCH3 0x0F60 -+#define SSB_ADMATCH2 0x0F68 -+#define SSB_ADMATCH1 0x0F70 -+#define SSB_IMSTATE 0x0F90 /* SB Initiator Agent State */ -+#define SSB_IMSTATE_PC 0x0000000f /* Pipe Count */ -+#define SSB_IMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ -+#define SSB_IMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */ -+#define SSB_IMSTATE_AP_TS 0x00000010 /* Use timeslices only */ -+#define SSB_IMSTATE_AP_TK 0x00000020 /* Use token only */ -+#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ -+#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ -+#define SSB_IMSTATE_TO 0x00040000 /* Timeout */ -+#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ -+#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ -+#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ -+#define SSB_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ -+#define SSB_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ -+#define SSB_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ -+#define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ -+#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ -+#define SSB_TMSLOW 0x0F98 /* SB Target State Low */ -+#define SSB_TMSLOW_RESET 0x00000001 /* Reset */ -+#define SSB_TMSLOW_REJECT 0x00000002 /* Reject */ -+#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */ -+#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ -+#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */ -+#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */ -+#define SSB_TMSHIGH 0x0F9C /* SB Target State High */ -+#define SSB_TMSHIGH_SERR 0x00000001 /* S-error */ -+#define SSB_TMSHIGH_INT 0x00000002 /* Interrupt */ -+#define SSB_TMSHIGH_BUSY 0x00000004 /* Busy */ -+#define SSB_TMSHIGH_TO 0x00000020 /* Timeout. Backplane rev >= 2.3 only */ -+#define SSB_TMSHIGH_COREFL 0x1FFF0000 /* Core specific flags */ -+#define SSB_TMSHIGH_COREFL_SHIFT 16 -+#define SSB_TMSHIGH_DMA64 0x10000000 /* 64bit DMA supported */ -+#define SSB_TMSHIGH_GCR 0x20000000 /* Gated Clock Request */ -+#define SSB_TMSHIGH_BISTF 0x40000000 /* BIST Failed */ -+#define SSB_TMSHIGH_BISTD 0x80000000 /* BIST Done */ -+#define SSB_BWA0 0x0FA0 -+#define SSB_IMCFGLO 0x0FA8 -+#define SSB_IMCFGLO_SERTO 0x00000007 /* Service timeout */ -+#define SSB_IMCFGLO_REQTO 0x00000070 /* Request timeout */ -+#define SSB_IMCFGLO_REQTO_SHIFT 4 -+#define SSB_IMCFGLO_CONNID 0x00FF0000 /* Connection ID */ -+#define SSB_IMCFGLO_CONNID_SHIFT 16 -+#define SSB_IMCFGHI 0x0FAC -+#define SSB_BCONFIG 0x0FC0 -+#define SSB_BSTATE 0x0FC8 -+#define SSB_ACTCFG 0x0FD8 -+#define SSB_FLAGST 0x0FE8 -+#define SSB_IDLOW 0x0FF8 -+#define SSB_IDLOW_CFGSP 0x00000003 /* Config Space */ -+#define SSB_IDLOW_ADDRNGE 0x00000038 /* Address Ranges supported */ -+#define SSB_IDLOW_ADDRNGE_SHIFT 3 -+#define SSB_IDLOW_SYNC 0x00000040 -+#define SSB_IDLOW_INITIATOR 0x00000080 -+#define SSB_IDLOW_MIBL 0x00000F00 /* Minimum Backplane latency */ -+#define SSB_IDLOW_MIBL_SHIFT 8 -+#define SSB_IDLOW_MABL 0x0000F000 /* Maximum Backplane latency */ -+#define SSB_IDLOW_MABL_SHIFT 12 -+#define SSB_IDLOW_TIF 0x00010000 /* This Initiator is first */ -+#define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */ -+#define SSB_IDLOW_CCW_SHIFT 18 -+#define SSB_IDLOW_TPT 0x00F00000 /* Target ports */ -+#define SSB_IDLOW_TPT_SHIFT 20 -+#define SSB_IDLOW_INITP 0x0F000000 /* Initiator ports */ -+#define SSB_IDLOW_INITP_SHIFT 24 -+#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */ -+#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */ -+#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */ -+#define SSB_IDHIGH 0x0FFC /* SB Identification High */ -+#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ -+#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */ -+#define SSB_IDHIGH_CC_SHIFT 4 -+#define SSB_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ -+#define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */ -+#define SSB_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ -+#define SSB_IDHIGH_VC_SHIFT 16 -+ -+/* SPROM shadow area. If not otherwise noted, fields are -+ * two bytes wide. Note that the SPROM can _only_ be read -+ * in two-byte quantinies. -+ */ -+#define SSB_SPROMSIZE_WORDS 64 -+#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16)) -+#define SSB_SPROM_BASE 0x1000 -+#define SSB_SPROM_REVISION 0x107E -+#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ -+#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ -+#define SSB_SPROM_REVISION_CRC_SHIFT 8 -+/* SPROM Revision 1 */ -+#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ -+#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ -+#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ -+#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ -+#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ -+#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ -+#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ -+#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ -+#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ -+#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 -+#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ -+#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ -+#define SSB_SPROM1_BINF 0x105C /* Board info */ -+#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ -+#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ -+#define SSB_SPROM1_BINF_CCODE_SHIFT 8 -+#define SSB_SPROM1_BINF_ANTA 0x3000 /* Available A-PHY antennas */ -+#define SSB_SPROM1_BINF_ANTA_SHIFT 12 -+#define SSB_SPROM1_BINF_ANTBG 0xC000 /* Available B-PHY antennas */ -+#define SSB_SPROM1_BINF_ANTBG_SHIFT 14 -+#define SSB_SPROM1_PA0B0 0x105E -+#define SSB_SPROM1_PA0B1 0x1060 -+#define SSB_SPROM1_PA0B2 0x1062 -+#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ -+#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ -+#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ -+#define SSB_SPROM1_GPIOA_P1_SHIFT 8 -+#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ -+#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ -+#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ -+#define SSB_SPROM1_GPIOB_P3_SHIFT 8 -+#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ -+#define SSB_SPROM1_MAXPWR_A 0x00FF /* A-PHY (in dBm Q5.2) */ -+#define SSB_SPROM1_MAXPWR_BG 0xFF00 /* B-PHY and G-PHY (in dBm Q5.2) */ -+#define SSB_SPROM1_MAXPWR_BG_SHIFT 8 -+#define SSB_SPROM1_PA1B0 0x106A -+#define SSB_SPROM1_PA1B1 0x106C -+#define SSB_SPROM1_PA1B2 0x106E -+#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ -+#define SSB_SPROM1_ITSSI_A 0x00FF /* A-PHY */ -+#define SSB_SPROM1_ITSSI_BG 0xFF00 /* B-PHY and G-PHY */ -+#define SSB_SPROM1_ITSSI_BG_SHIFT 8 -+#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ -+#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ -+#define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */ -+#define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */ -+#define SSB_SPROM1_AGAIN_BG_SHIFT 8 -+#define SSB_SPROM1_OEM 0x1076 /* 8 bytes OEM string (rev 1 only) */ -+/* SPROM Revision 2 (inherits from rev 1) */ -+#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ -+#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ -+#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ -+#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ -+#define SSB_SPROM2_MAXP_A_LO_SHIFT 8 -+#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ -+#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ -+#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ -+#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ -+#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ -+#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ -+#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ -+#define SSB_SPROM2_OPO_VALUE 0x00FF -+#define SSB_SPROM2_OPO_UNUSED 0xFF00 -+#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ -+/* SPROM Revision 3 (inherits from rev 2) */ -+#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ -+#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ -+#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ -+#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ -+#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ -+#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 -+#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ -+#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 -+#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ -+#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ -+#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ -+#define SSB_SPROM3_CCKPO_2M_SHIFT 4 -+#define SSB_SPROM3_CCKPO_55M 0x0F00 /* 5.5M Rate PO */ -+#define SSB_SPROM3_CCKPO_55M_SHIFT 8 -+#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */ -+#define SSB_SPROM3_CCKPO_11M_SHIFT 12 -+#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ -+ -+/* Values for SSB_SPROM1_BINF_CCODE */ -+enum { -+ SSB_SPROM1CCODE_WORLD = 0, -+ SSB_SPROM1CCODE_THAILAND, -+ SSB_SPROM1CCODE_ISRAEL, -+ SSB_SPROM1CCODE_JORDAN, -+ SSB_SPROM1CCODE_CHINA, -+ SSB_SPROM1CCODE_JAPAN, -+ SSB_SPROM1CCODE_USA_CANADA_ANZ, -+ SSB_SPROM1CCODE_EUROPE, -+ SSB_SPROM1CCODE_USA_LOW, -+ SSB_SPROM1CCODE_JAPAN_HIGH, -+ SSB_SPROM1CCODE_ALL, -+ SSB_SPROM1CCODE_NONE, -+}; -+ -+ -+#endif /* __KERNEL__ */ -+#endif /* LINUX_SSB_REGS_H_ */ + * Definitions for 7:0 on legacy processors + */ + +@@ -200,7 +207,9 @@ + #define CPU_SB1A 62 + #define CPU_74K 63 + #define CPU_R14000 64 +-#define CPU_LAST 64 ++#define CPU_BCM3302 65 ++#define CPU_BCM4710 66 ++#define CPU_LAST 66 + + /* + * ISA Level encodings +diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h +--- linux.old/include/linux/pci_ids.h 2007-01-26 00:51:33.000000000 +0100 ++++ linux.dev/include/linux/pci_ids.h 2007-01-25 23:34:01.000000000 +0100 +@@ -1981,6 +1981,7 @@ + #define PCI_DEVICE_ID_TIGON3_5906M 0x1713 + #define PCI_DEVICE_ID_BCM4401 0x4401 + #define PCI_DEVICE_ID_BCM4401B0 0x4402 ++#define PCI_DEVICE_ID_BCM4713 0x4713 + + #define PCI_VENDOR_ID_TOPIC 0x151f + #define PCI_DEVICE_ID_TOPIC_TP560 0x0000 +