X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/ac1c76183402522d64fa5608c9806b3e0d0ba1b9..a95e8602caad2e0fa7000656bcbf8204e558dd25:/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c?ds=sidebyside diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c index f27c171a6..ac94da986 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c @@ -1,7 +1,7 @@ /* * Atheros AR71xx PCI host controller driver * - * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008-2009 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * Parts of this file are based on Atheros' 2.6.15 BSP @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -36,11 +37,9 @@ #define PCI_IDSEL_BASE 0 #endif -static unsigned ar71xx_pci_nr_irqs; -static struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; static void __iomem *ar71xx_pcicfg_base; - static DEFINE_SPINLOCK(ar71xx_pci_lock); +static int ar71xx_pci_fixup_enable; static inline void ar71xx_pci_delay(void) { @@ -93,7 +92,7 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, return ret; } -static int __ar71xx_pci_be_handler(int is_fixup) +int ar71xx_pci_be_handler(int is_fixup) { u32 pci_err; u32 ahb_err; @@ -135,7 +134,7 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, ar71xx_pcicfg_wr(PCI_REG_CFG_CBE, cmd | ar71xx_pci_get_ble(where, size, 0)); - return __ar71xx_pci_be_handler(1); + return ar71xx_pci_be_handler(1); } static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, @@ -231,6 +230,9 @@ static void ar71xx_pci_fixup(struct pci_dev *dev) { u32 t; + if (!ar71xx_pci_fixup_enable) + return; + if (dev->bus->number != 0 || dev->devfn != 0) return; @@ -243,10 +245,10 @@ static void ar71xx_pci_fixup(struct pci_dev *dev) pci_write_config_word(dev, PCI_COMMAND, t); } - DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); -int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) +int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, + uint8_t pin) { int irq = -1; int i; @@ -274,11 +276,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) return irq; } -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - static struct pci_ops ar71xx_pci_ops = { .read = ar71xx_pci_read_config, .write = ar71xx_pci_write_config, @@ -304,8 +301,74 @@ static struct pci_controller ar71xx_pci_controller = { .io_resource = &ar71xx_pci_io_resource, }; -static int __init __ar71xx_pci_bios_init(unsigned nr_irqs, - struct ar71xx_pci_irq *map) +static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 pending; + + pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) & + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); + + if (pending & PCI_INT_DEV0) + generic_handle_irq(AR71XX_PCI_IRQ_DEV0); + + else if (pending & PCI_INT_DEV1) + generic_handle_irq(AR71XX_PCI_IRQ_DEV1); + + else if (pending & PCI_INT_DEV2) + generic_handle_irq(AR71XX_PCI_IRQ_DEV2); + + else if (pending & PCI_INT_CORE) + generic_handle_irq(AR71XX_PCI_IRQ_CORE); + + else + spurious_interrupt(); +} + +static void ar71xx_pci_irq_unmask(unsigned int irq) +{ + irq -= AR71XX_PCI_IRQ_BASE; + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static void ar71xx_pci_irq_mask(unsigned int irq) +{ + irq -= AR71XX_PCI_IRQ_BASE; + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static struct irq_chip ar71xx_pci_irq_chip = { + .name = "AR71XX PCI ", + .mask = ar71xx_pci_irq_mask, + .unmask = ar71xx_pci_irq_unmask, + .mask_ack = ar71xx_pci_irq_mask, +}; + +static void __init ar71xx_pci_irq_init(void) +{ + int i; + + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0); + ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0); + + for (i = AR71XX_PCI_IRQ_BASE; + i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); +} + +int __init ar71xx_pcibios_init(void) { ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); ar71xx_pci_delay(); @@ -316,32 +379,23 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs, ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); - ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS); - ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS); + ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS); ar71xx_pci_delay(); /* clear bus errors */ - (void)__ar71xx_pci_be_handler(1); - - ar71xx_pci_nr_irqs = nr_irqs; - ar71xx_pci_irq_map = map; - ar71xx_pci_be_handler = __ar71xx_pci_be_handler; + (void)ar71xx_pci_be_handler(1); + ar71xx_pci_fixup_enable = 1; + ar71xx_pci_irq_init(); register_pci_controller(&ar71xx_pci_controller); return 0; } - -static int __init __ar71xx_pci_init(void) -{ - ar71xx_pci_bios_init = __ar71xx_pci_bios_init; - return 0; -} -pure_initcall(__ar71xx_pci_init);