X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/b887a6d197170b719028f31085876d8deaed35b6..b1b7fcb8bd1fd7c4bfebbb94ed5087e1856e104e:/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c
index 168b2390b..fcac2dd86 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c
@@ -16,6 +16,7 @@
 #include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
 
+#include <asm/mach-ralink/common.h>
 #include <asm/mach-ralink/rt305x.h>
 #include <asm/mach-ralink/rt305x_regs.h>
 
@@ -23,7 +24,7 @@ static void rt305x_intc_irq_dispatch(void)
 {
 	u32 pending;
 
-	pending = rt305x_intc_rr(INTC_REG_STATUS0);
+	pending = ramips_intc_get_status();
 
 	if (pending & RT305X_INTC_INT_TIMER0)
 		do_IRQ(RT305X_INTC_IRQ_TIMER0);
@@ -37,58 +38,18 @@ static void rt305x_intc_irq_dispatch(void)
 	else if (pending & RT305X_INTC_INT_UART1)
 		do_IRQ(RT305X_INTC_IRQ_UART1);
 
+	else if (pending &  RT305X_INTC_INT_PERFC)
+		do_IRQ(RT305X_INTC_IRQ_PERFC);
+
+	else if (pending & RT305X_INTC_INT_OTG)
+		do_IRQ(RT305X_INTC_IRQ_OTG);
+
 	/* TODO: handle PIO interrupts as well */
 
 	else
 		spurious_interrupt();
 }
 
-static void rt305x_intc_irq_unmask(unsigned int irq)
-{
-	irq -= RT305X_INTC_IRQ_BASE;
-	rt305x_intc_wr((1 << irq), INTC_REG_ENABLE);
-}
-
-static void rt305x_intc_irq_mask(unsigned int irq)
-{
-	irq -= RT305X_INTC_IRQ_BASE;
-	rt305x_intc_wr((1 << irq), INTC_REG_DISABLE);
-}
-
-struct irq_chip rt305x_intc_irq_chip = {
-	.name		= "RT305X INTC",
-	.unmask		= rt305x_intc_irq_unmask,
-	.mask		= rt305x_intc_irq_mask,
-	.mask_ack	= rt305x_intc_irq_mask,
-};
-
-static struct irqaction rt305x_intc_irqaction = {
-	.handler	= no_action,
-	.name		= "cascade [RT305X INTC]",
-};
-
-static void __init rt305x_intc_irq_init(void)
-{
-	int i;
-
-	/* disable all interrupts */
-	rt305x_intc_wr(~0, INTC_REG_DISABLE);
-
-	/* route all INTC interrupts to MIPS HW0 interrupt */
-	rt305x_intc_wr(0, INTC_REG_TYPE);
-
-	for (i = RT305X_INTC_IRQ_BASE;
-	     i < RT305X_INTC_IRQ_BASE + RT305X_INTC_IRQ_COUNT; i++) {
-		set_irq_chip_and_handler(i, &rt305x_intc_irq_chip,
-					 handle_level_irq);
-	}
-
-	setup_irq(RT305X_CPU_IRQ_INTC, &rt305x_intc_irqaction);
-
-	/* enable interrupt masking */
-	rt305x_intc_wr(RT305X_INTC_INT_GLOBAL, INTC_REG_ENABLE);
-}
-
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned long pending;
@@ -114,5 +75,8 @@ asmlinkage void plat_irq_dispatch(void)
 void __init arch_init_irq(void)
 {
 	mips_cpu_irq_init();
-	rt305x_intc_irq_init();
+	ramips_intc_irq_init(RT305X_INTC_BASE, RT305X_CPU_IRQ_INTC,
+			     RT305X_INTC_IRQ_BASE);
+
+	cp0_perfcount_irq = RT305X_INTC_IRQ_PERFC;
 }