X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/c5552ad03973839d83d32d7108f20c00f192633b..c4174021acc57c9d482e4496733352bcac5a0d13:/target/linux/generic/patches-2.6.33/975-ssb_update.patch

diff --git a/target/linux/generic/patches-2.6.33/975-ssb_update.patch b/target/linux/generic/patches-2.6.33/975-ssb_update.patch
index fbc8f517b..e994a8a50 100644
--- a/target/linux/generic/patches-2.6.33/975-ssb_update.patch
+++ b/target/linux/generic/patches-2.6.33/975-ssb_update.patch
@@ -1,15 +1,6 @@
 --- a/drivers/ssb/driver_chipcommon.c
 +++ b/drivers/ssb/driver_chipcommon.c
-@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
- {
- 	if (!cc->dev)
- 		return; /* We don't have a ChipCommon */
-+	if (cc->dev->id.revision >= 11)
-+		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
- 	ssb_pmu_init(cc);
- 	chipco_powercontrol_init(cc);
- 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
-@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
+@@ -373,6 +373,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
  {
  	return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
  }
@@ -124,70 +115,6 @@
  	}
  
  	return err;
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -167,7 +167,7 @@ err_pci:
- }
- 
- /* Get the word-offset for a SSB_SPROM_XXX define. */
--#define SPOFF(offset)	(((offset) - SSB_SPROM_BASE) / sizeof(u16))
-+#define SPOFF(offset)	((offset) / sizeof(u16))
- /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
- #define SPEX16(_outvar, _offset, _mask, _shift)	\
- 	out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
-@@ -253,7 +253,7 @@ static int sprom_do_read(struct ssb_bus 
- 	int i;
- 
- 	for (i = 0; i < bus->sprom_size; i++)
--		sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
-+		sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
- 
- 	return 0;
- }
-@@ -284,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
- 			ssb_printk("75%%");
- 		else if (i % 2)
- 			ssb_printk(".");
--		writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
-+		writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
- 		mmiowb();
- 		msleep(20);
- 	}
-@@ -620,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
- 	int err = -ENOMEM;
- 	u16 *buf;
- 
-+	if (!ssb_is_sprom_available(bus)) {
-+		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
-+		return -ENODEV;
-+	}
-+
-+	bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
-+		SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
-+
- 	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
- 	if (!buf)
- 		goto out;
---- a/drivers/ssb/sprom.c
-+++ b/drivers/ssb/sprom.c
-@@ -175,3 +175,17 @@ const struct ssb_sprom *ssb_get_fallback
- {
- 	return fallback_sprom;
- }
-+
-+/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
-+bool ssb_is_sprom_available(struct ssb_bus *bus)
-+{
-+	/* status register only exists on chipcomon rev >= 11 and we need check
-+	   for >= 31 only */
-+	/* this routine differs from specs as we do not access SPROM directly
-+	   on PCMCIA */
-+	if (bus->bustype == SSB_BUSTYPE_PCI &&
-+	    bus->chipco.dev->id.revision >= 31)
-+		return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
-+
-+	return true;
-+}
 --- a/drivers/ssb/ssb_private.h
 +++ b/drivers/ssb/ssb_private.h
 @@ -196,7 +196,7 @@ extern int ssb_devices_thaw(struct ssb_f
@@ -207,29 +134,9 @@
 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
  
  #endif /* LINUX_SSB_PRIVATE_H_ */
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -305,6 +305,7 @@ struct ssb_bus {
- 	/* ID information about the Chip. */
- 	u16 chip_id;
- 	u16 chip_rev;
-+	u16 sprom_offset;
- 	u16 sprom_size;		/* number of words in sprom */
- 	u8 chip_package;
- 
-@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
- 
- extern void ssb_bus_unregister(struct ssb_bus *bus);
- 
-+/* Does the device have an SPROM? */
-+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
-+
- /* Set a fallback SPROM.
-  * See kdoc at the function definition for complete documentation. */
- extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
 --- a/include/linux/ssb/ssb_driver_chipcommon.h
 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
-@@ -53,6 +53,7 @@
+@@ -54,6 +54,7 @@
  #define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
  #define  SSB_CHIPCO_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
  #define  SSB_CHIPCO_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
@@ -237,7 +144,7 @@
  #define SSB_CHIPCO_CORECTL		0x0008
  #define  SSB_CHIPCO_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
  #define	 SSB_CHIPCO_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
-@@ -385,6 +386,7 @@
+@@ -386,6 +387,7 @@
  
  
  /** Chip specific Chip-Status register contents. */
@@ -245,7 +152,7 @@
  #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL	0x00000003
  #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL		0 /* OTP is powered up, use def. CIS, no SPROM */
  #define SSB_CHIPCO_CHST_4325_SPROM_SEL		1 /* OTP is powered up, SPROM is present */
-@@ -398,6 +400,18 @@
+@@ -399,6 +401,18 @@
  #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT	4
  #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 		0x00000200 /* 1 for 2b, 0 for to 2a */
  
@@ -264,27 +171,9 @@
  
  
  /** Clockcontrol masks and values **/
-@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
- struct ssb_chipcommon {
- 	struct ssb_device *dev;
- 	u32 capabilities;
-+	u32 status;
- 	/* Fast Powerup Delay constant */
- 	u16 fast_pwrup_delay;
- 	struct ssb_chipcommon_pmu pmu;
 --- a/include/linux/ssb/ssb_regs.h
 +++ b/include/linux/ssb/ssb_regs.h
-@@ -170,26 +170,27 @@
- #define SSB_SPROMSIZE_WORDS_R4		220
- #define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
- #define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
--#define SSB_SPROM_BASE			0x1000
--#define SSB_SPROM_REVISION		0x107E
-+#define SSB_SPROM_BASE1			0x1000
-+#define SSB_SPROM_BASE31		0x0800
-+#define SSB_SPROM_REVISION		0x007E
- #define  SSB_SPROM_REVISION_REV		0x00FF	/* SPROM Revision number */
- #define  SSB_SPROM_REVISION_CRC		0xFF00	/* SPROM CRC8 value */
+@@ -178,19 +178,19 @@
  #define  SSB_SPROM_REVISION_CRC_SHIFT	8
  
  /* SPROM Revision 1 */
@@ -312,7 +201,7 @@
  #define  SSB_SPROM1_BINF_BREV		0x00FF	/* Board Revision */
  #define  SSB_SPROM1_BINF_CCODE		0x0F00	/* Country Code */
  #define  SSB_SPROM1_BINF_CCODE_SHIFT	8
-@@ -197,63 +198,63 @@
+@@ -198,63 +198,63 @@
  #define  SSB_SPROM1_BINF_ANTBG_SHIFT	12
  #define  SSB_SPROM1_BINF_ANTA		0xC000	/* Available A-PHY antennas */
  #define  SSB_SPROM1_BINF_ANTA_SHIFT	14
@@ -404,7 +293,7 @@
  #define  SSB_SPROM3_CCKPO_1M		0x000F	/* 1M Rate PO */
  #define  SSB_SPROM3_CCKPO_2M		0x00F0	/* 2M Rate PO */
  #define  SSB_SPROM3_CCKPO_2M_SHIFT	4
-@@ -264,100 +265,100 @@
+@@ -265,100 +265,100 @@
  #define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
  
  /* SPROM Revision 4 */
@@ -562,7 +451,7 @@
  #define  SSB_SPROM8_RSSISMF2G		0x000F
  #define  SSB_SPROM8_RSSISMC2G		0x00F0
  #define  SSB_SPROM8_RSSISMC2G_SHIFT	4
-@@ -365,7 +366,7 @@
+@@ -366,7 +366,7 @@
  #define  SSB_SPROM8_RSSISAV2G_SHIFT	8
  #define  SSB_SPROM8_BXA2G		0x1800
  #define  SSB_SPROM8_BXA2G_SHIFT		11
@@ -571,7 +460,7 @@
  #define  SSB_SPROM8_RSSISMF5G		0x000F
  #define  SSB_SPROM8_RSSISMC5G		0x00F0
  #define  SSB_SPROM8_RSSISMC5G_SHIFT	4
-@@ -373,47 +374,47 @@
+@@ -374,47 +374,47 @@
  #define  SSB_SPROM8_RSSISAV5G_SHIFT	8
  #define  SSB_SPROM8_BXA5G		0x1800
  #define  SSB_SPROM8_BXA5G_SHIFT		11