X-Git-Url: http://git.rohieb.name/openwrt.git/blobdiff_plain/fd3222baa48c89bad08cd33b0b8a6dc8956b0806..c0734b8ffe25732738199a03407289ffb450bf0c:/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c index b1f5fa9ee..bf8e36952 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c @@ -110,8 +110,11 @@ static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, * WAR for BAR issue - We are unable to access the PCI device space * if we set the BAR with proper base address */ - if ((where == 0x10) && (size == 4)) - ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff); + if ((where == 0x10) && (size == 4)) { + u32 val; + val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff; + ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val); + } return PCIBIOS_SUCCESSFUL; } @@ -237,7 +240,11 @@ static int __init ar724x_pci_setup(void) udelay(100000); } - __raw_writel(AR724X_PCI_APP_LTSSM_ENABLE, base + AR724X_PCI_REG_APP); + if (ar71xx_soc == AR71XX_SOC_AR7240) + t = AR724X_PCI_APP_LTSSM_ENABLE; + else + t = 0x1ffc1; + __raw_writel(t, base + AR724X_PCI_REG_APP); /* flush write */ (void) __raw_readl(base + AR724X_PCI_REG_APP); udelay(1000); @@ -248,7 +255,8 @@ static int __init ar724x_pci_setup(void) return -ENODEV; } - if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { + if (ar71xx_soc == AR71XX_SOC_AR7241 || + ar71xx_soc == AR71XX_SOC_AR7242) { t = __raw_readl(base + AR724X_PCI_REG_APP); t |= BIT(16); __raw_writel(t, base + AR724X_PCI_REG_APP); @@ -376,12 +384,12 @@ int __init ar724x_pcibios_init(void) return 0; - err_unmap_ctrl: +err_unmap_ctrl: iounmap(ar724x_pci_ctrl_base); - err_unmap_devcfg: +err_unmap_devcfg: iounmap(ar724x_pci_devcfg_base); - err_unmap_localcfg: +err_unmap_localcfg: iounmap(ar724x_pci_localcfg_base); - err: +err: return ret; }