core/usbcdc/usbreg.h

   1 /*----------------------------------------------------------------------------
   2  *      U S B  -  K e r n e l
   3  *----------------------------------------------------------------------------
   4  *      Name:    USBREG.H
   5  *      Purpose: USB Hardware Layer Definitions for NXP LPC13xx
   6  *      Version: V1.20
   7  *----------------------------------------------------------------------------
   8  *      This software is supplied "AS IS" without any warranties, express,
   9  *      implied or statutory, including but not limited to the implied
  10  *      warranties of fitness for purpose, satisfactory quality and
  11  *      noninfringement. Keil extends you a royalty-free right to reproduce
  12  *      and distribute executable files created using this software for use
  13  *      on NXP Semiconductors LPC microcontroller devices only. Nothing else
  14  *      gives you the right to use this software.
  15  *
  16  * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
  17  *---------------------------------------------------------------------------*/
  18
  19 #ifndef __USBREG_H
  20 #define __USBREG_H
  21
  22 /* Device Interrupt Bit Definitions */
  23 #define FRAME_INT           (0x1<<0)
  24 #define EP0_INT             (0x1<<1)
  25 #define EP1_INT             (0x1<<2)
  26 #define EP2_INT             (0x1<<3)
  27 #define EP3_INT             (0x1<<4)
  28 #define EP4_INT             (0x1<<5)
  29 #define EP5_INT             (0x1<<6)
  30 #define EP6_INT             (0x1<<7)
  31 #define EP7_INT             (0x1<<8)
  32 #define DEV_STAT_INT        (0x1<<9)
  33 #define CCEMTY_INT          (0x1<<10)
  34 #define CDFULL_INT          (0x1<<11)
  35 #define RxENDPKT_INT        (0x1<<12)
  36 #define TxENDPKT_INT        (0x1<<13)
  37
  38 /* Rx & Tx Packet Length Definitions */
  39 #define PKT_LNGTH_MASK      0x000003FF
  40 #define PKT_DV              0x00000400
  41 #define PKT_RDY             0x00000800
  42
  43 /* USB Control Definitions */
  44 #define CTRL_RD_EN          0x00000001
  45 #define CTRL_WR_EN          0x00000002
  46
  47 /* Command Codes */
  48 #define CMD_SET_ADDR        0x00D00500
  49 #define CMD_CFG_DEV         0x00D80500
  50 #define CMD_SET_MODE        0x00F30500
  51 #define CMD_RD_INT          0x00F40500
  52 #define DAT_RD_INT          0x00F40200
  53 #define CMD_RD_FRAME        0x00F50500
  54 #define DAT_RD_FRAME        0x00F50200
  55 #define CMD_RD_CHIP_ID      0x00FD0500
  56 #define DAT_RD_CHIP_ID      0x00FD0200
  57
  58 #define CMD_SET_DEV_STAT    0x00FE0500
  59 #define CMD_GET_DEV_STAT    0x00FE0500
  60 #define DAT_GET_DEV_STAT    0x00FE0200
  61 #define CMD_GET_ERR_CODE    0x00FF0500
  62 #define DAT_GET_ERR_CODE    0x00FF0200
  63
  64 #define DAT_WR_BYTE(x)     (0x00000100 | ((x) << 16))
  65 #define CMD_SEL_EP(x)      (0x00000500 | ((x) << 16))
  66 #define DAT_SEL_EP(x)      (0x00000200 | ((x) << 16))
  67 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
  68 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
  69 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
  70 #define CMD_CLR_BUF         0x00F20500
  71 #define CMD_VALID_BUF       0x00FA0500
  72
  73 /* Device Address Register Definitions */
  74 #define DEV_ADDR_MASK       0x7F
  75 #define DEV_EN              0x80
  76
  77 /* Device Configure Register Definitions */
  78 #define CONF_DVICE          0x01
  79
  80 /* Device Mode Register Definitions */
  81 #define AP_CLK              0x01
  82 #define INAK_CI             0x02
  83 #define INAK_CO             0x04
  84 #define INAK_AI             0x08
  85 #define INAK_AO             0x10
  86
  87 /* Device Status Register Definitions */
  88 #define DEV_CON             0x01
  89 #define DEV_CON_CH          0x02
  90 #define DEV_SUS             0x04
  91 #define DEV_SUS_CH          0x08
  92 #define DEV_RST             0x10
  93
  94 /* Error Code Register Definitions */
  95 #define ERR_EC_MASK         0x0F
  96 #define ERR_EA              0x10
  97
  98 /* Error Status Register Definitions */
  99 #define ERR_NOERROR                     0x00
 100 #define ERR_PID_ENCODE      0x01
 101 #define ERR_UNKNOWN_PID     0x02
 102 #define ERR_UNEXPECT_PKT    0x03
 103 #define ERR_TCRC            0x04
 104 #define ERR_DCRC            0x05
 105 #define ERR_TIMEOUT         0x06
 106 #define ERR_BABBIE          0x07
 107 #define ERR_EOF_PKT         0x08
 108 #define ERR_TX_RX_NAK           0x09
 109 #define ERR_SENT_STALL      0x0A
 110 #define ERR_BUF_OVERRUN     0x0B
 111 #define ERR_SENT_EPT_PKT    0x0C
 112 #define ERR_BIT_STUFF       0x0D
 113 #define ERR_SYNC            0x0E
 114 #define ERR_TOGGLE_BIT      0x0F
 115
 116 /* Endpoint Select Register Definitions */
 117 #define EP_SEL_F            0x01
 118 #define EP_SEL_ST           0x02
 119 #define EP_SEL_STP          0x04
 120 #define EP_SEL_PO           0x08
 121 #define EP_SEL_EPN          0x10
 122 #define EP_SEL_B_1_FULL     0x20
 123 #define EP_SEL_B_2_FULL     0x40
 124
 125 /* Endpoint Status Register Definitions */
 126 #define EP_STAT_ST          0x01
 127 #define EP_STAT_DA          0x20
 128 #define EP_STAT_RF_MO       0x40
 129 #define EP_STAT_CND_ST      0x80
 130
 131 /* Clear Buffer Register Definitions */
 132 #define CLR_BUF_PO          0x01
 133
 134 #endif  /* __USBREG_H */