a7154e18baf76cece7fb0ae510e07998555fd643
[hackover2013-badge-firmware.git] / core / gpio / gpio.c
1 /**************************************************************************/
2 /*!
3 @file gpio.c
4 @author K. Townsend (microBuilder.eu)
5 @date 22 March 2010
6 @version 0.10
7
8 @section DESCRIPTION
9
10 Controls the general purpose digital IO.
11
12 @section LICENSE
13
14 Software License Agreement (BSD License)
15
16 Copyright (c) 2010, microBuilder SARL
17 All rights reserved.
18
19 Redistribution and use in source and binary forms, with or without
20 modification, are permitted provided that the following conditions are met:
21 1. Redistributions of source code must retain the above copyright
22 notice, this list of conditions and the following disclaimer.
23 2. Redistributions in binary form must reproduce the above copyright
24 notice, this list of conditions and the following disclaimer in the
25 documentation and/or other materials provided with the distribution.
26 3. Neither the name of the copyright holders nor the
27 names of its contributors may be used to endorse or promote products
28 derived from this software without specific prior written permission.
29
30 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
31 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
34 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41 /**************************************************************************/
42
43 #include "gpio.h"
44
45 #ifdef CFG_CHIBI
46 #include "drivers/rf/chibi/chb_drvr.h"
47 volatile uint32_t chibi_counter = 0;
48 #endif
49
50 #ifdef CFG_ALTRESET
51 #include "core/cpu/cpu.h"
52 #endif
53
54 static bool _gpioInitialised = false;
55
56 /**************************************************************************/
57 /*!
58 @brief IRQ Handler for GPIO port 0 (currently checks pin 0.1)
59
60 @note By default, this IRQ handler is probably disabled in
61 projectconfig.h (see GPIO_ENABLE_IRQ0), but you can use
62 the code below as a model to implement this interrupt
63 handler in an appropriate place in your project.
64 */
65 /**************************************************************************/
66 #if defined GPIO_ENABLE_IRQ0
67 void PIOINT0_IRQHandler(void)
68 {
69 uint32_t regVal;
70
71 regVal = gpioIntStatus(0, 1);
72 if (regVal)
73 {
74 gpioIntClear(0, 1);
75 }
76 return;
77 }
78 #endif
79
80 /**************************************************************************/
81 /*!
82 @brief IRQ Handler for GPIO port 1 (currently checks pin 1.1)
83 */
84 /**************************************************************************/
85 #if defined GPIO_ENABLE_IRQ1
86 void PIOINT1_IRQHandler(void)
87 {
88 uint32_t regVal;
89
90 #if defined CFG_ALTRESET && CFG_ALTRESET_PORT == 1
91 regVal = gpioIntStatus(CFG_ALTRESET_PORT, CFG_ALTRESET_PIN);
92 if (regVal)
93 {
94 // Cause a reset and wait
95 cpuReset();
96 }
97 #endif
98
99 #ifdef CFG_CHIBI
100 // Check for interrupt on 1.8
101 regVal = gpioIntStatus(1, 8);
102 if (regVal)
103 {
104 chibi_counter++;
105 chb_ISR_Handler();
106 gpioIntClear(1, 8);
107 }
108 #else
109 regVal = gpioIntStatus(1, 1);
110 if ( regVal )
111 {
112 gpioIntClear(1, 1);
113 }
114 #endif
115
116 return;
117 }
118 #endif
119
120 /**************************************************************************/
121 /*!
122 @brief IRQ Handler for GPIO port 2 (currently checks pin 2.1)
123
124 @note By default, this IRQ handler is probably disabled in
125 projectconfig.h (see GPIO_ENABLE_IRQ2), but you can use
126 the code below as a model to implement this interrupt
127 handler in an appropriate place in your project.
128 */
129 /**************************************************************************/
130 #if defined GPIO_ENABLE_IRQ2
131 void PIOINT2_IRQHandler(void)
132 {
133 uint32_t regVal;
134
135 regVal = gpioIntStatus(2, 1);
136 if ( regVal )
137 {
138 gpioIntClear(2, 1);
139 }
140 return;
141 }
142 #endif
143
144 /**************************************************************************/
145 /*!
146 @brief IRQ Handler for GPIO port 3 (currently checks pin 3.1)
147
148 @note By default, this IRQ handler is probably disabled in
149 projectconfig.h (see GPIO_ENABLE_IRQ3), but you can use
150 the code below as a model to implement this interrupt
151 handler in an appropriate place in your project.
152 */
153 /**************************************************************************/
154 #if defined GPIO_ENABLE_IRQ3
155 void PIOINT3_IRQHandler(void)
156 {
157 uint32_t regVal;
158
159 regVal = gpioIntStatus(3, 1);
160 if ( regVal )
161 {
162 gpioIntClear(3, 1);
163 }
164 return;
165 }
166 #endif
167
168 /**************************************************************************/
169 /*!
170 @brief Initialises GPIO and enables the GPIO interrupt
171 handler for all GPIO ports.
172 */
173 /**************************************************************************/
174 void gpioInit (void)
175 {
176 /* Enable AHB clock to the GPIO domain. */
177 SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_GPIO);
178
179 /* Set up NVIC when I/O pins are configured as external interrupts. */
180 NVIC_EnableIRQ(EINT0_IRQn);
181 NVIC_EnableIRQ(EINT1_IRQn);
182 NVIC_EnableIRQ(EINT2_IRQn);
183 NVIC_EnableIRQ(EINT3_IRQn);
184
185 /* Set initialisation flag */
186 _gpioInitialised = true;
187
188 return;
189 }
190
191 /**************************************************************************/
192 /*!
193 @brief Sets the direction (input/output) for a specific port pin
194
195 @param[in] portNum
196 The port number (0..3)
197 @param[in] bitPos
198 The bit position (0..11)
199 @param[in] dir
200 The pin direction (gpioDirection_Input or
201 gpioDirection_Output)
202 */
203 /**************************************************************************/
204 void gpioSetDir (uint32_t portNum, uint32_t bitPos, gpioDirection_t dir)
205 {
206 if (!_gpioInitialised) gpioInit();
207
208 // Get the appropriate register (handled this way to optimise code size)
209 REG32 *gpiodir = &GPIO_GPIO0DIR;
210 switch (portNum)
211 {
212 case 0:
213 gpiodir = &GPIO_GPIO0DIR;
214 break;
215 case 1:
216 gpiodir = &GPIO_GPIO1DIR;
217 break;
218 case 2:
219 gpiodir = &GPIO_GPIO2DIR;
220 break;
221 case 3:
222 gpiodir = &GPIO_GPIO3DIR;
223 break;
224 }
225
226 // Toggle dir
227 dir == gpioDirection_Output ? (*gpiodir |= (1 << bitPos)) : (*gpiodir &= ~(1 << bitPos));
228 }
229
230 /**************************************************************************/
231 /*!
232 @brief Gets the value for a specific port pin
233
234 @param[in] portNum
235 The port number (0..3)
236 @param[in] bitPos
237 The bit position (0..31)
238
239 @return The current value for the specified port pin (0..1)
240 */
241 /**************************************************************************/
242 uint32_t gpioGetValue (uint32_t portNum, uint32_t bitPos)
243 {
244 if (!_gpioInitialised) gpioInit();
245
246 uint32_t value = 0;
247
248 switch (portNum)
249 {
250 case 0:
251 value = (GPIO_GPIO0DATA & (1 << bitPos)) ? 1 : 0;
252 break;
253 case 1:
254 value = (GPIO_GPIO1DATA & (1 << bitPos)) ? 1 : 0;
255 break;
256 case 2:
257 value = (GPIO_GPIO2DATA & (1 << bitPos)) ? 1 : 0;
258 break;
259 case 3:
260 value = (GPIO_GPIO3DATA & (1 << bitPos)) ? 1 : 0;
261 break;
262 default:
263 break;
264 }
265
266 return value;
267 }
268
269 /**************************************************************************/
270 /*!
271 @brief Sets the value for a specific port pin (only relevant when a
272 pin is configured as output).
273
274 @param[in] portNum
275 The port number (0..3)
276 @param[in] bitPos
277 The bit position (0..31)
278 @param[in] bitValue
279 The value to set for the specified bit (0..1). 0 will set
280 the pin low and 1 will set the pin high.
281 */
282 /**************************************************************************/
283 void gpioSetValue (uint32_t portNum, uint32_t bitPos, uint32_t bitVal)
284 {
285 if (!_gpioInitialised) gpioInit();
286
287 // Get the appropriate register (handled this way to optimise code size)
288 REG32 *gpiodata = &GPIO_GPIO0DATA;
289 switch (portNum)
290 {
291 case 0:
292 gpiodata = &GPIO_GPIO0DATA;
293 break;
294 case 1:
295 gpiodata = &GPIO_GPIO1DATA;
296 break;
297 case 2:
298 gpiodata = &GPIO_GPIO2DATA;
299 break;
300 case 3:
301 gpiodata = &GPIO_GPIO3DATA;
302 break;
303 }
304
305 // Toggle value
306 bitVal == 1 ? (*gpiodata |= (1 << bitPos)) : (*gpiodata &= ~(1 << bitPos));
307 }
308
309 /**************************************************************************/
310 /*!
311 @brief Sets the interrupt sense, event, etc.
312
313 @param[in] portNum
314 The port number (0..3)
315 @param[in] bitPos
316 The bit position (0..31)
317 @param[in] sense
318 Whether the interrupt should be configured as edge or level
319 sensitive.
320 @param[in] edge
321 Whether one edge or both trigger an interrupt.
322 @param[in] event
323 Whether the rising or the falling edge (high or low)
324 should be used to trigger the interrupt.
325
326 @section Example
327
328 @code
329 // Initialise gpio
330 gpioInit();
331 // Set GPIO1.8 to input
332 gpioSetDir(1, 8, gpioDirection_Input);
333 // Disable the internal pullup/down resistor on P1.8
334 gpioSetPullup (&IOCON_PIO1_8, gpioPullupMode_Inactive);
335 // Setup an interrupt on GPIO1.8
336 gpioSetInterrupt(1, // Port
337 8, // Pin
338 gpioInterruptSense_Edge, // Edge/Level Sensitive
339 gpioInterruptEdge_Single, // Single/Double Edge
340 gpioInterruptEvent_ActiveHigh); // Rising/Falling
341 // Enable the interrupt
342 gpioIntEnable(1, 8);
343 @endcode
344 */
345 /**************************************************************************/
346 void gpioSetInterrupt (uint32_t portNum, uint32_t bitPos, gpioInterruptSense_t sense, gpioInterruptEdge_t edge, gpioInterruptEvent_t event)
347 {
348 if (!_gpioInitialised) gpioInit();
349
350 // Get the appropriate register (handled this way to optimise code size)
351 REG32 *gpiois = &GPIO_GPIO0IS; // Interrupt sense (edge or level sensitive)
352 REG32 *gpioibe = &GPIO_GPIO0IBE; // Interrupt both edges (0 = int controlled by GPIOIEV, 1 = both edges trigger interrupt)
353 REG32 *gpioiev = &GPIO_GPIO0IEV; // 0 = falling edge or low, 1 = rising edge or high (depending on GPIOIS)
354 switch (portNum)
355 {
356 case 0:
357 gpiois = &GPIO_GPIO0IS;
358 gpioibe = &GPIO_GPIO0IBE;
359 gpioiev = &GPIO_GPIO0IEV;
360 break;
361 case 1:
362 gpiois = &GPIO_GPIO1IS;
363 gpioibe = &GPIO_GPIO1IBE;
364 gpioiev = &GPIO_GPIO1IEV;
365 break;
366 case 2:
367 gpiois = &GPIO_GPIO2IS;
368 gpioibe = &GPIO_GPIO2IBE;
369 gpioiev = &GPIO_GPIO2IEV;
370 break;
371 case 3:
372 gpiois = &GPIO_GPIO3IS;
373 gpioibe = &GPIO_GPIO3IBE;
374 gpioiev = &GPIO_GPIO3IEV;
375 break;
376 }
377
378 if (sense == gpioInterruptSense_Edge)
379 {
380 *gpiois &= ~(0x1<<bitPos);
381 edge == gpioInterruptEdge_Single ? (*gpioibe &= ~(0x1<<bitPos)) : (*gpioibe |= (0x1<<bitPos));
382 }
383 else
384 {
385 *gpiois |= (0x1<<bitPos);
386 }
387
388 event == gpioInterruptEvent_ActiveHigh ? (*gpioiev &= ~(0x1<<bitPos)) : (*gpioiev |= (0x1<<bitPos));
389
390 return;
391 }
392
393 /**************************************************************************/
394 /*!
395 @brief Enables the interrupt mask for a specific port pin
396
397 @param[in] portNum
398 The port number (0..3)
399 @param[in] bitPos
400 The bit position (0..31)
401 */
402 /**************************************************************************/
403 void gpioIntEnable (uint32_t portNum, uint32_t bitPos)
404 {
405 if (!_gpioInitialised) gpioInit();
406
407 switch (portNum)
408 {
409 case 0:
410 GPIO_GPIO0IE |= (0x1<<bitPos);
411 break;
412 case 1:
413 GPIO_GPIO1IE |= (0x1<<bitPos);
414 break;
415 case 2:
416 GPIO_GPIO2IE |= (0x1<<bitPos);
417 break;
418 case 3:
419 GPIO_GPIO3IE |= (0x1<<bitPos);
420 break;
421 default:
422 break;
423 }
424 return;
425 }
426
427 /**************************************************************************/
428 /*!
429 @brief Disables the interrupt mask for a specific port pin
430
431 @param[in] portNum
432 The port number (0..3)
433 @param[in] bitPos
434 The bit position (0..31)
435 */
436 /**************************************************************************/
437 void gpioIntDisable (uint32_t portNum, uint32_t bitPos)
438 {
439 if (!_gpioInitialised) gpioInit();
440
441 switch (portNum)
442 {
443 case 0:
444 GPIO_GPIO0IE &= ~(0x1<<bitPos);
445 break;
446 case 1:
447 GPIO_GPIO1IE &= ~(0x1<<bitPos);
448 break;
449 case 2:
450 GPIO_GPIO2IE &= ~(0x1<<bitPos);
451 break;
452 case 3:
453 GPIO_GPIO3IE &= ~(0x1<<bitPos);
454 break;
455 default:
456 break;
457 }
458 return;
459 }
460
461 /**************************************************************************/
462 /*!
463 @brief Gets the interrupt status for a specific port pin
464
465 @param[in] portNum
466 The port number (0..3)
467 @param[in] bitPos
468 The bit position (0..31)
469
470 @return The interrupt status for the specified port pin (0..1)
471 */
472 /**************************************************************************/
473 uint32_t gpioIntStatus (uint32_t portNum, uint32_t bitPos)
474 {
475 if (!_gpioInitialised) gpioInit();
476
477 uint32_t regVal = 0;
478
479 switch (portNum)
480 {
481 case 0:
482 if (GPIO_GPIO0MIS & (0x1<<bitPos))
483 {
484 regVal = 1;
485 }
486 break;
487 case 1:
488 if (GPIO_GPIO1MIS & (0x1<<bitPos))
489 {
490 regVal = 1;
491 }
492 break;
493 case 2:
494 if (GPIO_GPIO2MIS & (0x1<<bitPos))
495 {
496 regVal = 1;
497 }
498 break;
499 case 3:
500 if (GPIO_GPIO3MIS & (0x1<<bitPos))
501 {
502 regVal = 1;
503 }
504 break;
505 default:
506 break;
507 }
508 return ( regVal );
509 }
510
511 /**************************************************************************/
512 /*!
513 @brief Clears the interrupt for a port pin
514
515 @param[in] portNum
516 The port number (0..3)
517 @param[in] bitPos
518 The bit position (0..31)
519 */
520 /**************************************************************************/
521 void gpioIntClear (uint32_t portNum, uint32_t bitPos)
522 {
523 if (!_gpioInitialised) gpioInit();
524
525 switch (portNum)
526 {
527 case 0:
528 GPIO_GPIO0IC |= (0x1<<bitPos);
529 break;
530 case 1:
531 GPIO_GPIO1IC |= (0x1<<bitPos);
532 break;
533 case 2:
534 GPIO_GPIO2IC |= (0x1<<bitPos);
535 break;
536 case 3:
537 GPIO_GPIO3IC |= (0x1<<bitPos);
538 break;
539 default:
540 break;
541 }
542 return;
543 }
544
545 /**************************************************************************/
546 /*!
547 @brief Configures the internal pullup/down resistor for GPIO pins
548 (only relevant for pins configured as inputs)
549
550 @param[in] ioconReg
551 A pointer to the IOCON registry value corresponding to
552 the pin you wish to change (for example: &IOCON_PIO2_0
553 for GPIO pin 2.0).
554 @param[in] mode
555 The 'mode' that the pin should be set to, which must be
556 correspond to a value defined in gpioPullupMode_t
557
558 @warning By default, all GPIO pins have the internal pull-up
559 resistor enabled. This may cause unusual behaviour if
560 care isn't taken to set the internal resistor to an
561 appropriate state.
562
563 @section Example
564
565 @code
566 // Initialise gpio
567 gpioInit();
568 // Set GPIO1.8 to input
569 gpioSetDir(1, 8, gpioDirection_Input);
570 // Disable the internal pullup/down resistor on P1.8
571 gpioSetPullup(&IOCON_PIO1_8, gpioPullupMode_Inactive);
572 @endcode
573 */
574 /**************************************************************************/
575 void gpioSetPullup (volatile uint32_t *ioconReg, gpioPullupMode_t mode)
576 {
577 if (!_gpioInitialised) gpioInit();
578
579 // ToDo: Disable interrupts while we are doing this?
580
581 *ioconReg &= ~(IOCON_COMMON_MODE_MASK);
582 *ioconReg |= mode;
583
584 // ToDo: Re-enable interrupts?
585 };
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