drivers/displays/tft/hw/ssd1351.h

   1 /**************************************************************************/
   2 /*!
   3     @file     ssd1351.h
   4     @author   K. Townsend (www.adafruit.com)
   5
   6     @section LICENSE
   7
   8     Software License Agreement (BSD License)
   9
  10     Copyright (c) 2012, Adafruit Industries
  11     All rights reserved.
  12
  13     Redistribution and use in source and binary forms, with or without
  14     modification, are permitted provided that the following conditions are met:
  15     1. Redistributions of source code must retain the above copyright
  16     notice, this list of conditions and the following disclaimer.
  17     2. Redistributions in binary form must reproduce the above copyright
  18     notice, this list of conditions and the following disclaimer in the
  19     documentation and/or other materials provided with the distribution.
  20     3. Neither the name of the copyright holders nor the
  21     names of its contributors may be used to endorse or promote products
  22     derived from this software without specific prior written permission.
  23
  24     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
  25     EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  26     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
  28     DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  30     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  31     ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34 */
  35 /**************************************************************************/
  36 #ifndef __SSD1351_H__
  37 #define __SSD1351_H__
  38
  39 #include "projectconfig.h"
  40 #include "drivers/displays/tft/lcd.h"
  41 #include "core/gpio/gpio.h"
  42
  43 /*=========================================================================
  44     SPI modes
  45     -----------------------------------------------------------------------
  46     The OLED supports both 3-pin and 4-pin SPI modes
  47
  48     3-PIN MODE      Saves one GPIO pin (D/C) by adding the D/C bit before
  49                     every transfer, meaning that 9 bits are sent every frame
  50                     instead of 8.  You have slightly slower performance
  51                     but use less pins. Requires 3 GPIO pins (SCK, SID, RST)
  52
  53     4-PIN MODE      Uses a normal SPI interface with 8-bits per transfer,
  54                     plus a dedicated D/C pin to indicate if this is a
  55                     command or data byte. Requires 4 GPIO pins (SCK, SID,
  56                     RST, DC).
  57
  58     To select one of the SPI modes, make sure the BS0/1 pins are correctly
  59     set on the OLED display and uncomment the appropriate define below.
  60     -----------------------------------------------------------------------*/
  61     // #define SSD1351_BUS_SPI3
  62     #define SSD1351_BUS_SPI4
  63 /*=========================================================================*/
  64
  65 // Control pins
  66 #define SSD1351_SCK_PORT                (2) // SCK (D0)
  67 #define SSD1351_SCK_PIN                 (1)
  68 #define SSD1351_SID_PORT                (2) // DAT/MOSI (D1)
  69 #define SSD1351_SID_PIN                 (2)
  70 #define SSD1351_CS_PORT                 (2) // OLEDCS
  71 #define SSD1351_CS_PIN                  (3)
  72 #define SSD1351_RST_PORT                (2) // RST
  73 #define SSD1351_RST_PIN                 (4)
  74 #define SSD1351_DC_PORT                 (2) // D/C (only required for 4-pin SPI)
  75 #define SSD1351_DC_PIN                  (5)
  76
  77 // Placed here to try to keep all pin specific values in the header file
  78 #define SSD1351_DISABLEPULLUPS()  do {  gpioSetPullup(&IOCON_PIO2_1, gpioPullupMode_Inactive); \
  79                                         gpioSetPullup(&IOCON_PIO2_2, gpioPullupMode_Inactive); \
  80                                         gpioSetPullup(&IOCON_PIO2_3, gpioPullupMode_Inactive); \
  81                                         gpioSetPullup(&IOCON_PIO2_4, gpioPullupMode_Inactive); \
  82                                         gpioSetPullup(&IOCON_PIO2_5, gpioPullupMode_Inactive); } while (0)
  83
  84 // These registers allow fast single cycle clear+set of bits (see section 8.5.1 of LPC1343 UM)
  85 #define SSD1351_GPIO2DATA_SCK           (*(pREG32 (GPIO_GPIO2_BASE + ((1 << SSD1351_SCK_PIN) << 2))))
  86 #define SSD1351_GPIO2DATA_SID           (*(pREG32 (GPIO_GPIO2_BASE + ((1 << SSD1351_SID_PIN) << 2))))
  87 #define SSD1351_GPIO2DATA_CS            (*(pREG32 (GPIO_GPIO2_BASE + ((1 << SSD1351_CS_PIN) << 2))))
  88 #define SSD1351_GPIO2DATA_RST           (*(pREG32 (GPIO_GPIO2_BASE + ((1 << SSD1351_RST_PIN) << 2))))
  89 #define SSD1351_GPIO2DATA_DC            (*(pREG32 (GPIO_GPIO2_BASE + ((1 << SSD1351_DC_PIN) << 2))))
  90
  91 // Macros for control line state
  92 #define CLR_SCK                         SSD1351_GPIO2DATA_SCK = (0)
  93 #define SET_SCK                         SSD1351_GPIO2DATA_SCK = (1 << SSD1351_SCK_PIN)
  94 #define CLR_SID                         SSD1351_GPIO2DATA_SID = (0)
  95 #define SET_SID                         SSD1351_GPIO2DATA_SID = (1 << SSD1351_SID_PIN)
  96 #define CLR_CS                          SSD1351_GPIO2DATA_CS  = (0)
  97 #define SET_CS                          SSD1351_GPIO2DATA_CS  = (1 << SSD1351_CS_PIN)
  98 #define CLR_RST                         SSD1351_GPIO2DATA_RST = (0)
  99 #define SET_RST                         SSD1351_GPIO2DATA_RST = (1 << SSD1351_RST_PIN)
 100 #define CLR_DC                          SSD1351_GPIO2DATA_DC  = (0)
 101 #define SET_DC                          SSD1351_GPIO2DATA_DC  = (1 << SSD1351_DC_PIN)
 102
 103 // SSD1351 Commands
 104 enum
 105 {
 106   SSD1351_CMD_SETCOLUMNADDRESS          = 0x15,
 107   SSD1351_CMD_SETROWADDRESS             = 0x75,
 108   SSD1351_CMD_WRITERAM                  = 0x5C, // Write data to GRAM and increment until another command is sent
 109   SSD1351_CMD_READRAM                   = 0x5D, // Read data from GRAM and increment until another command is sent
 110   SSD1351_CMD_COLORDEPTH                = 0xA0, // Numerous functions include increment direction ... see DS
 111                                                 // A0[0] = Address Increment Mode (0 = horizontal, 1 = vertical)
 112                                                 // A0[1] = Column Address Remap (0 = left to right, 1 = right to left)
 113                                                 // A0[2] = Color Remap (0 = ABC, 1 = CBA) - HW RGB/BGR switch
 114                                                 // A0[4] = COM Scan Direction (0 = top to bottom, 1 = bottom to top)
 115                                                 // A0[5] = Odd/Even Paid Split
 116                                                 // A0[7:6] = Display Color Mode (00 = 8-bit, 01 = 65K, 10/11 = 262K, 8/16-bit interface only)
 117   SSD1351_CMD_SETDISPLAYSTARTLINE       = 0xA1,
 118   SSD1351_CMD_SETDISPLAYOFFSET          = 0xA2,
 119   SSD1351_CMD_SETDISPLAYMODE_ALLOFF     = 0xA4, // Force entire display area to grayscale GS0
 120   SSD1351_CMD_SETDISPLAYMODE_ALLON      = 0xA5, // Force entire display area to grayscale GS63
 121   SSD1351_CMD_SETDISPLAYMODE_RESET      = 0xA6, // Resets the display area relative to the above two commands
 122   SSD1351_CMD_SETDISPLAYMODE_INVERT     = 0xA7, // Inverts the display contents (GS0 -> GS63, GS63 -> GS0, etc.)
 123   SSD1351_CMD_FUNCTIONSELECTION         = 0xAB, // Enable/Disable the internal VDD regulator
 124   SSD1351_CMD_SLEEPMODE_DISPLAYOFF      = 0xAE, // Sleep mode on (display off)
 125   SSD1351_CMD_SLEEPMODE_DISPLAYON       = 0xAF, // Sleep mode off (display on)
 126   SSD1351_CMD_SETPHASELENGTH            = 0xB1, // Larger capacitance may require larger delay to discharge previous pixel state
 127   SSD1351_CMD_ENHANCEDDRIVINGSCHEME     = 0xB2,
 128   SSD1351_CMD_SETFRONTCLOCKDIV          = 0xB3, // DCLK divide ration fro CLK (from 1 to 16)
 129   SSD1351_CMD_SETSEGMENTLOWVOLTAGE      = 0xB4,
 130   SSD1351_CMD_SETGPIO                   = 0xB5,
 131   SSD1351_CMD_SETSECONDPRECHARGEPERIOD  = 0xB6,
 132   SSD1351_CMD_GRAYSCALELOOKUP           = 0xB8,
 133   SSD1351_CMD_LINEARLUT                 = 0xB9,
 134   SSD1351_CMD_SETPRECHARGEVOLTAGE       = 0xBB,
 135   SSD1351_CMD_SETVCOMHVOLTAGE           = 0xBE,
 136   SSD1351_CMD_SETCONTRAST               = 0xC1,
 137   SSD1351_CMD_MASTERCONTRAST            = 0xC7,
 138   SSD1351_CMD_SETMUXRRATIO              = 0xCA,
 139   SSD1351_CMD_NOP3                      = 0xD1,
 140   SSD1351_CMD_NOP4                      = 0xE3,
 141   SSD1351_CMD_SETCOMMANDLOCK            = 0xFD,
 142   SSD1351_CMD_HORIZONTALSCROLL          = 0x96,
 143   SSD1351_CMD_STOPMOVING                = 0x9E,
 144   SSD1351_CMD_STARTMOVING               = 0x9F
 145 };
 146
 147 #endif