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Fahrplandaten.
[hackover2013-badge-firmware.git] / lpc134x.h
diff --git a/lpc134x.h b/lpc134x.h
index 9da8fcb..002f7cd 100644 (file)
--- a/lpc134x.h
+++ b/lpc134x.h
@@ -232,45 +232,45 @@
     subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can
     produce a clock up to the maximum allowed for the CPU, which is 72 MHz. */
 
     subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can
     produce a clock up to the maximum allowed for the CPU, which is 72 MHz. */
 
-#define SCB_PLLCTRL_MULT_1                        ((unsigned int) 0x00000000)
-#define SCB_PLLCTRL_MULT_2                        ((unsigned int) 0x00000001)
-#define SCB_PLLCTRL_MULT_3                        ((unsigned int) 0x00000002)
-#define SCB_PLLCTRL_MULT_4                        ((unsigned int) 0x00000003)
-#define SCB_PLLCTRL_MULT_5                        ((unsigned int) 0x00000004)
-#define SCB_PLLCTRL_MULT_6                        ((unsigned int) 0x00000005)
-#define SCB_PLLCTRL_MULT_7                        ((unsigned int) 0x00000006)
-#define SCB_PLLCTRL_MULT_8                        ((unsigned int) 0x00000007)
-#define SCB_PLLCTRL_MULT_9                        ((unsigned int) 0x00000008)
-#define SCB_PLLCTRL_MULT_10                       ((unsigned int) 0x00000009)
-#define SCB_PLLCTRL_MULT_11                       ((unsigned int) 0x0000000A)
-#define SCB_PLLCTRL_MULT_12                       ((unsigned int) 0x0000000B)
-#define SCB_PLLCTRL_MULT_13                       ((unsigned int) 0x0000000C)
-#define SCB_PLLCTRL_MULT_14                       ((unsigned int) 0x0000000D)
-#define SCB_PLLCTRL_MULT_15                       ((unsigned int) 0x0000000E)
-#define SCB_PLLCTRL_MULT_16                       ((unsigned int) 0x0000000F)
-#define SCB_PLLCTRL_MULT_17                       ((unsigned int) 0x00000010)
-#define SCB_PLLCTRL_MULT_18                       ((unsigned int) 0x00000011)
-#define SCB_PLLCTRL_MULT_19                       ((unsigned int) 0x00000012)
-#define SCB_PLLCTRL_MULT_20                       ((unsigned int) 0x00000013)
-#define SCB_PLLCTRL_MULT_21                       ((unsigned int) 0x00000014)
-#define SCB_PLLCTRL_MULT_22                       ((unsigned int) 0x00000015)
-#define SCB_PLLCTRL_MULT_23                       ((unsigned int) 0x00000016)
-#define SCB_PLLCTRL_MULT_24                       ((unsigned int) 0x00000017)
-#define SCB_PLLCTRL_MULT_25                       ((unsigned int) 0x00000018)
-#define SCB_PLLCTRL_MULT_26                       ((unsigned int) 0x00000019)
-#define SCB_PLLCTRL_MULT_27                       ((unsigned int) 0x0000001A)
-#define SCB_PLLCTRL_MULT_28                       ((unsigned int) 0x0000001B)
-#define SCB_PLLCTRL_MULT_29                       ((unsigned int) 0x0000001C)
-#define SCB_PLLCTRL_MULT_30                       ((unsigned int) 0x0000001D)
-#define SCB_PLLCTRL_MULT_31                       ((unsigned int) 0x0000001E)
-#define SCB_PLLCTRL_MULT_32                       ((unsigned int) 0x0000001F)
-#define SCB_PLLCTRL_MULT_MASK                     ((unsigned int) 0x0000001F)    
-#define SCB_PLLCTRL_DIV_2                         ((unsigned int) 0x00000000)       
-#define SCB_PLLCTRL_DIV_4                         ((unsigned int) 0x00000020)       
-#define SCB_PLLCTRL_DIV_8                         ((unsigned int) 0x00000040)       
-#define SCB_PLLCTRL_DIV_16                        ((unsigned int) 0x00000060)
-#define SCB_PLLCTRL_DIV_BIT                       (5)
-#define SCB_PLLCTRL_DIV_MASK                      ((unsigned int) 0x00000060)    
+#define SCB_PLLCTRL_MSEL_1                        ((unsigned int) 0x00000000)
+#define SCB_PLLCTRL_MSEL_2                        ((unsigned int) 0x00000001)
+#define SCB_PLLCTRL_MSEL_3                        ((unsigned int) 0x00000002)
+#define SCB_PLLCTRL_MSEL_4                        ((unsigned int) 0x00000003)
+#define SCB_PLLCTRL_MSEL_5                        ((unsigned int) 0x00000004)
+#define SCB_PLLCTRL_MSEL_6                        ((unsigned int) 0x00000005)
+#define SCB_PLLCTRL_MSEL_7                        ((unsigned int) 0x00000006)
+#define SCB_PLLCTRL_MSEL_8                        ((unsigned int) 0x00000007)
+#define SCB_PLLCTRL_MSEL_9                        ((unsigned int) 0x00000008)
+#define SCB_PLLCTRL_MSEL_10                       ((unsigned int) 0x00000009)
+#define SCB_PLLCTRL_MSEL_11                       ((unsigned int) 0x0000000A)
+#define SCB_PLLCTRL_MSEL_12                       ((unsigned int) 0x0000000B)
+#define SCB_PLLCTRL_MSEL_13                       ((unsigned int) 0x0000000C)
+#define SCB_PLLCTRL_MSEL_14                       ((unsigned int) 0x0000000D)
+#define SCB_PLLCTRL_MSEL_15                       ((unsigned int) 0x0000000E)
+#define SCB_PLLCTRL_MSEL_16                       ((unsigned int) 0x0000000F)
+#define SCB_PLLCTRL_MSEL_17                       ((unsigned int) 0x00000010)
+#define SCB_PLLCTRL_MSEL_18                       ((unsigned int) 0x00000011)
+#define SCB_PLLCTRL_MSEL_19                       ((unsigned int) 0x00000012)
+#define SCB_PLLCTRL_MSEL_20                       ((unsigned int) 0x00000013)
+#define SCB_PLLCTRL_MSEL_21                       ((unsigned int) 0x00000014)
+#define SCB_PLLCTRL_MSEL_22                       ((unsigned int) 0x00000015)
+#define SCB_PLLCTRL_MSEL_23                       ((unsigned int) 0x00000016)
+#define SCB_PLLCTRL_MSEL_24                       ((unsigned int) 0x00000017)
+#define SCB_PLLCTRL_MSEL_25                       ((unsigned int) 0x00000018)
+#define SCB_PLLCTRL_MSEL_26                       ((unsigned int) 0x00000019)
+#define SCB_PLLCTRL_MSEL_27                       ((unsigned int) 0x0000001A)
+#define SCB_PLLCTRL_MSEL_28                       ((unsigned int) 0x0000001B)
+#define SCB_PLLCTRL_MSEL_29                       ((unsigned int) 0x0000001C)
+#define SCB_PLLCTRL_MSEL_30                       ((unsigned int) 0x0000001D)
+#define SCB_PLLCTRL_MSEL_31                       ((unsigned int) 0x0000001E)
+#define SCB_PLLCTRL_MSEL_32                       ((unsigned int) 0x0000001F)
+#define SCB_PLLCTRL_MSEL_MASK                     ((unsigned int) 0x0000001F)    
+#define SCB_PLLCTRL_PSEL_2                        ((unsigned int) 0x00000000)       
+#define SCB_PLLCTRL_PSEL_4                        ((unsigned int) 0x00000020)       
+#define SCB_PLLCTRL_PSEL_8                        ((unsigned int) 0x00000040)       
+#define SCB_PLLCTRL_PSEL_16                       ((unsigned int) 0x00000060)
+#define SCB_PLLCTRL_PSEL_BIT                      (5)
+#define SCB_PLLCTRL_PSEL_MASK                     ((unsigned int) 0x00000060)    
 #define SCB_PLLCTRL_DIRECT_MASK                   ((unsigned int) 0x00000080) // Direct CCO clock output control
 #define SCB_PLLCTRL_BYPASS_MASK                   ((unsigned int) 0x00000100) // Input clock bypass control
 #define SCB_PLLCTRL_MASK                          ((unsigned int) 0x000001FF)    
 #define SCB_PLLCTRL_DIRECT_MASK                   ((unsigned int) 0x00000080) // Direct CCO clock output control
 #define SCB_PLLCTRL_BYPASS_MASK                   ((unsigned int) 0x00000100) // Input clock bypass control
 #define SCB_PLLCTRL_MASK                          ((unsigned int) 0x000001FF)    
@@ -1797,7 +1797,7 @@
 #define IOCON_SWDIO_PIO1_3_FUNC_SWDIO             ((unsigned int) 0x00000000)
 #define IOCON_SWDIO_PIO1_3_FUNC_GPIO              ((unsigned int) 0x00000001)
 #define IOCON_SWDIO_PIO1_3_FUNC_AD4               ((unsigned int) 0x00000002)
 #define IOCON_SWDIO_PIO1_3_FUNC_SWDIO             ((unsigned int) 0x00000000)
 #define IOCON_SWDIO_PIO1_3_FUNC_GPIO              ((unsigned int) 0x00000001)
 #define IOCON_SWDIO_PIO1_3_FUNC_AD4               ((unsigned int) 0x00000002)
-#define IOCON_SWDIO_PIO1_3_FUNC_CT32B1_MAT2       ((unsigned int) 0x00000004)
+#define IOCON_SWDIO_PIO1_3_FUNC_CT32B1_MAT2       ((unsigned int) 0x00000003)
 #define IOCON_SWDIO_PIO1_3_HYS_MASK               ((unsigned int) 0x00000020)
 #define IOCON_SWDIO_PIO1_3_HYS_DISABLE            ((unsigned int) 0x00000000)
 #define IOCON_SWDIO_PIO1_3_HYS_ENABLE             ((unsigned int) 0x00000020)
 #define IOCON_SWDIO_PIO1_3_HYS_MASK               ((unsigned int) 0x00000020)
 #define IOCON_SWDIO_PIO1_3_HYS_DISABLE            ((unsigned int) 0x00000000)
 #define IOCON_SWDIO_PIO1_3_HYS_ENABLE             ((unsigned int) 0x00000020)
@@ -2770,7 +2770,7 @@ static inline void NVIC_DisableIRQ(IRQn_t IRQn)
 #define TMR_TMR16B0TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR16B0TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR16B0TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
 #define TMR_TMR16B0TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR16B0TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR16B0TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
-#define TMR_TMR16B0TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000002)
+#define TMR_TMR16B0TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000000)
 
 #define TMR_TMR16B0MCR_MR0_INT_MASK               ((unsigned int) 0x00000001) // Interrupt on MRO
 #define TMR_TMR16B0MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
 
 #define TMR_TMR16B0MCR_MR0_INT_MASK               ((unsigned int) 0x00000001) // Interrupt on MRO
 #define TMR_TMR16B0MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
@@ -2904,7 +2904,7 @@ static inline void NVIC_DisableIRQ(IRQn_t IRQn)
 #define TMR_TMR16B1TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR16B1TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR16B1TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
 #define TMR_TMR16B1TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR16B1TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR16B1TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
-#define TMR_TMR16B1TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000002)
+#define TMR_TMR16B1TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000000)
 
 #define TMR_TMR16B1MCR_MR0_INT_MASK               ((unsigned int) 0x00000001) // Interrupt on MRO
 #define TMR_TMR16B1MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
 
 #define TMR_TMR16B1MCR_MR0_INT_MASK               ((unsigned int) 0x00000001) // Interrupt on MRO
 #define TMR_TMR16B1MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
@@ -3042,7 +3042,7 @@ static inline void NVIC_DisableIRQ(IRQn_t IRQn)
 #define TMR_TMR32B0TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR32B0TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR32B0TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
 #define TMR_TMR32B0TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR32B0TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR32B0TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
-#define TMR_TMR32B0TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000002)
+#define TMR_TMR32B0TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000000)
 
 #define TMR_TMR32B0MCR_MR0_INT_MASK               ((unsigned int) 0x00000001)   // Interrupt on MRO
 #define TMR_TMR32B0MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
 
 #define TMR_TMR32B0MCR_MR0_INT_MASK               ((unsigned int) 0x00000001)   // Interrupt on MRO
 #define TMR_TMR32B0MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
@@ -3176,7 +3176,7 @@ static inline void NVIC_DisableIRQ(IRQn_t IRQn)
 #define TMR_TMR32B1TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR32B1TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR32B1TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
 #define TMR_TMR32B1TCR_COUNTERENABLE_DISABLED     ((unsigned int) 0x00000000)
 #define TMR_TMR32B1TCR_COUNTERRESET_MASK          ((unsigned int) 0x00000002)
 #define TMR_TMR32B1TCR_COUNTERRESET_ENABLED       ((unsigned int) 0x00000002)
-#define TMR_TMR32B1TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000002)
+#define TMR_TMR32B1TCR_COUNTERRESET_DISABLED      ((unsigned int) 0x00000000)
 
 #define TMR_TMR32B1MCR_MR0_INT_MASK               ((unsigned int) 0x00000001)   // Interrupt on MRO
 #define TMR_TMR32B1MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
 
 #define TMR_TMR32B1MCR_MR0_INT_MASK               ((unsigned int) 0x00000001)   // Interrupt on MRO
 #define TMR_TMR32B1MCR_MR0_INT_ENABLED            ((unsigned int) 0x00000001)
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