X-Git-Url: https://git.rohieb.name/hackover2013-badge-firmware.git/blobdiff_plain/9d18e10afb2439a6a9ba6978a799259746a837b7..1ab16aec62e20065faba56c469ddf75830860162:/core/cpu/cpu.c

diff --git a/core/cpu/cpu.c b/core/cpu/cpu.c
index 03c6db6..10080fc 100644
--- a/core/cpu/cpu.c
+++ b/core/cpu/cpu.c
@@ -102,24 +102,39 @@ void cpuPllSetup (cpuMultiplier_t multiplier)
   // Set clock speed
   switch (multiplier)
   {
+    // Fclkout = M * Fclkin = FCCO / (2 * P)
+    // FCCO should be in the range of 156-320MHz 
+    // (see Table 58 of the LPC1343 usermanual for examples)
     case CPU_MULTIPLIER_2:
-      SCB_PLLCTRL = (SCB_PLLCTRL_MULT_2 | (1 << SCB_PLLCTRL_DIV_BIT));
+      // Fclkout = 24.0MHz
+      // FCCO = 2 * 4 * 24 = 192MHz
+      SCB_PLLCTRL = (SCB_PLLCTRL_MSEL_2 | SCB_PLLCTRL_PSEL_4);
       break;
     case CPU_MULTIPLIER_3:
-      SCB_PLLCTRL = (SCB_PLLCTRL_MULT_3 | (1 << SCB_PLLCTRL_DIV_BIT));
+      // Fclkout = 36.0MHz
+      // FCCO = 2 * 4 * 36 = 288MHz
+      SCB_PLLCTRL = (SCB_PLLCTRL_MSEL_3 | SCB_PLLCTRL_PSEL_4);
       break;
     case CPU_MULTIPLIER_4:
-      SCB_PLLCTRL = (SCB_PLLCTRL_MULT_4 | (1 << SCB_PLLCTRL_DIV_BIT));
+      // Fclkout = 48.0MHz
+      // FCCO = 2 * 2 * 48 = 192MHz
+      SCB_PLLCTRL = (SCB_PLLCTRL_MSEL_4 | SCB_PLLCTRL_PSEL_2);
       break;
     case CPU_MULTIPLIER_5:
-      SCB_PLLCTRL = (SCB_PLLCTRL_MULT_5 | (1 << SCB_PLLCTRL_DIV_BIT));
+      // Fclkout = 60.0MHz
+      // FCCO = 2 * 2 * 60 = 240MHz
+      SCB_PLLCTRL = (SCB_PLLCTRL_MSEL_5 | SCB_PLLCTRL_PSEL_2);
       break;
     case CPU_MULTIPLIER_6:
-      SCB_PLLCTRL = (SCB_PLLCTRL_MULT_6 | (1 << SCB_PLLCTRL_DIV_BIT));
+      // Fclkout = 72.0MHz
+      // FCCO = 2 * 2 * 72 = 288MHz
+      SCB_PLLCTRL = (SCB_PLLCTRL_MSEL_6 | SCB_PLLCTRL_PSEL_2);
       break;
     case CPU_MULTIPLIER_1:
     default:
-      SCB_PLLCTRL = (SCB_PLLCTRL_MULT_1 | (1 << SCB_PLLCTRL_DIV_BIT));
+      // Fclkout = 12.0MHz
+      // FCCO = 2 * 8 * 12 = 192MHz
+      SCB_PLLCTRL = (SCB_PLLCTRL_MSEL_1 | SCB_PLLCTRL_PSEL_8);
       break;
   }
 
@@ -167,3 +182,24 @@ void cpuInit (void)
   // Setup PLL (etc.)
   cpuPllSetup(CPU_MULTIPLIER_6);
 }
+
+/**************************************************************************/
+/*! 
+    @brief Resets the device using the AIRCR register
+*/
+/**************************************************************************/
+void cpuReset (void)
+{
+  // Reset device
+  SCB_AIRCR = SCB_AIRCR_VECTKEY_VALUE | SCB_AIRCR_SYSRESETREQ; // 0x05FA0004
+
+  // Ensure completion of memory access
+  // DSB acts as a special data synchronization memory barrier. Instructions
+  // that come after the DSB, in program order, do not execute until the DSB
+  // instruction completes. The DSB instruction completes when all explicit
+  // memory accesses before it complete.
+  __asm volatile("DSB");
+
+  // Wait for reset
+  while(1);
+}