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update openswan to 0.4.10, reenable 2.6 support, sync with included openwrt packaging...
[openwrt.git] / package / rt2x00 / src / rt2400pci.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt2400pci"
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/init.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/delay.h>
39 #include <linux/etherdevice.h>
40 #include <linux/eeprom_93cx6.h>
41
42 #include <asm/io.h>
43
44 #include "rt2x00.h"
45 #include "rt2x00lib.h"
46 #include "rt2x00pci.h"
47 #include "rt2400pci.h"
48
49 /*
50 * Register access.
51 * All access to the CSR registers will go through the methods
52 * rt2x00pci_register_read and rt2x00pci_register_write.
53 * BBP and RF register require indirect register access,
54 * and use the CSR registers BBPCSR and RFCSR to achieve this.
55 * These indirect registers work with busy bits,
56 * and we will try maximal REGISTER_BUSY_COUNT times to access
57 * the register while taking a REGISTER_BUSY_DELAY us delay
58 * between each attampt. When the busy bit is still set at that time,
59 * the access attempt is considered to have failed,
60 * and we will print an error.
61 */
62 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
63 {
64 u32 reg;
65 unsigned int i;
66
67 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
68 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
69 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
70 break;
71 udelay(REGISTER_BUSY_DELAY);
72 }
73
74 return reg;
75 }
76
77 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
78 const u8 reg_id, const u8 value)
79 {
80 u32 reg;
81
82 /*
83 * Wait until the BBP becomes ready.
84 */
85 reg = rt2400pci_bbp_check(rt2x00dev);
86 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
87 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
88 return;
89 }
90
91 /*
92 * Write the data into the BBP.
93 */
94 reg = 0;
95 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
96 rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
97 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
98 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
99
100 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
101 }
102
103 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
104 const u8 reg_id, u8 *value)
105 {
106 u32 reg;
107
108 /*
109 * Wait until the BBP becomes ready.
110 */
111 reg = rt2400pci_bbp_check(rt2x00dev);
112 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
113 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
114 return;
115 }
116
117 /*
118 * Write the request into the BBP.
119 */
120 reg = 0;
121 rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
122 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
123 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
124
125 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
126
127 /*
128 * Wait until the BBP becomes ready.
129 */
130 reg = rt2400pci_bbp_check(rt2x00dev);
131 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
132 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
133 *value = 0xff;
134 return;
135 }
136
137 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
138 }
139
140 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
141 const u32 value)
142 {
143 u32 reg;
144 unsigned int i;
145
146 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
147 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
148 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
149 goto rf_write;
150 udelay(REGISTER_BUSY_DELAY);
151 }
152
153 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
154 return;
155
156 rf_write:
157 reg = 0;
158 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
159 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
160 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
161 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
162
163 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
164 }
165
166 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
167 {
168 struct rt2x00_dev *rt2x00dev = eeprom->data;
169 u32 reg;
170
171 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
172
173 eeprom->reg_data_in = !!rt2x00_get_field32(reg,
174 CSR21_EEPROM_DATA_IN);
175 eeprom->reg_data_out = !!rt2x00_get_field32(reg,
176 CSR21_EEPROM_DATA_OUT);
177 eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
178 CSR21_EEPROM_DATA_CLOCK);
179 eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
180 CSR21_EEPROM_CHIP_SELECT);
181 }
182
183 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
184 {
185 struct rt2x00_dev *rt2x00dev = eeprom->data;
186 u32 reg = 0;
187
188 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN,
189 !!eeprom->reg_data_in);
190 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT,
191 !!eeprom->reg_data_out);
192 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
193 !!eeprom->reg_data_clock);
194 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
195 !!eeprom->reg_chip_select);
196
197 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
198 }
199
200 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
201 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
202
203 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
204 const unsigned long word, void *data)
205 {
206 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
207 }
208
209 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
210 const unsigned long word, void *data)
211 {
212 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
213 }
214
215 static void rt2400pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
216 const unsigned long word, void *data)
217 {
218 rt2x00_eeprom_read(rt2x00dev, word, data);
219 }
220
221 static void rt2400pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
222 const unsigned long word, void *data)
223 {
224 rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
225 }
226
227 static void rt2400pci_read_bbp(struct rt2x00_dev *rt2x00dev,
228 const unsigned long word, void *data)
229 {
230 rt2400pci_bbp_read(rt2x00dev, word, data);
231 }
232
233 static void rt2400pci_write_bbp(struct rt2x00_dev *rt2x00dev,
234 const unsigned long word, void *data)
235 {
236 rt2400pci_bbp_write(rt2x00dev, word, *((u8*)data));
237 }
238
239 static const struct rt2x00debug rt2400pci_rt2x00debug = {
240 .owner = THIS_MODULE,
241 .reg_csr = {
242 .read = rt2400pci_read_csr,
243 .write = rt2400pci_write_csr,
244 .word_size = sizeof(u32),
245 .word_count = CSR_REG_SIZE / sizeof(u32),
246 },
247 .reg_eeprom = {
248 .read = rt2400pci_read_eeprom,
249 .write = rt2400pci_write_eeprom,
250 .word_size = sizeof(u16),
251 .word_count = EEPROM_SIZE / sizeof(u16),
252 },
253 .reg_bbp = {
254 .read = rt2400pci_read_bbp,
255 .write = rt2400pci_write_bbp,
256 .word_size = sizeof(u8),
257 .word_count = BBP_SIZE / sizeof(u8),
258 },
259 };
260 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
261
262 #ifdef CONFIG_RT2400PCI_RFKILL
263 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
264 {
265 u32 reg;
266
267 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
268 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
269 }
270 #endif /* CONFIG_RT2400PCI_RFKILL */
271
272 /*
273 * Configuration handlers.
274 */
275 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
276 {
277 u32 reg[2];
278
279 memset(&reg, 0, sizeof(reg));
280 memcpy(&reg, bssid, ETH_ALEN);
281
282 /*
283 * The BSSID is passed to us as an array of bytes,
284 * that array is little endian, so no need for byte ordering.
285 */
286 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
287 }
288
289 static void rt2400pci_config_promisc(struct rt2x00_dev *rt2x00dev,
290 const int promisc)
291 {
292 u32 reg;
293
294 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
295 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, !promisc);
296 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
297 }
298
299 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
300 {
301 u32 reg;
302
303 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
304
305 /*
306 * Apply hardware packet filter.
307 */
308 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
309
310 if (!is_monitor_present(&rt2x00dev->interface) &&
311 (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
312 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 1);
313 else
314 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
315
316 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
317 if (is_monitor_present(&rt2x00dev->interface)) {
318 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 0);
319 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 0);
320 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 0);
321 } else {
322 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
323 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
324 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
325 }
326
327 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
328
329 /*
330 * Enable beacon config
331 */
332 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
333 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
334 PREAMBLE + get_duration(IEEE80211_HEADER, 2));
335 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
336
337 /*
338 * Enable synchronisation.
339 */
340 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
341 if (is_interface_present(&rt2x00dev->interface)) {
342 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
343 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
344 }
345
346 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
347 if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
348 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
349 else if (type == IEEE80211_IF_TYPE_STA)
350 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
351 else if (is_monitor_present(&rt2x00dev->interface) &&
352 !is_interface_present(&rt2x00dev->interface))
353 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
354
355 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
356 }
357
358 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
359 const int value, const int channel, const int txpower)
360 {
361 u32 rf1 = rt2x00dev->rf1;
362 u32 rf2 = value;
363 u32 rf3 = rt2x00dev->rf3;
364
365 /*
366 * Switch on tuning bits.
367 */
368 rt2x00_set_field32(&rf1, RF1_TUNER, 1);
369 rt2x00_set_field32(&rf3, RF3_TUNER, 1);
370
371 rt2400pci_rf_write(rt2x00dev, rf1);
372 rt2400pci_rf_write(rt2x00dev, rf2);
373 rt2400pci_rf_write(rt2x00dev, rf3);
374
375 /*
376 * RF2420 chipset don't need any additional actions.
377 */
378 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
379 return;
380
381 /*
382 * For the RT2421 chipsets we need to write an invalid
383 * reference clock rate to activate auto_tune.
384 * After that we set the value back to the correct channel.
385 */
386 rt2400pci_rf_write(rt2x00dev, rf1);
387 rt2400pci_rf_write(rt2x00dev, 0x000c2a32);
388 rt2400pci_rf_write(rt2x00dev, rf3);
389
390 msleep(1);
391
392 rt2400pci_rf_write(rt2x00dev, rf1);
393 rt2400pci_rf_write(rt2x00dev, rf2);
394 rt2400pci_rf_write(rt2x00dev, rf3);
395
396 msleep(1);
397
398 /*
399 * Switch off tuning bits.
400 */
401 rt2x00_set_field32(&rf1, RF1_TUNER, 0);
402 rt2x00_set_field32(&rf3, RF3_TUNER, 0);
403
404 rt2400pci_rf_write(rt2x00dev, rf1);
405 rt2400pci_rf_write(rt2x00dev, rf3);
406
407 /*
408 * Update rf fields
409 */
410 rt2x00dev->rf1 = rf1;
411 rt2x00dev->rf2 = rf2;
412 rt2x00dev->rf3 = rf3;
413
414 /*
415 * Clear false CRC during channel switch.
416 */
417 rt2x00pci_register_read(rt2x00dev, CNT0, &rf1);
418 }
419
420 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
421 {
422 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
423 }
424
425 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
426 int antenna_tx, int antenna_rx)
427 {
428 u8 r1;
429 u8 r4;
430
431 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
432 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
433
434 /*
435 * Configure the TX antenna.
436 */
437 if (antenna_tx == ANTENNA_DIVERSITY)
438 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
439 else if (antenna_tx == ANTENNA_A)
440 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
441 else if (antenna_tx == ANTENNA_B)
442 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
443
444 /*
445 * Configure the RX antenna.
446 */
447 if (antenna_rx == ANTENNA_DIVERSITY)
448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
449 else if (antenna_rx == ANTENNA_A)
450 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
451 else if (antenna_rx == ANTENNA_B)
452 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
453
454 rt2400pci_bbp_write(rt2x00dev, 4, r4);
455 rt2400pci_bbp_write(rt2x00dev, 1, r1);
456 }
457
458 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
459 struct ieee80211_tx_queue_params *params)
460 {
461 u32 reg;
462
463 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
464 rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
465 rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
466 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
467 }
468
469 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
470 int short_slot_time, int beacon_int)
471 {
472 u32 reg;
473
474 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
475 rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
476 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
477 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
478
479 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
480 rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
481 rt2x00_set_field32(&reg, CSR18_PIFS,
482 short_slot_time ? SHORT_PIFS : PIFS);
483 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
484
485 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
486 rt2x00_set_field32(&reg, CSR19_DIFS,
487 short_slot_time ? SHORT_DIFS : DIFS);
488 rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
489 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
490
491 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
492 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
493 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
494 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
495
496 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
497 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
498 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
499 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
500 }
501
502 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
503 {
504 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
505 u32 reg;
506 u32 preamble;
507 u16 value;
508
509 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
510 ? SHORT_PREAMBLE : PREAMBLE;
511
512 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
513 rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
514
515 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
516 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
517 SHORT_DIFS : DIFS) +
518 PLCP + preamble + get_duration(ACK_SIZE, 10);
519 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
520 value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
521 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
522 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
523
524 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
525
526 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
527 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
528 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
529 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
530 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
531
532 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
533 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
534 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
535 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
536 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
537
538 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
539 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
540 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
541 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
542 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
543
544 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
545 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
546 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
547 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
548 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
549 }
550
551 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
552 const int phymode)
553 {
554 struct ieee80211_hw_mode *mode;
555 struct ieee80211_rate *rate;
556
557 rt2x00dev->curr_hwmode = HWMODE_B;
558
559 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
560 rate = &mode->rates[mode->num_rates - 1];
561
562 rt2400pci_config_rate(rt2x00dev, rate->val2);
563 }
564
565 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
566 {
567 u32 reg[2];
568
569 memset(&reg, 0, sizeof(reg));
570 memcpy(&reg, addr, ETH_ALEN);
571
572 /*
573 * The MAC address is passed to us as an array of bytes,
574 * that array is little endian, so no need for byte ordering.
575 */
576 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
577 }
578
579 /*
580 * LED functions.
581 */
582 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
583 {
584 u32 reg;
585
586 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
587
588 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
589 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
590
591 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
592 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
593 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
594 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
595 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
596 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
597 } else {
598 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
599 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
600 }
601
602 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
603 }
604
605 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
606 {
607 u32 reg;
608
609 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
610 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
611 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
612 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
613 }
614
615 /*
616 * Link tuning
617 */
618 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
619 {
620 u8 reg;
621 char false_cca_delta;
622
623 /*
624 * The link tuner should not run longer then 60 seconds,
625 * and should run once every 2 seconds.
626 */
627 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
628 return;
629
630 /*
631 * Read false CCA counter.
632 */
633 rt2400pci_bbp_read(rt2x00dev, 39, &reg);
634
635 /*
636 * Determine difference with previous CCA counter.
637 */
638 false_cca_delta = reg - rt2x00dev->link.false_cca;
639 rt2x00dev->link.false_cca = reg;
640
641 /*
642 * Check if the difference is higher than the
643 * threshold and if so, tune the link.
644 */
645 if (false_cca_delta >= 8) {
646 /*
647 * Read and update RX AGC VGC.
648 */
649 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
650 reg += 2;
651 if (reg < 0x20)
652 rt2400pci_bbp_write(rt2x00dev, 13, reg);
653 rt2x00dev->rx_status.noise = reg;
654 }
655 }
656
657 /*
658 * Initialization functions.
659 */
660 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
661 {
662 struct data_desc *rxd;
663 unsigned int i;
664 u32 word;
665
666 memset(rt2x00dev->rx->data_addr, 0x00,
667 rt2x00_get_ring_size(rt2x00dev->rx));
668
669 for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
670 rxd = rt2x00dev->rx->entry[i].priv;
671
672 rt2x00_desc_read(rxd, 2, &word);
673 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
674 rt2x00dev->rx->data_size);
675 rt2x00_desc_write(rxd, 2, word);
676
677 rt2x00_desc_read(rxd, 1, &word);
678 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
679 rt2x00dev->rx->entry[i].data_dma);
680 rt2x00_desc_write(rxd, 1, word);
681
682 rt2x00_desc_read(rxd, 0, &word);
683 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
684 rt2x00_desc_write(rxd, 0, word);
685 }
686
687 rt2x00_ring_index_clear(rt2x00dev->rx);
688 }
689
690 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev,
691 const int queue)
692 {
693 struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
694 struct data_desc *txd;
695 unsigned int i;
696 u32 word;
697
698 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
699
700 for (i = 0; i < ring->stats.limit; i++) {
701 txd = ring->entry[i].priv;
702
703 rt2x00_desc_read(txd, 1, &word);
704 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
705 ring->entry[i].data_dma);
706 rt2x00_desc_write(txd, 1, word);
707
708 rt2x00_desc_read(txd, 2, &word);
709 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
710 ring->data_size);
711 rt2x00_desc_write(txd, 2, word);
712
713 rt2x00_desc_read(txd, 0, &word);
714 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
715 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
716 rt2x00_desc_write(txd, 0, word);
717 }
718
719 rt2x00_ring_index_clear(ring);
720 }
721
722 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
723 {
724 u32 reg;
725
726 /*
727 * Initialize rings.
728 */
729 rt2400pci_init_rxring(rt2x00dev);
730 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
731 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
732 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
733 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
734
735 /*
736 * Initialize registers.
737 */
738 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
739 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
740 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
741 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
742 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
743 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
744 rt2x00dev->bcn[1].stats.limit);
745 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
746 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
747 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
748
749 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
750 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
751 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
752 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
753
754 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
755 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
756 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
757 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
758
759 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
760 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
761 rt2x00dev->bcn[1].data_dma);
762 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
763
764 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
765 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
766 rt2x00dev->bcn[0].data_dma);
767 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
768
769 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
770 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE,
771 rt2x00dev->rx->desc_size);
772 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD,
773 rt2x00dev->rx->stats.limit);
774 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
775
776 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
777 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
778 rt2x00dev->rx->data_dma);
779 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
780
781 return 0;
782 }
783
784 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
785 {
786 u32 reg;
787
788 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
789 return -EBUSY;
790
791 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
792
793 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
794 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
795 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
796 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
797
798 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
799 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
800 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
801 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
802 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
803
804 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
805 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
806 (rt2x00dev->rx->data_size / 128));
807 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
808
809 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
810
811 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
812 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
813
814 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
815 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
816 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
817
818 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
819 /*
820 * Tx power.
821 */
822 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3);
823 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
824 /*
825 * Signal.
826 */
827 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32);
828 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
829 /*
830 * Rssi.
831 */
832 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36);
833 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
834 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
835
836 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
837 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
838 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
839 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
840 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
841 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
842
843 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
844 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
845 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
846 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
847 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
848
849 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
850 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
851 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
852 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
853
854 /*
855 * We must clear the FCS and FIFO error count.
856 * These registers are cleared on read,
857 * so we may pass a useless variable to store the value.
858 */
859 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
860 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
861
862 return 0;
863 }
864
865 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
866 {
867 unsigned int i;
868 u16 eeprom;
869 u8 reg_id;
870 u8 value;
871
872 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
873 rt2400pci_bbp_read(rt2x00dev, 0, &value);
874 if ((value != 0xff) && (value != 0x00))
875 goto continue_csr_init;
876 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
877 udelay(REGISTER_BUSY_DELAY);
878 }
879
880 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
881 return -EACCES;
882
883 continue_csr_init:
884 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
885 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
886 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
887 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
888 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
889 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
890 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
891 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
892 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
893 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
894 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
895 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
896 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
897 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
898 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
899
900 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
901 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
902 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
903
904 if (eeprom != 0xffff && eeprom != 0x0000) {
905 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
906 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
907 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
908 reg_id, value);
909 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
910 }
911 }
912 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
913
914 return 0;
915 }
916
917 /*
918 * Device state switch handlers.
919 */
920 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
921 enum dev_state state)
922 {
923 u32 reg;
924
925 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
926 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
927 state == STATE_RADIO_RX_OFF);
928 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
929 }
930
931 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, int enabled)
932 {
933 u32 reg;
934
935 /*
936 * When interrupts are being enabled, the interrupt registers
937 * should clear the register to assure a clean state.
938 */
939 if (enabled) {
940 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
941 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
942 }
943
944 /*
945 * Only toggle the interrupts bits we are going to use.
946 * Non-checked interrupt bits are disabled by default.
947 */
948 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
949 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, !enabled);
950 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, !enabled);
951 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, !enabled);
952 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, !enabled);
953 rt2x00_set_field32(&reg, CSR8_RXDONE, !enabled);
954 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
955 }
956
957 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
958 {
959 /*
960 * Initialize all registers.
961 */
962 if (rt2400pci_init_rings(rt2x00dev) ||
963 rt2400pci_init_registers(rt2x00dev) ||
964 rt2400pci_init_bbp(rt2x00dev)) {
965 ERROR(rt2x00dev, "Register initialization failed.\n");
966 return -EIO;
967 }
968
969 /*
970 * Enable interrupts.
971 */
972 rt2400pci_toggle_irq(rt2x00dev, 1);
973
974 /*
975 * Enable LED
976 */
977 rt2400pci_enable_led(rt2x00dev);
978
979 return 0;
980 }
981
982 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
983 {
984 u32 reg;
985
986 /*
987 * Disable LED
988 */
989 rt2400pci_disable_led(rt2x00dev);
990
991 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
992
993 /*
994 * Disable synchronisation.
995 */
996 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
997
998 /*
999 * Cancel RX and TX.
1000 */
1001 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1002 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1003 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1004
1005 /*
1006 * Disable interrupts.
1007 */
1008 rt2400pci_toggle_irq(rt2x00dev, 0);
1009 }
1010
1011 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1012 enum dev_state state)
1013 {
1014 u32 reg;
1015 unsigned int i;
1016 char put_to_sleep;
1017 char bbp_state;
1018 char rf_state;
1019
1020 put_to_sleep = (state != STATE_AWAKE);
1021
1022 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1023 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1024 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1025 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1026 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1027 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1028
1029 /*
1030 * Device is not guaranteed to be in the requested state yet.
1031 * We must wait until the register indicates that the
1032 * device has entered the correct state.
1033 */
1034 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1035 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1036 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1037 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1038 if (bbp_state == state && rf_state == state)
1039 return 0;
1040 msleep(10);
1041 }
1042
1043 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1044 "current device state: bbp %d and rf %d.\n",
1045 state, bbp_state, rf_state);
1046
1047 return -EBUSY;
1048 }
1049
1050 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1051 enum dev_state state)
1052 {
1053 int retval = 0;
1054
1055 switch (state) {
1056 case STATE_RADIO_ON:
1057 retval = rt2400pci_enable_radio(rt2x00dev);
1058 break;
1059 case STATE_RADIO_OFF:
1060 rt2400pci_disable_radio(rt2x00dev);
1061 break;
1062 case STATE_RADIO_RX_ON:
1063 case STATE_RADIO_RX_OFF:
1064 rt2400pci_toggle_rx(rt2x00dev, state);
1065 break;
1066 case STATE_DEEP_SLEEP:
1067 case STATE_SLEEP:
1068 case STATE_STANDBY:
1069 case STATE_AWAKE:
1070 retval = rt2400pci_set_state(rt2x00dev, state);
1071 break;
1072 default:
1073 retval = -ENOTSUPP;
1074 break;
1075 }
1076
1077 return retval;
1078 }
1079
1080 /*
1081 * TX descriptor initialization
1082 */
1083 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1084 struct data_entry *entry, struct data_desc *txd,
1085 struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1086 unsigned int length, struct ieee80211_tx_control *control)
1087 {
1088 u32 word;
1089 u32 signal = 0;
1090 u32 service = 0;
1091 u32 length_high = 0;
1092 u32 length_low = 0;
1093
1094 /*
1095 * The PLCP values should be treated as if they
1096 * were BBP values.
1097 */
1098 rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1099 rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1100 rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1101
1102 rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1103 rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1104 rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1105
1106 rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1107 rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1108 rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1109
1110 rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1111 rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1112 rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1113
1114 /*
1115 * Start writing the descriptor words.
1116 */
1117 rt2x00_desc_read(txd, 2, &word);
1118 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1119 rt2x00_desc_write(txd, 2, word);
1120
1121 rt2x00_desc_read(txd, 3, &word);
1122 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1123 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1124 rt2x00_desc_write(txd, 3, word);
1125
1126 rt2x00_desc_read(txd, 4, &word);
1127 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1128 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1129 rt2x00_desc_write(txd, 4, word);
1130
1131 rt2x00_desc_read(txd, 0, &word);
1132 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1133 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1134 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1135 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1136 rt2x00_set_field32(&word, TXD_W0_ACK,
1137 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1138 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1139 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1140 rt2x00_set_field32(&word, TXD_W0_RTS,
1141 test_bit(ENTRY_TXD_RTS_FRAME, &entry->flags));
1142 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1143 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1144 rt2x00_desc_write(txd, 0, word);
1145 }
1146
1147 /*
1148 * TX data initialization
1149 */
1150 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1151 {
1152 u32 reg;
1153
1154 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1155 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1156 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1157 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1158 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1159 }
1160 return;
1161 }
1162
1163 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1164 if (queue == IEEE80211_TX_QUEUE_DATA0)
1165 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1166 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1167 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1168 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1169 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1170 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1171 }
1172
1173 /*
1174 * RX control handlers
1175 */
1176 static int rt2400pci_fill_rxdone(struct data_entry *entry,
1177 int *signal, int *rssi, int *ofdm)
1178 {
1179 struct data_desc *rxd = entry->priv;
1180 u32 word0;
1181 u32 word2;
1182
1183 rt2x00_desc_read(rxd, 0, &word0);
1184 rt2x00_desc_read(rxd, 2, &word2);
1185
1186 /*
1187 * TODO: Don't we need to keep statistics
1188 * updated about these errors?
1189 */
1190 if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
1191 rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1192 return -EINVAL;
1193
1194 /*
1195 * Obtain the status about this packet.
1196 */
1197 *signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1198 *rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1199 entry->ring->rt2x00dev->rssi_offset;
1200 *ofdm = 0;
1201
1202 return rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1203 }
1204
1205 /*
1206 * Interrupt functions.
1207 */
1208 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1209 {
1210 struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
1211 struct data_entry *entry;
1212 struct data_desc *txd;
1213 u32 word;
1214 int tx_status;
1215 int retry;
1216
1217 while (!rt2x00_ring_empty(ring)) {
1218 entry = rt2x00_get_data_entry_done(ring);
1219 txd = entry->priv;
1220 rt2x00_desc_read(txd, 0, &word);
1221
1222 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1223 !rt2x00_get_field32(word, TXD_W0_VALID))
1224 break;
1225
1226 /*
1227 * Obtain the status about this packet.
1228 */
1229 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1230 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1231
1232 rt2x00lib_txdone(entry, tx_status, retry);
1233
1234 /*
1235 * Make this entry available for reuse.
1236 */
1237 entry->flags = 0;
1238 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1239 rt2x00_desc_write(txd, 0, word);
1240 rt2x00_ring_index_done_inc(ring);
1241 }
1242
1243 /*
1244 * If the data ring was full before the txdone handler
1245 * we must make sure the packet queue in the mac80211 stack
1246 * is reenabled when the txdone handler has finished.
1247 */
1248 entry = ring->entry;
1249 if (!rt2x00_ring_full(ring))
1250 ieee80211_wake_queue(rt2x00dev->hw,
1251 entry->tx_status.control.queue);
1252 }
1253
1254 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1255 {
1256 struct rt2x00_dev *rt2x00dev = dev_instance;
1257 u32 reg;
1258
1259 /*
1260 * Get the interrupt sources & saved to local variable.
1261 * Write register value back to clear pending interrupts.
1262 */
1263 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1264 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1265
1266 if (!reg)
1267 return IRQ_NONE;
1268
1269 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1270 return IRQ_HANDLED;
1271
1272 /*
1273 * Handle interrupts, walk through all bits
1274 * and run the tasks, the bits are checked in order of
1275 * priority.
1276 */
1277
1278 /*
1279 * 1 - Beacon timer expired interrupt.
1280 */
1281 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1282 rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1283
1284 /*
1285 * 2 - Rx ring done interrupt.
1286 */
1287 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1288 rt2x00pci_rxdone(rt2x00dev);
1289
1290 /*
1291 * 3 - Atim ring transmit done interrupt.
1292 */
1293 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1294 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1295
1296 /*
1297 * 4 - Priority ring transmit done interrupt.
1298 */
1299 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1300 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1301
1302 /*
1303 * 5 - Tx ring transmit done interrupt.
1304 */
1305 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1306 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1307
1308 return IRQ_HANDLED;
1309 }
1310
1311 /*
1312 * Device initialization functions.
1313 */
1314 static int rt2400pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1315 {
1316 struct eeprom_93cx6 eeprom;
1317 u32 reg;
1318 u16 word;
1319 u8 *mac;
1320
1321 /*
1322 * Allocate the eeprom memory, check the eeprom width
1323 * and copy the entire eeprom into this allocated memory.
1324 */
1325 rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1326 if (!rt2x00dev->eeprom)
1327 return -ENOMEM;
1328
1329 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1330
1331 eeprom.data = rt2x00dev;
1332 eeprom.register_read = rt2400pci_eepromregister_read;
1333 eeprom.register_write = rt2400pci_eepromregister_write;
1334 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1335 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1336 eeprom.reg_data_in = 0;
1337 eeprom.reg_data_out = 0;
1338 eeprom.reg_data_clock = 0;
1339 eeprom.reg_chip_select = 0;
1340
1341 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1342 EEPROM_SIZE / sizeof(u16));
1343
1344 /*
1345 * Start validation of the data that has been read.
1346 */
1347 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1348 if (!is_valid_ether_addr(mac)) {
1349 random_ether_addr(mac);
1350 EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
1351 }
1352
1353 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1354 if (word == 0xffff) {
1355 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1356 return -EINVAL;
1357 }
1358
1359 return 0;
1360 }
1361
1362 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1363 {
1364 u32 reg;
1365 u16 value;
1366 u16 eeprom;
1367
1368 /*
1369 * Read EEPROM word for configuration.
1370 */
1371 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1372
1373 /*
1374 * Identify RF chipset.
1375 */
1376 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1377 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1378 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1379
1380 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1381 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1382 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1383 return -ENODEV;
1384 }
1385
1386 /*
1387 * Identify default antenna configuration.
1388 */
1389 rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
1390 EEPROM_ANTENNA_TX_DEFAULT);
1391 rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
1392 EEPROM_ANTENNA_RX_DEFAULT);
1393
1394 /*
1395 * Store led mode, for correct led behaviour.
1396 */
1397 rt2x00dev->led_mode = rt2x00_get_field16(eeprom,
1398 EEPROM_ANTENNA_LED_MODE);
1399
1400 /*
1401 * Detect if this device has an hardware controlled radio.
1402 */
1403 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1404 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1405
1406 /*
1407 * Check if the BBP tuning should be enabled.
1408 */
1409 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1410 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1411
1412 return 0;
1413 }
1414
1415 /*
1416 * RF value list for RF2420 & RF2421
1417 * Supports: 2.4 GHz
1418 */
1419 static const u32 rf_vals_bg[] = {
1420 0x000c1fda, 0x000c1fee, 0x000c2002, 0x000c2016, 0x000c202a,
1421 0x000c203e, 0x000c2052, 0x000c2066, 0x000c207a, 0x000c208e,
1422 0x000c20a2, 0x000c20b6, 0x000c20ca, 0x000c20fa
1423 };
1424
1425 static void rt2400pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
1426 {
1427 struct hw_mode_spec *spec = &rt2x00dev->spec;
1428 u8 *txpower;
1429 unsigned int i;
1430
1431 /*
1432 * Initialize all hw fields.
1433 */
1434 rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON |
1435 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1436 IEEE80211_HW_WEP_INCLUDE_IV |
1437 IEEE80211_HW_DATA_NULLFUNC_ACK |
1438 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
1439 IEEE80211_HW_MONITOR_DURING_OPER |
1440 IEEE80211_HW_NO_PROBE_FILTERING;
1441 rt2x00dev->hw->extra_tx_headroom = 0;
1442 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1443 rt2x00dev->hw->max_noise = MAX_RX_NOISE;
1444 rt2x00dev->hw->queues = 2;
1445
1446 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1447 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1448 rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0));
1449
1450 /*
1451 * Set device specific, but channel independent RF values.
1452 */
1453 rt2x00dev->rf1 = 0x00022058;
1454 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
1455 rt2x00dev->rf3 = 0x00000111;
1456 else
1457 rt2x00dev->rf3 = 0x00000101;
1458
1459 /*
1460 * Convert tx_power array in eeprom.
1461 */
1462 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1463 for (i = 0; i < 14; i++)
1464 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1465
1466 /*
1467 * Initialize hw_mode information.
1468 */
1469 spec->num_modes = 1;
1470 spec->num_rates = 4;
1471 spec->num_channels = 14;
1472 spec->tx_power_a = NULL;
1473 spec->tx_power_bg = txpower;
1474 spec->tx_power_default = DEFAULT_TXPOWER;
1475 spec->chan_val_a = NULL;
1476 spec->chan_val_bg = rf_vals_bg;
1477 }
1478
1479 static int rt2400pci_init_hw(struct rt2x00_dev *rt2x00dev)
1480 {
1481 int retval;
1482
1483 /*
1484 * Allocate eeprom data.
1485 */
1486 retval = rt2400pci_alloc_eeprom(rt2x00dev);
1487 if (retval)
1488 return retval;
1489
1490 retval = rt2400pci_init_eeprom(rt2x00dev);
1491 if (retval)
1492 return retval;
1493
1494 /*
1495 * Initialize hw specifications.
1496 */
1497 rt2400pci_init_hw_mode(rt2x00dev);
1498
1499 /*
1500 * This device supports ATIM
1501 */
1502 __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
1503
1504 /*
1505 * Set the rssi offset.
1506 */
1507 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1508
1509 return 0;
1510 }
1511
1512 /*
1513 * IEEE80211 stack callback functions.
1514 */
1515 static int rt2400pci_get_stats(struct ieee80211_hw *hw,
1516 struct ieee80211_low_level_stats *stats)
1517 {
1518 struct rt2x00_dev *rt2x00dev = hw->priv;
1519 u32 reg;
1520
1521 /*
1522 * Update FCS error count from register.
1523 * The dot11ACKFailureCount, dot11RTSFailureCount and
1524 * dot11RTSSuccessCount are updated in interrupt time.
1525 */
1526 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1527 rt2x00dev->low_level_stats.dot11FCSErrorCount +=
1528 rt2x00_get_field32(reg, CNT0_FCS_ERROR);
1529
1530 memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
1531
1532 return 0;
1533 }
1534
1535 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1536 u32 short_retry, u32 long_retry)
1537 {
1538 struct rt2x00_dev *rt2x00dev = hw->priv;
1539 u32 reg;
1540
1541 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1542 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1543 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1544 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1545
1546 return 0;
1547 }
1548
1549 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1550 int queue, const struct ieee80211_tx_queue_params *params)
1551 {
1552 struct rt2x00_dev *rt2x00dev = hw->priv;
1553
1554 /*
1555 * We don't support variating cw_min and cw_max variables
1556 * per queue. So by default we only configure the TX queue,
1557 * and ignore all other configurations.
1558 */
1559 if (queue != IEEE80211_TX_QUEUE_DATA0)
1560 return -EINVAL;
1561
1562 if (rt2x00lib_conf_tx(hw, queue, params))
1563 return -EINVAL;
1564
1565 /*
1566 * Write configuration to register.
1567 */
1568 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1569
1570 return 0;
1571 }
1572
1573 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1574 {
1575 struct rt2x00_dev *rt2x00dev = hw->priv;
1576 u64 tsf;
1577 u32 reg;
1578
1579 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1580 tsf = (u64)rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1581 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1582 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1583
1584 return tsf;
1585 }
1586
1587 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1588 {
1589 struct rt2x00_dev *rt2x00dev = hw->priv;
1590
1591 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1592 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1593 }
1594
1595 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1596 {
1597 struct rt2x00_dev *rt2x00dev = hw->priv;
1598 u32 reg;
1599
1600 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1601 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1602 }
1603
1604 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1605 .tx = rt2x00lib_tx,
1606 .reset = rt2x00lib_reset,
1607 .add_interface = rt2x00lib_add_interface,
1608 .remove_interface = rt2x00lib_remove_interface,
1609 .config = rt2x00lib_config,
1610 .config_interface = rt2x00lib_config_interface,
1611 .set_multicast_list = rt2x00lib_set_multicast_list,
1612 .get_stats = rt2400pci_get_stats,
1613 .set_retry_limit = rt2400pci_set_retry_limit,
1614 .conf_tx = rt2400pci_conf_tx,
1615 .get_tx_stats = rt2x00lib_get_tx_stats,
1616 .get_tsf = rt2400pci_get_tsf,
1617 .reset_tsf = rt2400pci_reset_tsf,
1618 .beacon_update = rt2x00pci_beacon_update,
1619 .tx_last_beacon = rt2400pci_tx_last_beacon,
1620 };
1621
1622 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1623 .irq_handler = rt2400pci_interrupt,
1624 .init_hw = rt2400pci_init_hw,
1625 .initialize = rt2x00pci_initialize,
1626 .uninitialize = rt2x00pci_uninitialize,
1627 .set_device_state = rt2400pci_set_device_state,
1628 #ifdef CONFIG_RT2400PCI_RFKILL
1629 .rfkill_poll = rt2400pci_rfkill_poll,
1630 #endif /* CONFIG_RT2400PCI_RFKILL */
1631 .link_tuner = rt2400pci_link_tuner,
1632 .write_tx_desc = rt2400pci_write_tx_desc,
1633 .write_tx_data = rt2x00pci_write_tx_data,
1634 .kick_tx_queue = rt2400pci_kick_tx_queue,
1635 .fill_rxdone = rt2400pci_fill_rxdone,
1636 .config_type = rt2400pci_config_type,
1637 .config_phymode = rt2400pci_config_phymode,
1638 .config_channel = rt2400pci_config_channel,
1639 .config_mac_addr = rt2400pci_config_mac_addr,
1640 .config_bssid = rt2400pci_config_bssid,
1641 .config_promisc = rt2400pci_config_promisc,
1642 .config_txpower = rt2400pci_config_txpower,
1643 .config_antenna = rt2400pci_config_antenna,
1644 .config_duration = rt2400pci_config_duration,
1645 };
1646
1647 static const struct rt2x00_ops rt2400pci_ops = {
1648 .name = DRV_NAME,
1649 .rxd_size = RXD_DESC_SIZE,
1650 .txd_size = TXD_DESC_SIZE,
1651 .lib = &rt2400pci_rt2x00_ops,
1652 .hw = &rt2400pci_mac80211_ops,
1653 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1654 .debugfs = &rt2400pci_rt2x00debug,
1655 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1656 };
1657
1658 /*
1659 * RT2400pci module information.
1660 */
1661 static struct pci_device_id rt2400pci_device_table[] = {
1662 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1663 { 0, }
1664 };
1665
1666 MODULE_AUTHOR(DRV_PROJECT);
1667 MODULE_VERSION(DRV_VERSION);
1668 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1669 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1670 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1671 MODULE_LICENSE("GPL");
1672
1673 static struct pci_driver rt2400pci_driver = {
1674 .name = DRV_NAME,
1675 .id_table = rt2400pci_device_table,
1676 .probe = rt2x00pci_probe,
1677 .remove = __devexit_p(rt2x00pci_remove),
1678 #ifdef CONFIG_PM
1679 .suspend = rt2x00pci_suspend,
1680 .resume = rt2x00pci_resume,
1681 #endif /* CONFIG_PM */
1682 };
1683
1684 static int __init rt2400pci_init(void)
1685 {
1686 return pci_register_driver(&rt2400pci_driver);
1687 }
1688
1689 static void __exit rt2400pci_exit(void)
1690 {
1691 pci_unregister_driver(&rt2400pci_driver);
1692 }
1693
1694 module_init(rt2400pci_init);
1695 module_exit(rt2400pci_exit);
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