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0091ac276cd9965024c89becdd0e24d6f7f650a5
[openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / devices.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
25
26 #include "devices.h"
27
28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
29
30 static struct resource ar71xx_uart_resources[] = {
31 {
32 .start = AR71XX_UART_BASE,
33 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 };
37
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data[] = {
40 {
41 .mapbase = AR71XX_UART_BASE,
42 .irq = AR71XX_MISC_IRQ_UART,
43 .flags = AR71XX_UART_FLAGS,
44 .iotype = UPIO_MEM32,
45 .regshift = 2,
46 }, {
47 /* terminating entry */
48 }
49 };
50
51 static struct platform_device ar71xx_uart_device = {
52 .name = "serial8250",
53 .id = PLAT8250_DEV_PLATFORM,
54 .resource = ar71xx_uart_resources,
55 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
56 .dev = {
57 .platform_data = ar71xx_uart_data
58 },
59 };
60
61 static struct resource ar933x_uart_resources[] = {
62 {
63 .start = AR933X_UART_BASE,
64 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
65 .flags = IORESOURCE_MEM,
66 },
67 {
68 .start = AR71XX_MISC_IRQ_UART,
69 .end = AR71XX_MISC_IRQ_UART,
70 .flags = IORESOURCE_IRQ,
71 },
72 };
73
74 static struct ar933x_uart_platform_data ar933x_uart_data;
75 static struct platform_device ar933x_uart_device = {
76 .name = "ar933x-uart",
77 .id = -1,
78 .resource = ar933x_uart_resources,
79 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
80 .dev = {
81 .platform_data = &ar933x_uart_data,
82 },
83 };
84
85 void __init ar71xx_add_device_uart(void)
86 {
87 struct platform_device *pdev;
88
89 switch (ar71xx_soc) {
90 case AR71XX_SOC_AR7130:
91 case AR71XX_SOC_AR7141:
92 case AR71XX_SOC_AR7161:
93 case AR71XX_SOC_AR7240:
94 case AR71XX_SOC_AR7241:
95 case AR71XX_SOC_AR7242:
96 case AR71XX_SOC_AR9130:
97 case AR71XX_SOC_AR9132:
98 pdev = &ar71xx_uart_device;
99 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
100 break;
101
102 case AR71XX_SOC_AR9330:
103 case AR71XX_SOC_AR9331:
104 pdev = &ar933x_uart_device;
105 ar933x_uart_data.uartclk = ar71xx_ref_freq;
106 break;
107
108 case AR71XX_SOC_AR9341:
109 case AR71XX_SOC_AR9342:
110 case AR71XX_SOC_AR9344:
111 pdev = &ar71xx_uart_device;
112 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
113 break;
114
115 default:
116 BUG();
117 }
118
119 platform_device_register(pdev);
120 }
121
122 static struct resource ar71xx_mdio0_resources[] = {
123 {
124 .name = "mdio_base",
125 .flags = IORESOURCE_MEM,
126 .start = AR71XX_GE0_BASE,
127 .end = AR71XX_GE0_BASE + 0x200 - 1,
128 }
129 };
130
131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
132
133 struct platform_device ar71xx_mdio0_device = {
134 .name = "ag71xx-mdio",
135 .id = 0,
136 .resource = ar71xx_mdio0_resources,
137 .num_resources = ARRAY_SIZE(ar71xx_mdio0_resources),
138 .dev = {
139 .platform_data = &ar71xx_mdio0_data,
140 },
141 };
142
143 static struct resource ar71xx_mdio1_resources[] = {
144 {
145 .name = "mdio_base",
146 .flags = IORESOURCE_MEM,
147 .start = AR71XX_GE1_BASE,
148 .end = AR71XX_GE1_BASE + 0x200 - 1,
149 }
150 };
151
152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
153
154 struct platform_device ar71xx_mdio1_device = {
155 .name = "ag71xx-mdio",
156 .id = 1,
157 .resource = ar71xx_mdio1_resources,
158 .num_resources = ARRAY_SIZE(ar71xx_mdio1_resources),
159 .dev = {
160 .platform_data = &ar71xx_mdio1_data,
161 },
162 };
163
164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
165 {
166 void __iomem *base;
167 u32 t;
168
169 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
170
171 t = __raw_readl(base + cfg_reg);
172 t &= ~(3 << shift);
173 t |= (2 << shift);
174 __raw_writel(t, base + cfg_reg);
175 udelay(100);
176
177 __raw_writel(pll_val, base + pll_reg);
178
179 t |= (3 << shift);
180 __raw_writel(t, base + cfg_reg);
181 udelay(100);
182
183 t &= ~(3 << shift);
184 __raw_writel(t, base + cfg_reg);
185 udelay(100);
186
187 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
188 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
189
190 iounmap(base);
191 }
192
193 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
194 {
195 struct platform_device *mdio_dev;
196 struct ag71xx_mdio_platform_data *mdio_data;
197 unsigned int max_id;
198
199 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
200 ar71xx_soc == AR71XX_SOC_AR9342 ||
201 ar71xx_soc == AR71XX_SOC_AR9344)
202 max_id = 1;
203 else
204 max_id = 0;
205
206 if (id > max_id) {
207 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
208 return;
209 }
210
211 switch (ar71xx_soc) {
212 case AR71XX_SOC_AR7241:
213 case AR71XX_SOC_AR9330:
214 case AR71XX_SOC_AR9331:
215 mdio_dev = &ar71xx_mdio1_device;
216 mdio_data = &ar71xx_mdio1_data;
217 break;
218
219 case AR71XX_SOC_AR9341:
220 case AR71XX_SOC_AR9342:
221 case AR71XX_SOC_AR9344:
222 if (id == 0) {
223 mdio_dev = &ar71xx_mdio0_device;
224 mdio_data = &ar71xx_mdio0_data;
225 } else {
226 mdio_dev = &ar71xx_mdio1_device;
227 mdio_data = &ar71xx_mdio1_data;
228 }
229 break;
230
231 case AR71XX_SOC_AR7242:
232 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
233 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
234 AR71XX_ETH0_PLL_SHIFT);
235 /* fall through */
236 default:
237 mdio_dev = &ar71xx_mdio0_device;
238 mdio_data = &ar71xx_mdio0_data;
239 break;
240 }
241
242 mdio_data->phy_mask = phy_mask;
243
244 switch (ar71xx_soc) {
245 case AR71XX_SOC_AR7240:
246 case AR71XX_SOC_AR7241:
247 case AR71XX_SOC_AR9330:
248 case AR71XX_SOC_AR9331:
249 mdio_data->is_ar7240 = 1;
250 break;
251
252 case AR71XX_SOC_AR9341:
253 case AR71XX_SOC_AR9342:
254 case AR71XX_SOC_AR9344:
255 if (id == 1)
256 mdio_data->is_ar7240 = 1;
257 break;
258
259 default:
260 break;
261 }
262
263 platform_device_register(mdio_dev);
264 }
265
266 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
267 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
268
269 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
270 {
271 struct ar71xx_eth_pll_data *pll_data;
272 u32 pll_val;
273
274 switch (mac) {
275 case 0:
276 pll_data = &ar71xx_eth0_pll_data;
277 break;
278 case 1:
279 pll_data = &ar71xx_eth1_pll_data;
280 break;
281 default:
282 BUG();
283 }
284
285 switch (speed) {
286 case SPEED_10:
287 pll_val = pll_data->pll_10;
288 break;
289 case SPEED_100:
290 pll_val = pll_data->pll_100;
291 break;
292 case SPEED_1000:
293 pll_val = pll_data->pll_1000;
294 break;
295 default:
296 BUG();
297 }
298
299 return pll_val;
300 }
301
302 static void ar71xx_set_pll_ge0(int speed)
303 {
304 u32 val = ar71xx_get_eth_pll(0, speed);
305
306 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
307 val, AR71XX_ETH0_PLL_SHIFT);
308 }
309
310 static void ar71xx_set_pll_ge1(int speed)
311 {
312 u32 val = ar71xx_get_eth_pll(1, speed);
313
314 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
315 val, AR71XX_ETH1_PLL_SHIFT);
316 }
317
318 static void ar724x_set_pll_ge0(int speed)
319 {
320 /* TODO */
321 }
322
323 static void ar724x_set_pll_ge1(int speed)
324 {
325 /* TODO */
326 }
327
328 static void ar7242_set_pll_ge0(int speed)
329 {
330 u32 val = ar71xx_get_eth_pll(0, speed);
331 void __iomem *base;
332
333 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
334 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
335 iounmap(base);
336 }
337
338 static void ar91xx_set_pll_ge0(int speed)
339 {
340 u32 val = ar71xx_get_eth_pll(0, speed);
341
342 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
343 val, AR91XX_ETH0_PLL_SHIFT);
344 }
345
346 static void ar91xx_set_pll_ge1(int speed)
347 {
348 u32 val = ar71xx_get_eth_pll(1, speed);
349
350 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
351 val, AR91XX_ETH1_PLL_SHIFT);
352 }
353
354 static void ar933x_set_pll_ge0(int speed)
355 {
356 /* TODO */
357 }
358
359 static void ar933x_set_pll_ge1(int speed)
360 {
361 /* TODO */
362 }
363
364 static void ar934x_set_pll_ge0(int speed)
365 {
366 /* TODO */
367 }
368
369 static void ar934x_set_pll_ge1(int speed)
370 {
371 /* TODO */
372 }
373
374 static void ar71xx_ddr_flush_ge0(void)
375 {
376 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
377 }
378
379 static void ar71xx_ddr_flush_ge1(void)
380 {
381 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
382 }
383
384 static void ar724x_ddr_flush_ge0(void)
385 {
386 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
387 }
388
389 static void ar724x_ddr_flush_ge1(void)
390 {
391 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
392 }
393
394 static void ar91xx_ddr_flush_ge0(void)
395 {
396 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
397 }
398
399 static void ar91xx_ddr_flush_ge1(void)
400 {
401 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
402 }
403
404 static void ar933x_ddr_flush_ge0(void)
405 {
406 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
407 }
408
409 static void ar933x_ddr_flush_ge1(void)
410 {
411 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
412 }
413
414 static void ar934x_ddr_flush_ge0(void)
415 {
416 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
417 }
418
419 static void ar934x_ddr_flush_ge1(void)
420 {
421 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
422 }
423
424 static struct resource ar71xx_eth0_resources[] = {
425 {
426 .name = "mac_base",
427 .flags = IORESOURCE_MEM,
428 .start = AR71XX_GE0_BASE,
429 .end = AR71XX_GE0_BASE + 0x200 - 1,
430 }, {
431 .name = "mii_ctrl",
432 .flags = IORESOURCE_MEM,
433 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
434 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
435 }, {
436 .name = "mac_irq",
437 .flags = IORESOURCE_IRQ,
438 .start = AR71XX_CPU_IRQ_GE0,
439 .end = AR71XX_CPU_IRQ_GE0,
440 },
441 };
442
443 struct ag71xx_platform_data ar71xx_eth0_data = {
444 .reset_bit = RESET_MODULE_GE0_MAC,
445 };
446
447 struct platform_device ar71xx_eth0_device = {
448 .name = "ag71xx",
449 .id = 0,
450 .resource = ar71xx_eth0_resources,
451 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
452 .dev = {
453 .platform_data = &ar71xx_eth0_data,
454 },
455 };
456
457 static struct resource ar71xx_eth1_resources[] = {
458 {
459 .name = "mac_base",
460 .flags = IORESOURCE_MEM,
461 .start = AR71XX_GE1_BASE,
462 .end = AR71XX_GE1_BASE + 0x200 - 1,
463 }, {
464 .name = "mii_ctrl",
465 .flags = IORESOURCE_MEM,
466 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
467 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
468 }, {
469 .name = "mac_irq",
470 .flags = IORESOURCE_IRQ,
471 .start = AR71XX_CPU_IRQ_GE1,
472 .end = AR71XX_CPU_IRQ_GE1,
473 },
474 };
475
476 struct ag71xx_platform_data ar71xx_eth1_data = {
477 .reset_bit = RESET_MODULE_GE1_MAC,
478 };
479
480 struct platform_device ar71xx_eth1_device = {
481 .name = "ag71xx",
482 .id = 1,
483 .resource = ar71xx_eth1_resources,
484 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
485 .dev = {
486 .platform_data = &ar71xx_eth1_data,
487 },
488 };
489
490 #define AR71XX_PLL_VAL_1000 0x00110000
491 #define AR71XX_PLL_VAL_100 0x00001099
492 #define AR71XX_PLL_VAL_10 0x00991099
493
494 #define AR724X_PLL_VAL_1000 0x00110000
495 #define AR724X_PLL_VAL_100 0x00001099
496 #define AR724X_PLL_VAL_10 0x00991099
497
498 #define AR7242_PLL_VAL_1000 0x16000000
499 #define AR7242_PLL_VAL_100 0x00000101
500 #define AR7242_PLL_VAL_10 0x00001616
501
502 #define AR91XX_PLL_VAL_1000 0x1a000000
503 #define AR91XX_PLL_VAL_100 0x13000a44
504 #define AR91XX_PLL_VAL_10 0x00441099
505
506 #define AR933X_PLL_VAL_1000 0x00110000
507 #define AR933X_PLL_VAL_100 0x00001099
508 #define AR933X_PLL_VAL_10 0x00991099
509
510 #define AR934X_PLL_VAL_1000 0x00110000
511 #define AR934X_PLL_VAL_100 0x00001099
512 #define AR934X_PLL_VAL_10 0x00991099
513
514 static void __init ar71xx_init_eth_pll_data(unsigned int id)
515 {
516 struct ar71xx_eth_pll_data *pll_data;
517 u32 pll_10, pll_100, pll_1000;
518
519 switch (id) {
520 case 0:
521 pll_data = &ar71xx_eth0_pll_data;
522 break;
523 case 1:
524 pll_data = &ar71xx_eth1_pll_data;
525 break;
526 default:
527 BUG();
528 }
529
530 switch (ar71xx_soc) {
531 case AR71XX_SOC_AR7130:
532 case AR71XX_SOC_AR7141:
533 case AR71XX_SOC_AR7161:
534 pll_10 = AR71XX_PLL_VAL_10;
535 pll_100 = AR71XX_PLL_VAL_100;
536 pll_1000 = AR71XX_PLL_VAL_1000;
537 break;
538
539 case AR71XX_SOC_AR7240:
540 case AR71XX_SOC_AR7241:
541 pll_10 = AR724X_PLL_VAL_10;
542 pll_100 = AR724X_PLL_VAL_100;
543 pll_1000 = AR724X_PLL_VAL_1000;
544 break;
545
546 case AR71XX_SOC_AR7242:
547 pll_10 = AR7242_PLL_VAL_10;
548 pll_100 = AR7242_PLL_VAL_100;
549 pll_1000 = AR7242_PLL_VAL_1000;
550 break;
551
552 case AR71XX_SOC_AR9130:
553 case AR71XX_SOC_AR9132:
554 pll_10 = AR91XX_PLL_VAL_10;
555 pll_100 = AR91XX_PLL_VAL_100;
556 pll_1000 = AR91XX_PLL_VAL_1000;
557 break;
558
559 case AR71XX_SOC_AR9330:
560 case AR71XX_SOC_AR9331:
561 pll_10 = AR933X_PLL_VAL_10;
562 pll_100 = AR933X_PLL_VAL_100;
563 pll_1000 = AR933X_PLL_VAL_1000;
564 break;
565
566 case AR71XX_SOC_AR9341:
567 case AR71XX_SOC_AR9342:
568 case AR71XX_SOC_AR9344:
569 pll_10 = AR934X_PLL_VAL_10;
570 pll_100 = AR934X_PLL_VAL_100;
571 pll_1000 = AR934X_PLL_VAL_1000;
572 break;
573
574 default:
575 BUG();
576 }
577
578 if (!pll_data->pll_10)
579 pll_data->pll_10 = pll_10;
580
581 if (!pll_data->pll_100)
582 pll_data->pll_100 = pll_100;
583
584 if (!pll_data->pll_1000)
585 pll_data->pll_1000 = pll_1000;
586 }
587
588 static int __init ar71xx_setup_phy_if_mode(unsigned int id,
589 struct ag71xx_platform_data *pdata)
590 {
591 switch (id) {
592 case 0:
593 switch (pdata->phy_if_mode) {
594 case PHY_INTERFACE_MODE_MII:
595 pdata->mii_if = MII0_CTRL_IF_MII;
596 break;
597 case PHY_INTERFACE_MODE_GMII:
598 pdata->mii_if = MII0_CTRL_IF_GMII;
599 break;
600 case PHY_INTERFACE_MODE_RGMII:
601 pdata->mii_if = MII0_CTRL_IF_RGMII;
602 break;
603 case PHY_INTERFACE_MODE_RMII:
604 pdata->mii_if = MII0_CTRL_IF_RMII;
605 break;
606 default:
607 return -EINVAL;
608 }
609 break;
610 case 1:
611 switch (pdata->phy_if_mode) {
612 case PHY_INTERFACE_MODE_RMII:
613 pdata->mii_if = MII1_CTRL_IF_RMII;
614 break;
615 case PHY_INTERFACE_MODE_RGMII:
616 pdata->mii_if = MII1_CTRL_IF_RGMII;
617 break;
618 default:
619 return -EINVAL;
620 }
621 break;
622 }
623
624 return 0;
625 }
626
627 static int ar71xx_eth_instance __initdata;
628 void __init ar71xx_add_device_eth(unsigned int id)
629 {
630 struct platform_device *pdev;
631 struct ag71xx_platform_data *pdata;
632 int err;
633
634 if (id > 1) {
635 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
636 return;
637 }
638
639 ar71xx_init_eth_pll_data(id);
640
641 if (id == 0)
642 pdev = &ar71xx_eth0_device;
643 else
644 pdev = &ar71xx_eth1_device;
645
646 pdata = pdev->dev.platform_data;
647
648 err = ar71xx_setup_phy_if_mode(id, pdata);
649 if (err) {
650 printk(KERN_ERR
651 "ar71xx: invalid PHY interface mode for GE%u\n", id);
652 return;
653 }
654
655 switch (ar71xx_soc) {
656 case AR71XX_SOC_AR7130:
657 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
658 : ar71xx_ddr_flush_ge0;
659 pdata->set_pll = id ? ar71xx_set_pll_ge1
660 : ar71xx_set_pll_ge0;
661 break;
662
663 case AR71XX_SOC_AR7141:
664 case AR71XX_SOC_AR7161:
665 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
666 : ar71xx_ddr_flush_ge0;
667 pdata->set_pll = id ? ar71xx_set_pll_ge1
668 : ar71xx_set_pll_ge0;
669 pdata->has_gbit = 1;
670 break;
671
672 case AR71XX_SOC_AR7242:
673 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
674 RESET_MODULE_GE0_PHY;
675 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
676 RESET_MODULE_GE1_PHY;
677 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
678 : ar724x_ddr_flush_ge0;
679 pdata->set_pll = id ? ar724x_set_pll_ge1
680 : ar7242_set_pll_ge0;
681 pdata->has_gbit = 1;
682 pdata->is_ar724x = 1;
683
684 if (!pdata->fifo_cfg1)
685 pdata->fifo_cfg1 = 0x0010ffff;
686 if (!pdata->fifo_cfg2)
687 pdata->fifo_cfg2 = 0x015500aa;
688 if (!pdata->fifo_cfg3)
689 pdata->fifo_cfg3 = 0x01f00140;
690 break;
691
692 case AR71XX_SOC_AR7241:
693 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
694 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
695 /* fall through */
696 case AR71XX_SOC_AR7240:
697 ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
698 ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
699 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
700 : ar724x_ddr_flush_ge0;
701 pdata->set_pll = id ? ar724x_set_pll_ge1
702 : ar724x_set_pll_ge0;
703 pdata->is_ar724x = 1;
704 if (ar71xx_soc == AR71XX_SOC_AR7240)
705 pdata->is_ar7240 = 1;
706
707 if (!pdata->fifo_cfg1)
708 pdata->fifo_cfg1 = 0x0010ffff;
709 if (!pdata->fifo_cfg2)
710 pdata->fifo_cfg2 = 0x015500aa;
711 if (!pdata->fifo_cfg3)
712 pdata->fifo_cfg3 = 0x01f00140;
713 break;
714
715 case AR71XX_SOC_AR9130:
716 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
717 : ar91xx_ddr_flush_ge0;
718 pdata->set_pll = id ? ar91xx_set_pll_ge1
719 : ar91xx_set_pll_ge0;
720 pdata->is_ar91xx = 1;
721 break;
722
723 case AR71XX_SOC_AR9132:
724 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
725 : ar91xx_ddr_flush_ge0;
726 pdata->set_pll = id ? ar91xx_set_pll_ge1
727 : ar91xx_set_pll_ge0;
728 pdata->is_ar91xx = 1;
729 pdata->has_gbit = 1;
730 break;
731
732 case AR71XX_SOC_AR9330:
733 case AR71XX_SOC_AR9331:
734 ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
735 AR933X_RESET_GE0_MDIO;
736 ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
737 AR933X_RESET_GE1_MDIO;
738 pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
739 : ar933x_ddr_flush_ge0;
740 pdata->set_pll = id ? ar933x_set_pll_ge1
741 : ar933x_set_pll_ge0;
742 pdata->has_gbit = 1;
743 pdata->is_ar724x = 1;
744
745 if (!pdata->fifo_cfg1)
746 pdata->fifo_cfg1 = 0x0010ffff;
747 if (!pdata->fifo_cfg2)
748 pdata->fifo_cfg2 = 0x015500aa;
749 if (!pdata->fifo_cfg3)
750 pdata->fifo_cfg3 = 0x01f00140;
751 break;
752
753 case AR71XX_SOC_AR9341:
754 case AR71XX_SOC_AR9342:
755 case AR71XX_SOC_AR9344:
756 ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
757 AR934X_RESET_GE0_MDIO;
758 ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
759 AR934X_RESET_GE1_MDIO;
760 pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
761 : ar934x_ddr_flush_ge0;
762 pdata->set_pll = id ? ar934x_set_pll_ge1
763 : ar934x_set_pll_ge0;
764 pdata->has_gbit = 1;
765 pdata->is_ar724x = 1;
766
767 if (!pdata->fifo_cfg1)
768 pdata->fifo_cfg1 = 0x0010ffff;
769 if (!pdata->fifo_cfg2)
770 pdata->fifo_cfg2 = 0x015500aa;
771 if (!pdata->fifo_cfg3)
772 pdata->fifo_cfg3 = 0x01f00140;
773 break;
774
775 default:
776 BUG();
777 }
778
779 switch (pdata->phy_if_mode) {
780 case PHY_INTERFACE_MODE_GMII:
781 case PHY_INTERFACE_MODE_RGMII:
782 if (!pdata->has_gbit) {
783 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
784 id);
785 return;
786 }
787 /* fallthrough */
788 default:
789 break;
790 }
791
792 if (!is_valid_ether_addr(pdata->mac_addr)) {
793 random_ether_addr(pdata->mac_addr);
794 printk(KERN_DEBUG
795 "ar71xx: using random MAC address for eth%d\n",
796 ar71xx_eth_instance);
797 }
798
799 if (pdata->mii_bus_dev == NULL) {
800 switch (ar71xx_soc) {
801 case AR71XX_SOC_AR9341:
802 case AR71XX_SOC_AR9342:
803 case AR71XX_SOC_AR9344:
804 if (id == 0)
805 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
806 else
807 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
808 break;
809
810 case AR71XX_SOC_AR7241:
811 case AR71XX_SOC_AR9330:
812 case AR71XX_SOC_AR9331:
813 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
814 break;
815
816 default:
817 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
818 break;
819 }
820 }
821
822 /* Reset the device */
823 ar71xx_device_stop(pdata->reset_bit);
824 mdelay(100);
825
826 ar71xx_device_start(pdata->reset_bit);
827 mdelay(100);
828
829 platform_device_register(pdev);
830 ar71xx_eth_instance++;
831 }
832
833 static struct resource ar71xx_spi_resources[] = {
834 [0] = {
835 .start = AR71XX_SPI_BASE,
836 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
837 .flags = IORESOURCE_MEM,
838 },
839 };
840
841 static struct platform_device ar71xx_spi_device = {
842 .name = "ar71xx-spi",
843 .id = -1,
844 .resource = ar71xx_spi_resources,
845 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
846 };
847
848 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
849 struct spi_board_info const *info,
850 unsigned n)
851 {
852 spi_register_board_info(info, n);
853 ar71xx_spi_device.dev.platform_data = pdata;
854 platform_device_register(&ar71xx_spi_device);
855 }
856
857 void __init ar71xx_add_device_wdt(void)
858 {
859 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
860 }
861
862 void __init ar71xx_set_mac_base(unsigned char *mac)
863 {
864 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
865 }
866
867 void __init ar71xx_parse_mac_addr(char *mac_str)
868 {
869 u8 tmp[ETH_ALEN];
870 int t;
871
872 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
873 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
874
875 if (t != ETH_ALEN)
876 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
877 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
878
879 if (t == ETH_ALEN)
880 ar71xx_set_mac_base(tmp);
881 else
882 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
883 "\"%s\"\n", mac_str);
884 }
885
886 static int __init ar71xx_ethaddr_setup(char *str)
887 {
888 ar71xx_parse_mac_addr(str);
889 return 1;
890 }
891 __setup("ethaddr=", ar71xx_ethaddr_setup);
892
893 static int __init ar71xx_kmac_setup(char *str)
894 {
895 ar71xx_parse_mac_addr(str);
896 return 1;
897 }
898 __setup("kmac=", ar71xx_kmac_setup);
899
900 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
901 unsigned offset)
902 {
903 u32 t;
904
905 if (!is_valid_ether_addr(src)) {
906 memset(dst, '\0', ETH_ALEN);
907 return;
908 }
909
910 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
911 t += offset;
912
913 dst[0] = src[0];
914 dst[1] = src[1];
915 dst[2] = src[2];
916 dst[3] = (t >> 16) & 0xff;
917 dst[4] = (t >> 8) & 0xff;
918 dst[5] = t & 0xff;
919 }
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