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01f75755d4c3b9e5d09773dc5c2c90b7cbbb1465
[openwrt.git] / openwrt / target / linux / brcm-2.6 / patches / 004-b44_bcm47xx_support.patch
1 diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
2 --- linux.old/drivers/net/b44.c 2006-01-12 01:44:42.548326000 +0100
3 +++ linux.dev/drivers/net/b44.c 2006-01-13 17:30:08.283122500 +0100
4 @@ -1,7 +1,9 @@
5 -/* b44.c: Broadcom 4400 device driver.
6 +/* b44.c: Broadcom 4400/47xx device driver.
7 *
8 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
13 *
14 * Distribute under GPL.
15 */
16 @@ -31,6 +33,28 @@
17 #define DRV_MODULE_VERSION "0.97"
18 #define DRV_MODULE_RELDATE "Nov 30, 2005"
19
20 +#ifdef CONFIG_BCM947XX
21 +extern char *nvram_get(char *name);
22 +static inline void e_aton(char *str, char *dest)
23 +{
24 + int i = 0;
25 +
26 + if (str == NULL) {
27 + memset(dest, 0, 6);
28 + return;
29 + }
30 +
31 + for (;;) {
32 + dest[i++] = (char) simple_strtoul(str, NULL, 16);
33 + str += 2;
34 + if (!*str++ || i == 6)
35 + break;
36 + }
37 +}
38 +
39 +static int b44_4713_instance;
40 +#endif
41 +
42 #define B44_DEF_MSG_ENABLE \
43 (NETIF_MSG_DRV | \
44 NETIF_MSG_PROBE | \
45 @@ -77,8 +101,8 @@
46 static char version[] __devinitdata =
47 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
48
49 -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
50 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
51 +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
52 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
53 MODULE_LICENSE("GPL");
54 MODULE_VERSION(DRV_MODULE_VERSION);
55
56 @@ -93,6 +117,10 @@
57 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
58 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
59 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
60 +#ifdef CONFIG_BCM947XX
61 + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
62 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
63 +#endif
64 { } /* terminate list with empty entry */
65 };
66
67 @@ -131,17 +159,6 @@
68 dma_desc_sync_size, dir);
69 }
70
71 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
72 -{
73 - return readl(bp->regs + reg);
74 -}
75 -
76 -static inline void bw32(const struct b44 *bp,
77 - unsigned long reg, unsigned long val)
78 -{
79 - writel(val, bp->regs + reg);
80 -}
81 -
82 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
83 u32 bit, unsigned long timeout, const int clear)
84 {
85 @@ -268,6 +285,10 @@
86 break;
87 };
88 #endif
89 +#ifdef CONFIG_BCM947XX
90 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
91 + return b44_4713_instance++;
92 +#endif
93 return 0;
94 }
95
96 @@ -313,14 +334,14 @@
97 bw32(bp, B44_IMASK, bp->imask);
98 }
99
100 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
101 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
102 {
103 int err;
104
105 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
106 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
107 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
108 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
109 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
110 (reg << MDIO_DATA_RA_SHIFT) |
111 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
112 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
113 @@ -329,18 +350,34 @@
114 return err;
115 }
116
117 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
118 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
119 {
120 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
121 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
122 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
123 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
124 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
125 (reg << MDIO_DATA_RA_SHIFT) |
126 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
127 (val & MDIO_DATA_DATA)));
128 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
129 }
130
131 +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
132 +{
133 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
134 + return 0;
135 +
136 + return __b44_readphy(bp, bp->phy_addr, reg, val);
137 +}
138 +
139 +static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
140 +{
141 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
142 + return 0;
143 +
144 + return __b44_writephy(bp, bp->phy_addr, reg, val);
145 +}
146 +
147 /* miilib interface */
148 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
149 * due to code existing before miilib use was added to this driver.
150 @@ -369,6 +406,8 @@
151 u32 val;
152 int err;
153
154 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
155 + return 0;
156 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
157 if (err)
158 return err;
159 @@ -439,6 +478,18 @@
160 u32 val;
161 int err;
162
163 +#ifdef CONFIG_BCM947XX
164 + char *s;
165 + if ((s = nvram_get("boardnum")) && (s != NULL) && \
166 + !strncmp(s, "2", 1) && \
167 + (__b44_readphy(bp, 0, MII_BMCR, &val) != 0) && \
168 + (val & BMCR_ISOLATE) && \
169 + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
170 + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
171 + }
172 +#endif
173 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
174 + return 0;
175 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
176 goto out;
177 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
178 @@ -534,6 +585,19 @@
179 {
180 u32 bmsr, aux;
181
182 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
183 + bp->flags |= B44_FLAG_100_BASE_T;
184 + bp->flags |= B44_FLAG_FULL_DUPLEX;
185 + if (!netif_carrier_ok(bp->dev)) {
186 + u32 val = br32(bp, B44_TX_CTRL);
187 + val |= TX_CTRL_DUPLEX;
188 + bw32(bp, B44_TX_CTRL, val);
189 + netif_carrier_on(bp->dev);
190 + b44_link_report(bp);
191 + }
192 + return;
193 + }
194 +
195 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
196 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
197 (bmsr != 0xffff)) {
198 @@ -1281,9 +1345,10 @@
199 bw32(bp, B44_DMARX_CTRL, 0);
200 bp->rx_prod = bp->rx_cons = 0;
201 } else {
202 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
203 - SBINTVEC_ENET0 :
204 - SBINTVEC_ENET1));
205 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
206 + ssb_pci_setup(bp, (bp->core_unit == 0 ?
207 + SBINTVEC_ENET0 :
208 + SBINTVEC_ENET1));
209 }
210
211 ssb_core_reset(bp);
212 @@ -1291,8 +1356,14 @@
213 b44_clear_stats(bp);
214
215 /* Make PHY accessible. */
216 - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
217 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
218 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
219 + (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
220 + & MDIO_CTRL_MAXF_MASK)));
221 + else
222 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
223 (0x0d & MDIO_CTRL_MAXF_MASK)));
224 +
225 br32(bp, B44_MDIO_CTRL);
226
227 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
228 @@ -1834,18 +1905,297 @@
229 .get_perm_addr = ethtool_op_get_perm_addr,
230 };
231
232 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
233 +{
234 + struct b44 *bp = dev->priv;
235 + struct pci_dev *pci_dev = bp->pdev;
236 + u32 ethcmd;
237 +
238 + if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
239 + return -EFAULT;
240 +
241 + switch (ethcmd) {
242 + case ETHTOOL_GDRVINFO: {
243 + struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
244 + strcpy (info.driver, DRV_MODULE_NAME);
245 + strcpy (info.version, DRV_MODULE_VERSION);
246 + memset(&info.fw_version, 0, sizeof(info.fw_version));
247 + strcpy (info.bus_info, pci_name(pci_dev));
248 + info.eedump_len = 0;
249 + info.regdump_len = 0;
250 + if (copy_to_user (useraddr, &info, sizeof (info)))
251 + return -EFAULT;
252 + return 0;
253 + }
254 +
255 + case ETHTOOL_GSET: {
256 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
257 +
258 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
259 + return -EAGAIN;
260 + cmd.supported = (SUPPORTED_Autoneg);
261 + cmd.supported |= (SUPPORTED_100baseT_Half |
262 + SUPPORTED_100baseT_Full |
263 + SUPPORTED_10baseT_Half |
264 + SUPPORTED_10baseT_Full |
265 + SUPPORTED_MII);
266 +
267 + cmd.advertising = 0;
268 + if (bp->flags & B44_FLAG_ADV_10HALF)
269 + cmd.advertising |= ADVERTISE_10HALF;
270 + if (bp->flags & B44_FLAG_ADV_10FULL)
271 + cmd.advertising |= ADVERTISE_10FULL;
272 + if (bp->flags & B44_FLAG_ADV_100HALF)
273 + cmd.advertising |= ADVERTISE_100HALF;
274 + if (bp->flags & B44_FLAG_ADV_100FULL)
275 + cmd.advertising |= ADVERTISE_100FULL;
276 + cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
277 + cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
278 + SPEED_100 : SPEED_10;
279 + cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
280 + DUPLEX_FULL : DUPLEX_HALF;
281 + cmd.port = 0;
282 + cmd.phy_address = bp->phy_addr;
283 + cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
284 + XCVR_INTERNAL : XCVR_EXTERNAL;
285 + cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
286 + AUTONEG_DISABLE : AUTONEG_ENABLE;
287 + cmd.maxtxpkt = 0;
288 + cmd.maxrxpkt = 0;
289 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
290 + return -EFAULT;
291 + return 0;
292 + }
293 + case ETHTOOL_SSET: {
294 + struct ethtool_cmd cmd;
295 +
296 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
297 + return -EAGAIN;
298 +
299 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
300 + return -EFAULT;
301 +
302 + /* We do not support gigabit. */
303 + if (cmd.autoneg == AUTONEG_ENABLE) {
304 + if (cmd.advertising &
305 + (ADVERTISED_1000baseT_Half |
306 + ADVERTISED_1000baseT_Full))
307 + return -EINVAL;
308 + } else if ((cmd.speed != SPEED_100 &&
309 + cmd.speed != SPEED_10) ||
310 + (cmd.duplex != DUPLEX_HALF &&
311 + cmd.duplex != DUPLEX_FULL)) {
312 + return -EINVAL;
313 + }
314 +
315 + spin_lock_irq(&bp->lock);
316 +
317 + if (cmd.autoneg == AUTONEG_ENABLE) {
318 + bp->flags &= ~B44_FLAG_FORCE_LINK;
319 + bp->flags &= ~(B44_FLAG_ADV_10HALF |
320 + B44_FLAG_ADV_10FULL |
321 + B44_FLAG_ADV_100HALF |
322 + B44_FLAG_ADV_100FULL);
323 + if (cmd.advertising & ADVERTISE_10HALF)
324 + bp->flags |= B44_FLAG_ADV_10HALF;
325 + if (cmd.advertising & ADVERTISE_10FULL)
326 + bp->flags |= B44_FLAG_ADV_10FULL;
327 + if (cmd.advertising & ADVERTISE_100HALF)
328 + bp->flags |= B44_FLAG_ADV_100HALF;
329 + if (cmd.advertising & ADVERTISE_100FULL)
330 + bp->flags |= B44_FLAG_ADV_100FULL;
331 + } else {
332 + bp->flags |= B44_FLAG_FORCE_LINK;
333 + if (cmd.speed == SPEED_100)
334 + bp->flags |= B44_FLAG_100_BASE_T;
335 + if (cmd.duplex == DUPLEX_FULL)
336 + bp->flags |= B44_FLAG_FULL_DUPLEX;
337 + }
338 +
339 + b44_setup_phy(bp);
340 +
341 + spin_unlock_irq(&bp->lock);
342 +
343 + return 0;
344 + }
345 +
346 + case ETHTOOL_GMSGLVL: {
347 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
348 + edata.data = bp->msg_enable;
349 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
350 + return -EFAULT;
351 + return 0;
352 + }
353 + case ETHTOOL_SMSGLVL: {
354 + struct ethtool_value edata;
355 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
356 + return -EFAULT;
357 + bp->msg_enable = edata.data;
358 + return 0;
359 + }
360 + case ETHTOOL_NWAY_RST: {
361 + u32 bmcr;
362 + int r;
363 +
364 + spin_lock_irq(&bp->lock);
365 + b44_readphy(bp, MII_BMCR, &bmcr);
366 + b44_readphy(bp, MII_BMCR, &bmcr);
367 + r = -EINVAL;
368 + if (bmcr & BMCR_ANENABLE) {
369 + b44_writephy(bp, MII_BMCR,
370 + bmcr | BMCR_ANRESTART);
371 + r = 0;
372 + }
373 + spin_unlock_irq(&bp->lock);
374 +
375 + return r;
376 + }
377 + case ETHTOOL_GLINK: {
378 + struct ethtool_value edata = { ETHTOOL_GLINK };
379 + edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
380 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
381 + return -EFAULT;
382 + return 0;
383 + }
384 + case ETHTOOL_GRINGPARAM: {
385 + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
386 +
387 + ering.rx_max_pending = B44_RX_RING_SIZE - 1;
388 + ering.rx_pending = bp->rx_pending;
389 +
390 + /* XXX ethtool lacks a tx_max_pending, oops... */
391 +
392 + if (copy_to_user(useraddr, &ering, sizeof(ering)))
393 + return -EFAULT;
394 + return 0;
395 + }
396 + case ETHTOOL_SRINGPARAM: {
397 + struct ethtool_ringparam ering;
398 +
399 + if (copy_from_user(&ering, useraddr, sizeof(ering)))
400 + return -EFAULT;
401 +
402 + if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
403 + (ering.rx_mini_pending != 0) ||
404 + (ering.rx_jumbo_pending != 0) ||
405 + (ering.tx_pending > B44_TX_RING_SIZE - 1))
406 + return -EINVAL;
407 +
408 + spin_lock_irq(&bp->lock);
409 +
410 + bp->rx_pending = ering.rx_pending;
411 + bp->tx_pending = ering.tx_pending;
412 +
413 + b44_halt(bp);
414 + b44_init_rings(bp);
415 + b44_init_hw(bp);
416 + netif_wake_queue(bp->dev);
417 + spin_unlock_irq(&bp->lock);
418 +
419 + b44_enable_ints(bp);
420 +
421 + return 0;
422 + }
423 + case ETHTOOL_GPAUSEPARAM: {
424 + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
425 +
426 + epause.autoneg =
427 + (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
428 + epause.rx_pause =
429 + (bp->flags & B44_FLAG_RX_PAUSE) != 0;
430 + epause.tx_pause =
431 + (bp->flags & B44_FLAG_TX_PAUSE) != 0;
432 + if (copy_to_user(useraddr, &epause, sizeof(epause)))
433 + return -EFAULT;
434 + return 0;
435 + }
436 + case ETHTOOL_SPAUSEPARAM: {
437 + struct ethtool_pauseparam epause;
438 +
439 + if (copy_from_user(&epause, useraddr, sizeof(epause)))
440 + return -EFAULT;
441 +
442 + spin_lock_irq(&bp->lock);
443 + if (epause.autoneg)
444 + bp->flags |= B44_FLAG_PAUSE_AUTO;
445 + else
446 + bp->flags &= ~B44_FLAG_PAUSE_AUTO;
447 + if (epause.rx_pause)
448 + bp->flags |= B44_FLAG_RX_PAUSE;
449 + else
450 + bp->flags &= ~B44_FLAG_RX_PAUSE;
451 + if (epause.tx_pause)
452 + bp->flags |= B44_FLAG_TX_PAUSE;
453 + else
454 + bp->flags &= ~B44_FLAG_TX_PAUSE;
455 + if (bp->flags & B44_FLAG_PAUSE_AUTO) {
456 + b44_halt(bp);
457 + b44_init_rings(bp);
458 + b44_init_hw(bp);
459 + } else {
460 + __b44_set_flow_ctrl(bp, bp->flags);
461 + }
462 + spin_unlock_irq(&bp->lock);
463 +
464 + b44_enable_ints(bp);
465 +
466 + return 0;
467 + }
468 + };
469 +
470 + return -EOPNOTSUPP;
471 +}
472 +
473 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
474 {
475 struct mii_ioctl_data *data = if_mii(ifr);
476 struct b44 *bp = netdev_priv(dev);
477 int err = -EINVAL;
478
479 - if (!netif_running(dev))
480 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) {
481 + if (!netif_running(dev))
482 + goto out;
483 +
484 + spin_lock_irq(&bp->lock);
485 + err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
486 + spin_unlock_irq(&bp->lock);
487 goto out;
488 + }
489
490 - spin_lock_irq(&bp->lock);
491 - err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
492 - spin_unlock_irq(&bp->lock);
493 + switch (cmd) {
494 + case SIOCETHTOOL:
495 + return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
496 +
497 + case SIOCGMIIPHY:
498 + data->phy_id = bp->phy_addr;
499 +
500 + /* fallthru */
501 + case SIOCGMIIREG: {
502 + u32 mii_regval;
503 + spin_lock_irq(&bp->lock);
504 + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
505 + spin_unlock_irq(&bp->lock);
506 +
507 + data->val_out = mii_regval;
508 +
509 + return err;
510 + }
511 +
512 + case SIOCSMIIREG:
513 + if (!capable(CAP_NET_ADMIN))
514 + return -EPERM;
515 +
516 + spin_lock_irq(&bp->lock);
517 + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
518 + spin_unlock_irq(&bp->lock);
519 +
520 + return err;
521 +
522 + default:
523 + break;
524 + };
525 + return -EOPNOTSUPP;
526 +
527 out:
528 return err;
529 }
530 @@ -1865,22 +2215,43 @@
531 static int __devinit b44_get_invariants(struct b44 *bp)
532 {
533 u8 eeprom[128];
534 - int err;
535 + u8 buf[32];
536 + int err = 0;
537
538 - err = b44_read_eeprom(bp, &eeprom[0]);
539 - if (err)
540 - goto out;
541 -
542 - bp->dev->dev_addr[0] = eeprom[79];
543 - bp->dev->dev_addr[1] = eeprom[78];
544 - bp->dev->dev_addr[2] = eeprom[81];
545 - bp->dev->dev_addr[3] = eeprom[80];
546 - bp->dev->dev_addr[4] = eeprom[83];
547 - bp->dev->dev_addr[5] = eeprom[82];
548 - memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
549 -
550 - bp->phy_addr = eeprom[90] & 0x1f;
551 +#ifdef CONFIG_BCM947XX
552 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
553 + /*
554 + * BCM47xx boards don't have a EEPROM. The MAC is stored in
555 + * a NVRAM area somewhere in the flash memory.
556 + */
557 + sprintf(buf, "et%dmacaddr", b44_4713_instance);
558 + e_aton(nvram_get(buf), bp->dev->dev_addr);
559
560 + /*
561 + * BCM47xx boards don't have a PHY. Usually there is a switch
562 + * chip with multiple PHYs connected to the PHY port.
563 + */
564 + bp->phy_addr = B44_PHY_ADDR_NO_PHY;
565 + bp->dma_offset = 0;
566 + } else
567 +#endif
568 + {
569 + err = b44_read_eeprom(bp, &eeprom[0]);
570 + if (err)
571 + goto out;
572 +
573 + bp->dev->dev_addr[0] = eeprom[79];
574 + bp->dev->dev_addr[1] = eeprom[78];
575 + bp->dev->dev_addr[2] = eeprom[81];
576 + bp->dev->dev_addr[3] = eeprom[80];
577 + bp->dev->dev_addr[4] = eeprom[83];
578 + bp->dev->dev_addr[5] = eeprom[82];
579 + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
580 +
581 + bp->phy_addr = eeprom[90] & 0x1f;
582 + bp->dma_offset = SB_PCI_DMA;
583 + }
584 +
585 /* With this, plus the rx_header prepended to the data by the
586 * hardware, we'll land the ethernet header on a 2-byte boundary.
587 */
588 @@ -1889,11 +2260,7 @@
589 bp->imask = IMASK_DEF;
590
591 bp->core_unit = ssb_core_unit(bp);
592 - bp->dma_offset = SB_PCI_DMA;
593
594 - /* XXX - really required?
595 - bp->flags |= B44_FLAG_BUGGY_TXPTR;
596 - */
597 out:
598 return err;
599 }
600 @@ -2032,11 +2399,17 @@
601
602 pci_save_state(bp->pdev);
603
604 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
605 + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
606 + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
607 for (i = 0; i < 6; i++)
608 printk("%2.2x%c", dev->dev_addr[i],
609 i == 5 ? '\n' : ':');
610
611 + /* Initialize phy */
612 + spin_lock_irq(&bp->lock);
613 + b44_chip_reset(bp);
614 + spin_unlock_irq(&bp->lock);
615 +
616 return 0;
617
618 err_out_iounmap:
619 diff -urN linux.old/drivers/net/b44.h linux.dev/drivers/net/b44.h
620 --- linux.old/drivers/net/b44.h 2006-01-12 01:44:42.548326000 +0100
621 +++ linux.dev/drivers/net/b44.h 2006-01-12 02:55:06.290783500 +0100
622 @@ -292,6 +292,10 @@
623 #define SSB_PCI_MASK1 0xfc000000
624 #define SSB_PCI_MASK2 0xc0000000
625
626 +#define br32(bp, REG) readl((void *)bp->regs + (REG))
627 +#define bw32(bp, REG,VAL) writel((VAL), (void *)bp->regs + (REG))
628 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
629 +
630 /* 4400 PHY registers */
631 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
632 #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
633 @@ -345,6 +349,8 @@
634 };
635
636 #define B44_MCAST_TABLE_SIZE 32
637 +#define B44_PHY_ADDR_NO_PHY 30
638 +#define B44_MDC_RATIO 5000000
639
640 #define B44_STAT_REG_DECLARE \
641 _B44(tx_good_octets) \
642 @@ -420,6 +426,7 @@
643
644 u32 dma_offset;
645 u32 flags;
646 +#define B44_FLAG_INIT_COMPLETE 0x00000001
647 #define B44_FLAG_BUGGY_TXPTR 0x00000002
648 #define B44_FLAG_REORDER_BUG 0x00000004
649 #define B44_FLAG_PAUSE_AUTO 0x00008000
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