target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2005 infineon
  17  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  18  *
  19  */
  20 #ifndef _IFXMIPS_DMA_H__
  21 #define _IFXMIPS_DMA_H__
  22
  23 #define RCV_INT                                                 1
  24 #define TX_BUF_FULL_INT                                 2
  25 #define TRANSMIT_CPT_INT                                4
  26 #define IFXMIPS_DMA_CH_ON                               1
  27 #define IFXMIPS_DMA_CH_OFF                              0
  28 #define IFXMIPS_DMA_CH_DEFAULT_WEIGHT   100
  29
  30 enum attr_t{
  31         TX = 0,
  32         RX = 1,
  33         RESERVED = 2,
  34         DEFAULT = 3,
  35 };
  36
  37 #define DMA_OWN                                                 1
  38 #define CPU_OWN                                                 0
  39 #define DMA_MAJOR                                               250
  40
  41 #define DMA_DESC_OWN_CPU                                0x0
  42 #define DMA_DESC_OWN_DMA                                0x80000000
  43 #define DMA_DESC_CPT_SET                                0x40000000
  44 #define DMA_DESC_SOP_SET                                0x20000000
  45 #define DMA_DESC_EOP_SET                                0x10000000
  46
  47 #define MISCFG_MASK                                             0x40
  48 #define RDERR_MASK                                              0x20
  49 #define CHOFF_MASK                                              0x10
  50 #define DESCPT_MASK                                             0x8
  51 #define DUR_MASK                                                0x4
  52 #define EOP_MASK                                                0x2
  53
  54 #define DMA_DROP_MASK                                   (1<<31)
  55
  56 #define IFXMIPS_DMA_RX                                  -1
  57 #define IFXMIPS_DMA_TX                                  1
  58
  59 typedef struct dma_chan_map {
  60         char dev_name[15];
  61         enum attr_t dir;
  62         int pri;
  63         int irq;
  64         int rel_chan_no;
  65 } _dma_chan_map;
  66
  67 #ifdef CONFIG_CPU_LITTLE_ENDIAN
  68 typedef struct rx_desc{
  69         u32 data_length:16;
  70         volatile u32 reserved:7;
  71         volatile u32 byte_offset:2;
  72         volatile u32 Burst_length_offset:3;
  73         volatile u32 EoP:1;
  74         volatile u32 Res:1;
  75         volatile u32 C:1;
  76         volatile u32 OWN:1;
  77         volatile u32 Data_Pointer;
  78         /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
  79 }_rx_desc;
  80
  81 typedef struct tx_desc{
  82         volatile u32 data_length:16;
  83         volatile u32 reserved1:7;
  84         volatile u32 byte_offset:5;
  85         volatile u32 EoP:1;
  86         volatile u32 SoP:1;
  87         volatile u32 C:1;
  88         volatile u32 OWN:1;
  89         volatile u32 Data_Pointer;//fix me:should be 28 bits here
  90 }_tx_desc;
  91 #else //BIG
  92 typedef struct rx_desc{
  93         union
  94         {
  95                 struct
  96                 {
  97                         volatile u32 OWN:1;
  98                         volatile u32 C:1;
  99                         volatile u32 SoP:1;
 100                         volatile u32 EoP:1;
 101                         volatile u32 Burst_length_offset:3;
 102                         volatile u32 byte_offset:2;
 103                         volatile u32 reserve:7;
 104                         volatile u32 data_length:16;
 105                 }field;
 106                 volatile u32 word;
 107         }status;
 108         volatile u32 Data_Pointer;
 109 }_rx_desc;
 110
 111 typedef struct tx_desc{
 112         union
 113         {
 114                 struct
 115                 {
 116                         volatile u32 OWN:1;
 117                         volatile u32 C:1;
 118                         volatile u32 SoP:1;
 119                         volatile u32 EoP:1;
 120                         volatile u32 byte_offset:5;
 121                         volatile u32 reserved:7;
 122                         volatile u32 data_length:16;
 123                 }field;
 124                 volatile u32 word;
 125         }status;
 126         volatile u32 Data_Pointer;
 127 }_tx_desc;
 128 #endif //ENDIAN
 129
 130 typedef struct dma_channel_info{
 131    /*relative channel number*/
 132    int rel_chan_no;
 133    /*class for this channel for QoS*/
 134    int pri;
 135    /*specify byte_offset*/
 136    int byte_offset;
 137    /*direction*/
 138    int dir;
 139    /*irq number*/
 140    int irq;
 141    /*descriptor parameter*/
 142    int desc_base;
 143    int desc_len;
 144    int curr_desc;
 145    int prev_desc;/*only used if it is a tx channel*/
 146    /*weight setting for WFQ algorithm*/
 147    int weight;
 148    int default_weight;
 149    int packet_size;
 150    int burst_len;
 151    /*on or off of this channel*/
 152    int control;
 153    /**optional information for the upper layer devices*/
 154 #if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
 155    void* opt[64];
 156 #else
 157    void* opt[25];
 158 #endif
 159    /*Pointer to the peripheral device who is using this channel*/
 160    void* dma_dev;
 161    /*channel operations*/
 162    void (*open)(struct dma_channel_info* pCh);
 163    void (*close)(struct dma_channel_info* pCh);
 164    void (*reset)(struct dma_channel_info* pCh);
 165    void (*enable_irq)(struct dma_channel_info* pCh);
 166    void (*disable_irq)(struct dma_channel_info* pCh);
 167 }_dma_channel_info;
 168
 169 typedef struct dma_device_info{
 170     /*device name of this peripheral*/
 171     char device_name[15];
 172     int reserved;
 173     int tx_burst_len;
 174     int rx_burst_len;
 175     int default_weight;
 176     int  current_tx_chan;
 177         int  current_rx_chan;
 178     int  num_tx_chan;
 179     int  num_rx_chan;
 180     int  max_rx_chan_num;
 181     int  max_tx_chan_num;
 182     _dma_channel_info* tx_chan[20];
 183     _dma_channel_info* rx_chan[20];
 184     /*functions, optional*/
 185     u8* (*buffer_alloc)(int len,int* offset, void** opt);
 186     void (*buffer_free)(u8* dataptr, void* opt);
 187     int (*intr_handler)(struct dma_device_info* info, int status);
 188     void * priv;                /* used by peripheral driver only */
 189 }_dma_device_info;
 190
 191 _dma_device_info* dma_device_reserve(char* dev_name);
 192
 193 void dma_device_release(_dma_device_info* dev);
 194
 195 void dma_device_register(_dma_device_info* info);
 196
 197 void dma_device_unregister(_dma_device_info* info);
 198
 199 int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
 200
 201 int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
 202 #endif