package/ltq-vmmc/patches/400-falcon.patch

   1 --- a/configure.in
   2 +++ b/configure.in
   3 @@ -956,14 +956,15 @@ AC_DEFINE([VMMC],[1],[enable VMMC suppor
   4  AM_CONDITIONAL(DANUBE, false)
   5  AM_CONDITIONAL(AR9, false)
   6  AM_CONDITIONAL(VR9, false)
   7 +AM_CONDITIONAL(FALCON, false)
   8  AC_ARG_WITH(device,
   9     AC_HELP_STRING(
  10 -      [--with-device=DANUBE|TWINPASS|AR9|VR9],
  11 +      [--with-device=DANUBE|TWINPASS|AR9|VR9|FALCON],
  12        [Set device type, default is DANUBE]
  13     ),
  14     [
  15        if test "$withval" = yes; then
  16 -         AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);
  17 +         AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);
  18        else
  19           case $withval in
  20             DANUBE)
  21 @@ -986,8 +987,13 @@ AC_ARG_WITH(device,
  22                 AC_DEFINE([SYSTEM_VR9],[1],[enable VR9 specific code])
  23                 AM_CONDITIONAL(VR9, true)
  24             ;;
  25 +           FALCON)
  26 +               AC_MSG_RESULT(FALCON device is used);
  27 +               AC_DEFINE([SYSTEM_FALCON],[1],[enable FALCON specific code])
  28 +               AM_CONDITIONAL(FALCON, true)
  29 +           ;;
  30             *)
  31 -               AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);
  32 +               AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);
  33             ;;
  34         esac
  35        fi
  36 --- a/src/Makefile.am
  37 +++ b/src/Makefile.am
  38 @@ -70,6 +70,11 @@ drv_vmmc_SOURCES +=\
  39     mps/drv_mps_vmmc_ar9.c
  40  endif
  41
  42 +if FALCON
  43 +drv_vmmc_SOURCES +=\
  44 +   mps/drv_mps_vmmc_falcon.c
  45 +endif
  46 +
  47  endif
  48
  49  if PMC_SUPPORT
  50 --- a/drv_version.h
  51 +++ b/drv_version.h
  52 @@ -36,6 +36,10 @@
  53  #define MIN_FW_MAJORSTEP   2
  54  #define MIN_FW_MINORSTEP   1
  55  #define MIN_FW_HOTFIXSTEP  0
  56 +#elif  defined(SYSTEM_FALCON)
  57 +#define MIN_FW_MAJORSTEP   0
  58 +#define MIN_FW_MINORSTEP   1
  59 +#define MIN_FW_HOTFIXSTEP  0
  60  #else
  61  #error unknown system
  62  #endif
  63 --- a/src/drv_vmmc_bbd.c
  64 +++ b/src/drv_vmmc_bbd.c
  65 @@ -34,6 +34,7 @@
  66  #define VMMC_WL_SDD_BASIC_CFG       0x04000400
  67  #define VMMC_WL_SDD_RING_CFG        0x04000500
  68  #define VMMC_WL_SDD_DCDC_CFG        0x04000C00
  69 +#define VMMC_WL_SDD_MWI_CFG         0x04000600
  70
  71  #define IDLE_EXT_TOGGLE_SLEEP_MS    5
  72
  73 @@ -52,6 +53,8 @@
  74  #define BBD_VMMC_MAGIC                       0x41523921 /* "AR9"  */
  75  #elif defined(SYSTEM_VR9)
  76  #define BBD_VMMC_MAGIC                       0x56523921 /* "VR9"  */
  77 +#elif defined(SYSTEM_FALCON)
  78 +#define BBD_VMMC_MAGIC                       0x46414C43 /* "FALC"  */
  79  #else
  80  #error system undefined
  81  #endif
  82 @@ -525,9 +528,6 @@ static IFX_int32_t VMMC_BBD_BlockHandler
  83     IFX_uint16_t               slic_val;
  84     IFX_int32_t                ret = IFX_SUCCESS;
  85
  86 -   TRACE(VMMC, DBG_LEVEL_LOW,
  87 -         ("bbd block with tag 0x%04X passed\n", pBBDblock->tag));
  88 -
  89     /* for FXO line allowed blocks are FXO_CRAM and TRANSPARENT */
  90     if (pCh->pALM->line_type_fxs != IFX_TRUE)
  91     {
  92 @@ -686,6 +686,7 @@ static IFX_int32_t VMMC_BBD_BlockHandler
  93              break;
  94        }
  95     } /* if */
  96 +
  97     return ret;
  98  }
  99
 100 @@ -1026,6 +1027,7 @@ static IFX_int32_t vmmc_BBD_WhiteListedC
 101           }
 102        case VMMC_WL_SDD_RING_CFG:
 103        case VMMC_WL_SDD_DCDC_CFG:
 104 +      case VMMC_WL_SDD_MWI_CFG:
 105           ret = CmdWrite (pCh->pParent, Msg.val, Msg.cmd.LENGTH);
 106           break;
 107
 108 @@ -1068,7 +1070,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
 109     IFX_uint32_t countWords;
 110     IFX_uint32_t posBytes = 0;
 111     IFX_uint8_t  lenBytes, *pByte;
 112 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 113 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 114     IFX_uint8_t  padBytes = 0;
 115  #endif
 116     IFX_uint16_t cram_offset, cram_crc,
 117 @@ -1088,7 +1090,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
 118  #ifdef SYSTEM_DANUBE
 119     /* CMD1 is a COP command  */
 120     pCmd[0] = (0x0200) | (pCh->nChannel - 1);
 121 -#elif  defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 122 +#elif  defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 123     /* SDD_Coef command */
 124     pCmd[0] = (0x0400) | (pCh->nChannel - 1);
 125     pCmd[1] = (0x0D00);
 126 @@ -1111,7 +1113,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
 127        pCmd[1] = ((cram_offset + (posBytes >> 1)) << 8);
 128        /* set CRAM data while taking care of endianess  */
 129        cpb2w (&pCmd[2], &pByte[posBytes], lenBytes);
 130 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 131 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 132        /* calculate length to download (in words = 16bit),
 133           maximum allowed length for this message is 56 Bytes = 28 Words */
 134        if (countWords > ((MAX_CMD_WORD - CMD_HDR_CNT - 1)))
 135 @@ -1140,7 +1142,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
 136        /* write Data */
 137  #if defined SYSTEM_DANUBE
 138        ret = CmdWrite (pCh->pParent, (IFX_uint32_t *) pCmd, lenBytes);
 139 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 140 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 141  #if 1
 142        /* lenBytes + 2 bytes for block offset/length which are not calculated
 143           in the download progress */
 144 --- a/src/mps/drv_mps_version.h
 145 +++ b/src/mps/drv_mps_version.h
 146 @@ -17,7 +17,7 @@
 147  #define VERSIONSTEP  2
 148  #define VERS_TYPE    5
 149
 150 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 151 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 152  #define IFX_MPS_PLATFORM_NAME "MIPS34KEc"
 153  #elif  defined(SYSTEM_DANUBE)
 154  #define IFX_MPS_PLATFORM_NAME "MIPS24KEc"
 155 --- a/src/mps/drv_mps_vmmc_linux.c
 156 +++ b/src/mps/drv_mps_vmmc_linux.c
 157 @@ -2225,7 +2225,7 @@ IFX_int32_t __init ifx_mps_init_module (
 158  #if defined(CONFIG_MIPS) && !defined(CONFIG_MIPS_UNCACHED)
 159  #if defined(SYSTEM_DANUBE)
 160     bDoCacheOps = IFX_TRUE; /* on Danube always perform cache ops */
 161 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 162 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 163     /* on AR9/VR9 cache is configured by BSP;
 164        here we check whether the D-cache is shared or partitioned;
 165        1) in case of shared D-cache all cache operations are omitted;
 166 @@ -2255,7 +2255,8 @@ IFX_int32_t __init ifx_mps_init_module (
 167
 168     /* reset the device before initializing the device driver */
 169     ifx_mps_reset ();
 170 -   result = request_irq (INT_NUM_IM4_IRL18,
 171 +
 172 +  result = request_irq (INT_NUM_IM4_IRL18,
 173  #ifdef LINUX_2_6
 174                           ifx_mps_ad0_irq, IRQF_DISABLED
 175  #else /* */
 176 @@ -2396,7 +2397,7 @@ IFX_int32_t __init ifx_mps_init_module (
 177     if (result = ifx_mps_init_gpt_danube ())
 178        return result;
 179  #endif /*DANUBE*/
 180 -      TRACE (MPS, DBG_LEVEL_HIGH, ("Downloading Firmware...\n"));
 181 +   TRACE (MPS, DBG_LEVEL_HIGH, ("Downloading Firmware...\n"));
 182     ifx_mps_download_firmware (IFX_NULL, (mps_fw *) 0xa0a00000);
 183     udelay (500);
 184     TRACE (MPS, DBG_LEVEL_HIGH, ("Providing Buffers...\n"));
 185 --- /dev/null
 186 +++ b/src/mps/drv_mps_vmmc_falcon.c
 187 @@ -0,0 +1,463 @@
 188 +/******************************************************************************
 189 +
 190 +                              Copyright (c) 2009
 191 +                            Lantiq Deutschland GmbH
 192 +                     Am Campeon 3; 85579 Neubiberg, Germany
 193 +
 194 +  For licensing information, see the file 'LICENSE' in the root folder of
 195 +  this software module.
 196 +
 197 +****************************************************************************
 198 +   Module      : drv_mps_vmmc_falcon.c
 199 +   Description : This file contains the implementation of the FALC-ON specific
 200 +                 driver functions.
 201 +*******************************************************************************/
 202 +
 203 +/* ============================= */
 204 +/* Includes                      */
 205 +/* ============================= */
 206 +#include "drv_config.h"
 207 +
 208 +#if defined(SYSTEM_FALCON) /* defined in drv_config.h */
 209 +
 210 +/* lib_ifxos headers */
 211 +#include "ifx_types.h"
 212 +#include "ifxos_linux_drv.h"
 213 +#include "ifxos_copy_user_space.h"
 214 +#include "ifxos_event.h"
 215 +#include "ifxos_lock.h"
 216 +#include "ifxos_select.h"
 217 +#include "ifxos_interrupt.h"
 218 +#include <linux/gpio.h>
 219 +#include <sys1_reg.h>
 220 +#include <falcon.h>
 221 +#include <falcon_irq.h>
 222 +#include <vpe.h>
 223 +#include <sysctrl.h>
 224 +void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = (void (*)(unsigned int, int))0xbf000290;
 225 +
 226 +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
 227 +
 228 +/*#define USE_PLAIN_VOICE_FIRMWARE*/
 229 +/* board specific headers */
 230 +
 231 +/* device specific headers */
 232 +#include "drv_mps_vmmc.h"
 233 +#include "drv_mps_vmmc_dbg.h"
 234 +#include "drv_mps_vmmc_device.h"
 235 +
 236 +/* ============================= */
 237 +/* Local Macros & Definitions    */
 238 +/* ============================= */
 239 +/* Firmware watchdog timer counter address */
 240 +#define VPE1_WDOG_CTR_ADDR ((IFX_uint32_t)((IFX_uint8_t* )IFX_MPS_SRAM + 432))
 241 +
 242 +/* Firmware watchdog timeout range, values in ms */
 243 +#define VPE1_WDOG_TMOUT_MIN 20
 244 +#define VPE1_WDOG_TMOUT_MAX 5000
 245 +
 246 +/* ============================= */
 247 +/* Global variable definition    */
 248 +/* ============================= */
 249 +extern mps_comm_dev *pMPSDev;
 250 +
 251 +/* ============================= */
 252 +/* Global function declaration   */
 253 +/* ============================= */
 254 +IFX_void_t ifx_mps_release (IFX_void_t);
 255 +extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);
 256 +extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);
 257 +IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count);
 258 +extern IFXOS_event_t fw_ready_evt;
 259 +/* ============================= */
 260 +/* Local function declaration    */
 261 +/* ============================= */
 262 +static IFX_int32_t ifx_mps_fw_wdog_start_ar9(IFX_void_t);
 263 +
 264 +/* ============================= */
 265 +/* Local variable definition     */
 266 +/* ============================= */
 267 +static IFX_int32_t vpe1_started = 0;
 268 +/* VMMC watchdog timer callback */
 269 +IFX_int32_t (*ifx_wdog_callback) (IFX_uint32_t flags) = IFX_NULL;
 270 +
 271 +/* ============================= */
 272 +/* Local function definition     */
 273 +/* ============================= */
 274 +
 275 +/******************************************************************************
 276 + * AR9 Specific Routines
 277 + ******************************************************************************/
 278 +
 279 +/**
 280 + * Start AR9 EDSP firmware watchdog mechanism.
 281 + * Called after download and startup of VPE1.
 282 + *
 283 + * \param   none
 284 + * \return  0         IFX_SUCCESS
 285 + * \return  -1        IFX_ERROR
 286 + * \ingroup Internal
 287 + */
 288 +IFX_int32_t ifx_mps_fw_wdog_start_ar9()
 289 +{
 290 +   return IFX_SUCCESS;
 291 +}
 292 +
 293 +/**
 294 + * Firmware download to Voice CPU
 295 + * This function performs a firmware download to the coprocessor.
 296 + *
 297 + * \param   pMBDev    Pointer to mailbox device structure
 298 + * \param   pFWDwnld  Pointer to firmware structure
 299 + * \return  0         IFX_SUCCESS, firmware ready
 300 + * \return  -1        IFX_ERROR,   firmware not downloaded.
 301 + * \ingroup Internal
 302 + */
 303 +IFX_int32_t ifx_mps_download_firmware (mps_mbx_dev *pMBDev, mps_fw *pFWDwnld)
 304 +{
 305 +   IFX_uint32_t mem, cksum;
 306 +   IFX_uint8_t crc;
 307 +   IFX_boolean_t bMemReqNotPresent = IFX_FALSE;
 308 +
 309 +   /* VCC register */
 310 +   /* dummy accesss on GTC for GPONC-55, otherwise upper bits are random on read */
 311 +   ltq_r32 ((u32 *)((KSEG1 | 0x1DC000B0)));
 312 +   /* NTR Frequency Select 1536 kHz per default or take existing,
 313 +      NTR Output Enable and NTR8K Output Enable  */
 314 +   if ((ltq_r32 ((u32 *)(GPON_SYS_BASE + 0xBC)) & 7) == 0)
 315 +      ltq_w32_mask (0x10187, 0x183, (u32 *)(GPON_SYS_BASE + 0xBC));
 316 +   else
 317 +      ltq_w32_mask (0x10180, 0x180, (u32 *)(GPON_SYS_BASE + 0xBC));
 318 +#if 0
 319 +   /* BIU-ICU1-IM1_ISR - IM1:FSCT_CMP1=1 and FSC_ROOT=1
 320 +      (0x1f880328 = 0x00002800) */
 321 +   ltq_w32 (0x00002800, (u32 *)(GPON_ICU1_BASE + 0x30));
 322 +#endif
 323 +   /* copy FW footer from user space */
 324 +   if (IFX_NULL == IFXOS_CpyFromUser(pFW_img_data,
 325 +                           pFWDwnld->data+pFWDwnld->length/4-sizeof(*pFW_img_data)/4,
 326 +                           sizeof(*pFW_img_data)))
 327 +   {
 328 +      TRACE (MPS, DBG_LEVEL_HIGH,
 329 +                  (KERN_ERR "[%s %s %d]: copy_from_user error\r\n",
 330 +                   __FILE__, __func__, __LINE__));
 331 +      return IFX_ERROR;
 332 +   }
 333 +
 334 +   mem = pFW_img_data->mem;
 335 +
 336 +   /* memory requirement sanity check */
 337 +   if ((crc = ~((mem >> 16) + (mem >> 8) + mem)) != (mem >> 24))
 338 +   {
 339 +      TRACE (MPS, DBG_LEVEL_HIGH,
 340 +          ("[%s %s %d]: warning, image does not contain size - assuming 1MB!\n",
 341 +           __FILE__, __func__, __LINE__));
 342 +      mem = 1 * 1024 * 1024;
 343 +      bMemReqNotPresent = IFX_TRUE;
 344 +   }
 345 +   else
 346 +   {
 347 +      mem &= 0x00FFFFFF;
 348 +   }
 349 +
 350 +   /* check if FW image fits in available memory space */
 351 +   if (mem > vpe1_get_max_mem(0))
 352 +   {
 353 +      TRACE (MPS, DBG_LEVEL_HIGH,
 354 +      ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
 355 +                 __FILE__, __func__, __LINE__, mem, vpe1_get_max_mem(0)));
 356 +      return IFX_ERROR;
 357 +   }
 358 +
 359 +   /* reset the driver */
 360 +   ifx_mps_reset ();
 361 +
 362 +   /* call BSP to get cpu1 base address */
 363 +   cpu1_base_addr = (IFX_uint32_t *)vpe1_get_load_addr(0);
 364 +
 365 +   /* check if CPU1 base address is sane
 366 +      \todo: check if address is 1MB aligned,
 367 +      also make it visible in a /proc fs */
 368 +   if (!cpu1_base_addr)
 369 +   {
 370 +      TRACE (MPS, DBG_LEVEL_HIGH,
 371 +             (KERN_ERR "IFX_MPS: CPU1 base address is invalid!\r\n"));
 372 +      return IFX_ERROR;
 373 +   }
 374 +   /* further use uncached value */
 375 +   cpu1_base_addr = (IFX_uint32_t *)KSEG1ADDR(cpu1_base_addr);
 376 +
 377 +   /* free all data buffers that might be currently used by FW */
 378 +   if (IFX_NULL != ifx_mps_bufman_freeall)
 379 +   {
 380 +      ifx_mps_bufman_freeall();
 381 +   }
 382 +
 383 +   if(FW_FORMAT_NEW)
 384 +   {
 385 +      /* adjust download length */
 386 +      pFWDwnld->length -= (sizeof(*pFW_img_data)-sizeof(IFX_uint32_t));
 387 +   }
 388 +   else
 389 +   {
 390 +      pFWDwnld->length -= sizeof(IFX_uint32_t);
 391 +
 392 +      /* handle unlikely case if FW image does not contain memory requirement -
 393 +         assumed for old format only */
 394 +      if (IFX_TRUE == bMemReqNotPresent)
 395 +         pFWDwnld->length += sizeof(IFX_uint32_t);
 396 +
 397 +      /* in case of old FW format always assume that FW is encrypted;
 398 +         use compile switch USE_PLAIN_VOICE_FIRMWARE for plain FW */
 399 +#ifndef USE_PLAIN_VOICE_FIRMWARE
 400 +      pFW_img_data->enc = 1;
 401 +#else
 402 +#warning Using unencrypted firmware!
 403 +      pFW_img_data->enc = 0;
 404 +#endif /* USE_PLAIN_VOICE_FIRMWARE */
 405 +      /* initializations for the old format */
 406 +      pFW_img_data->st_addr_crc = 2*sizeof(IFX_uint32_t) +
 407 +                                  FW_AR9_OLD_FMT_XCPT_AREA_SZ;
 408 +      pFW_img_data->en_addr_crc = pFWDwnld->length;
 409 +      pFW_img_data->fw_vers = 0;
 410 +      pFW_img_data->magic = 0;
 411 +   }
 412 +
 413 +   /* copy FW image to base address of CPU1 */
 414 +   if (IFX_NULL ==
 415 +       IFXOS_CpyFromUser ((IFX_void_t *)cpu1_base_addr,
 416 +                          (IFX_void_t *)pFWDwnld->data, pFWDwnld->length))
 417 +   {
 418 +      TRACE (MPS, DBG_LEVEL_HIGH,
 419 +             (KERN_ERR "[%s %s %d]: copy_from_user error\r\n", __FILE__,
 420 +              __func__, __LINE__));
 421 +      return IFX_ERROR;
 422 +   }
 423 +
 424 +   /* process firmware decryption */
 425 +   if (pFW_img_data->enc == 1)
 426 +   {
 427 +      if(FW_FORMAT_NEW)
 428 +      {
 429 +         /* adjust decryption length (avoid decrypting CRC32 checksum) */
 430 +         pFWDwnld->length -= sizeof(IFX_uint32_t);
 431 +      }
 432 +      /* BootROM actually decrypts n+4 bytes if n bytes were passed for
 433 +         decryption. Subtract sizeof(u32) from length to avoid decryption
 434 +         of data beyond the FW image code */
 435 +      pFWDwnld->length -= sizeof(IFX_uint32_t);
 436 +      ifx_bsp_basic_mps_decrypt((unsigned int)cpu1_base_addr, pFWDwnld->length);
 437 +   }
 438 +
 439 +   /* calculate CRC32 checksum over downloaded image */
 440 +   cksum = ifx_mps_fw_crc32(cpu1_base_addr, pFW_img_data);
 441 +
 442 +   /* verify the checksum */
 443 +   if(FW_FORMAT_NEW)
 444 +   {
 445 +      if (cksum != pFW_img_data->crc32)
 446 +      {
 447 +         TRACE (MPS, DBG_LEVEL_HIGH,
 448 +                ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
 449 +                pFW_img_data->crc32, cksum));
 450 +         /*return IFX_ERROR;*/
 451 +      }
 452 +   }
 453 +   else
 454 +   {
 455 +      /* just store self-calculated checksum */
 456 +      pFW_img_data->crc32 = cksum;
 457 +   }
 458 +
 459 +   /* start VPE1 */
 460 +   ifx_mps_release ();
 461 +#if 0
 462 +   /* start FW watchdog mechanism */
 463 +   ifx_mps_fw_wdog_start_ar9();
 464 +#endif
 465 +   /* get FW version */
 466 +   return ifx_mps_get_fw_version (0);
 467 +}
 468 +
 469 +
 470 +/**
 471 + * Restart CPU1
 472 + * This function restarts CPU1 by accessing the reset request register and
 473 + * reinitializes the mailbox.
 474 + *
 475 + * \return  0        IFX_SUCCESS, successful restart
 476 + * \return  -1       IFX_ERROR, if reset failed
 477 + * \ingroup Internal
 478 + */
 479 +IFX_int32_t ifx_mps_restart (IFX_void_t)
 480 +{
 481 +   /* raise reset request for CPU1 and reset driver structures */
 482 +   ifx_mps_reset ();
 483 +   /* Disable GPTC Interrupt to CPU1 */
 484 +   ifx_mps_shutdown_gpt ();
 485 +   /* re-configure GPTC */
 486 +   ifx_mps_init_gpt ();
 487 +   /* let CPU1 run */
 488 +   ifx_mps_release ();
 489 +   /* start FW watchdog mechanism */
 490 +   ifx_mps_fw_wdog_start_ar9();
 491 +   TRACE (MPS, DBG_LEVEL_HIGH, ("IFX_MPS: Restarting firmware..."));
 492 +   return ifx_mps_get_fw_version (0);
 493 +}
 494 +
 495 +/**
 496 + * Shutdown MPS - stop VPE1
 497 + * This function stops VPE1
 498 + *
 499 + * \ingroup Internal
 500 + */
 501 +IFX_void_t ifx_mps_shutdown (IFX_void_t)
 502 +{
 503 +   if (vpe1_started)
 504 +   {
 505 +      /* stop software watchdog timer */
 506 +      vpe1_sw_wdog_stop (0);
 507 +      /* clean up the BSP callback function */
 508 +      vpe1_sw_wdog_register_reset_handler (IFX_NULL);
 509 +      /* stop VPE1 */
 510 +      vpe1_sw_stop (0);
 511 +      vpe1_started = 0;
 512 +   }
 513 +   /* free GPTC */
 514 +   ifx_mps_shutdown_gpt ();
 515 +}
 516 +
 517 +/**
 518 + * Reset CPU1
 519 + * This function causes a reset of CPU1 by clearing the CPU0 boot ready bit
 520 + * in the reset request register RCU_RST_REQ.
 521 + * It does not change the boot configuration registers for CPU0 or CPU1.
 522 + *
 523 + * \return  0        IFX_SUCCESS, cannot fail
 524 + * \ingroup Internal
 525 + */
 526 +IFX_void_t ifx_mps_reset (IFX_void_t)
 527 +{
 528 +   /* if VPE1 is already started, stop it */
 529 +   if (vpe1_started)
 530 +   {
 531 +      /* stop software watchdog timer first */
 532 +      vpe1_sw_wdog_stop (0);
 533 +      vpe1_sw_stop (0);
 534 +      vpe1_started = 0;
 535 +   }
 536 +
 537 +   /* reset driver */
 538 +   ifx_mps_reset_structures (pMPSDev);
 539 +   ifx_mps_bufman_close ();
 540 +   return;
 541 +}
 542 +
 543 +/**
 544 + * Let CPU1 run
 545 + * This function starts VPE1
 546 + *
 547 + * \return  none
 548 + * \ingroup Internal
 549 + */
 550 +IFX_void_t ifx_mps_release (IFX_void_t)
 551 +{
 552 +   IFX_int_t ret;
 553 +   IFX_int32_t RetCode = 0;
 554 +
 555 +   /* Start VPE1 */
 556 +   if (IFX_SUCCESS !=
 557 +       vpe1_sw_start ((IFX_void_t *)cpu1_base_addr, 0, 0))
 558 +   {
 559 +      TRACE (MPS, DBG_LEVEL_HIGH, (KERN_ERR "Error starting VPE1\r\n"));
 560 +      return;
 561 +   }
 562 +   vpe1_started = 1;
 563 +
 564 +   /* sleep 3 seconds until FW is ready */
 565 +   ret = IFXOS_EventWait (&fw_ready_evt, 3000, &RetCode);
 566 +   if ((ret == IFX_ERROR) && (RetCode == 1))
 567 +   {
 568 +      /* timeout */
 569 +      TRACE (MPS, DBG_LEVEL_HIGH,
 570 +             (KERN_ERR "[%s %s %d]: Timeout waiting for firmware ready.\r\n",
 571 +              __FILE__, __func__, __LINE__));
 572 +      /* recalculate and compare the firmware checksum */
 573 +      ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
 574 +      /* dump exception area on a console */
 575 +      ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);
 576 +   }
 577 +}
 578 +
 579 +/**
 580 + * WDT callback.
 581 + * This function is called by BSP (module softdog_vpe) in case if software
 582 + * watchdog timer expiration is detected by BSP.
 583 + * This function needs to be registered at BSP as WDT callback using
 584 + * vpe1_sw_wdog_register_reset_handler() API.
 585 + *
 586 + * \return  0        IFX_SUCCESS, cannot fail
 587 + * \ingroup Internal
 588 + */
 589 +IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count)
 590 +{
 591 +#ifdef DEBUG
 592 +   TRACE (MPS, DBG_LEVEL_HIGH,
 593 +          ("MPS: watchdog callback! arg=0x%08x\r\n", wdog_cleared_ok_count));
 594 +#endif /* DEBUG */
 595 +
 596 +   /* reset SmartSLIC is done by FW */
 597 +   /* recalculate and compare the firmware checksum */
 598 +   ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
 599 +
 600 +   /* dump exception area on a console */
 601 +   ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);
 602 +
 603 +   if (IFX_NULL != ifx_wdog_callback)
 604 +   {
 605 +      /* call VMMC driver */
 606 +      ifx_wdog_callback (wdog_cleared_ok_count);
 607 +   }
 608 +   else
 609 +   {
 610 +      TRACE (MPS, DBG_LEVEL_HIGH,
 611 +             (KERN_WARNING "MPS: VMMC watchdog timer callback is NULL.\r\n"));
 612 +   }
 613 +   return 0;
 614 +}
 615 +
 616 +/**
 617 + * Register WDT callback.
 618 + * This function is called by VMMC driver to register its callback in
 619 + * the MPS driver.
 620 + *
 621 + * \return  0        IFX_SUCCESS, cannot fail
 622 + * \ingroup Internal
 623 + */
 624 +IFX_int32_t
 625 +ifx_mps_register_wdog_callback (IFX_int32_t (*pfn) (IFX_uint32_t flags))
 626 +{
 627 +   ifx_wdog_callback = pfn;
 628 +   return 0;
 629 +}
 630 +
 631 +/**
 632 +   Hardware setup on FALC ON
 633 +*/
 634 +void sys_hw_setup (void)
 635 +{
 636 +   /* Set INFRAC register bit 1: clock enable of the GPE primary clock.  */
 637 +   sys_gpe_hw_activate (0);
 638 +   /* enable 1.5 V */
 639 +   ltq_w32_mask (0xf, 0x0b, (u32 *)(GPON_SYS1_BASE | 0xbc));
 640 +   /* SYS1-CLKEN:GPTC = 1 and MPS, no longer FSCT = 1 */
 641 +   sys1_hw_activate (ACTS_MPS | ACTS_GPTC);
 642 +   /* GPTC:CLC:RMC = 1 */
 643 +   ltq_w32 (0x00000100, (u32 *)(KSEG1 | 0x1E100E00));
 644 +}
 645 +
 646 +#ifndef VMMC_WITH_MPS
 647 +EXPORT_SYMBOL (ifx_mps_register_wdog_callback);
 648 +#endif /* !VMMC_WITH_MPS */
 649 +
 650 +#endif /* SYSTEM_FALCON */
 651 --- a/src/mps/drv_mps_vmmc_common.c
 652 +++ b/src/mps/drv_mps_vmmc_common.c
 653 @@ -66,6 +66,10 @@ static void inline bsp_mask_and_ack_irq(
 654  #  include <asm/ifx/ifx_regs.h>
 655  #  include <asm/ifx/ifx_gptu.h>
 656  #endif
 657 +#if defined(SYSTEM_FALCON)
 658 +#include <sys1_reg.h>
 659 +#include <sysctrl.h>
 660 +#endif
 661
 662  #include "drv_mps_vmmc.h"
 663  #include "drv_mps_vmmc_dbg.h"
 664 @@ -1156,7 +1160,12 @@ IFX_uint32_t ifx_mps_init_structures (mp
 665        mailbox, * upstream and downstream direction. */
 666     memset (
 667         /* avoid to overwrite CPU boot registers */
 668 +#if defined(SYSTEM_FALCON)
 669 +          (IFX_void_t *) MBX_Memory +
 670 +           2 * sizeof (mps_boot_cfg_reg),
 671 +#else
 672            (IFX_void_t *) MBX_Memory,
 673 +#endif
 674             0,
 675             sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
 676     MBX_Memory->MBX_UPSTR_CMD_BASE =
 677 @@ -2651,7 +2660,6 @@ IFX_void_t ifx_mps_enable_mailbox_int ()
 678  #endif
 679
 680     *IFX_MPS_AD0ENR = Ad0Reg.val;
 681 -
 682  }
 683
 684  /**
 685 @@ -2669,6 +2677,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
 686     Ad0Reg.fld.cu_mbx = 0;
 687     Ad0Reg.fld.du_mbx = 0;
 688     *IFX_MPS_AD0ENR = Ad0Reg.val;
 689 +
 690  }
 691
 692  /**
 693 @@ -2766,11 +2775,13 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
 694     /* handle only enabled interrupts */
 695     MPS_Ad0StatusReg.val &= *IFX_MPS_AD0ENR;
 696
 697 +#if !defined(SYSTEM_FALCON)
 698  #ifdef LINUX_2_6
 699     bsp_mask_and_ack_irq (irq);
 700  #else /* */
 701     mask_and_ack_danube_irq (irq);
 702  #endif /* */
 703 +#endif /* !defined(SYSTEM_FALCON) */
 704     /* FW is up and ready to process commands */
 705     if (MPS_Ad0StatusReg.fld.dl_end)
 706     {
 707 @@ -2919,11 +2930,13 @@ irqreturn_t ifx_mps_ad1_irq (IFX_int32_t
 708     /* handle only enabled interrupts */
 709     MPS_Ad1StatusReg.val &= *IFX_MPS_AD1ENR;
 710
 711 +#if !defined(SYSTEM_FALCON)
 712  #ifdef LINUX_2_6
 713     bsp_mask_and_ack_irq (irq);
 714  #else /* */
 715     mask_and_ack_danube_irq (irq);
 716  #endif /* */
 717 +#endif /* !defined(SYSTEM_FALCON) */
 718     pMPSDev->event.MPS_Ad1Reg.val = MPS_Ad1StatusReg.val;
 719
 720     /* use callback function or queue wake up to notify about data reception */
 721 @@ -2977,11 +2990,13 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
 722     IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
 723     /* handle only enabled interrupts */
 724     MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
 725 +#if !defined(SYSTEM_FALCON)
 726  #ifdef LINUX_2_6
 727     bsp_mask_and_ack_irq (irq);
 728  #else /* */
 729     mask_and_ack_danube_irq (irq);
 730  #endif /* */
 731 +#endif /* !defined(SYSTEM_FALCON) */
 732
 733     pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
 734  #ifdef PRINT_ON_ERR_INTERRUPT
 735 @@ -3126,6 +3141,7 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
 736   */
 737  IFX_return_t ifx_mps_init_gpt ()
 738  {
 739 +#if !defined(SYSTEM_FALCON)
 740     unsigned long flags;
 741     IFX_uint32_t timer_flags, timer, loops = 0;
 742     IFX_ulong_t count;
 743 @@ -3134,7 +3150,11 @@ IFX_return_t ifx_mps_init_gpt ()
 744  #else /* Danube */
 745     timer = TIMER1B;
 746  #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
 747 +#endif
 748
 749 +#if defined(SYSTEM_FALCON)
 750 +   sys_hw_setup ();
 751 +#else
 752     /* calibration loop - required to syncronize GPTC interrupt with falling
 753        edge of FSC clock */
 754     timer_flags =
 755 @@ -3179,7 +3199,7 @@ Probably already in use.\r\n", __FILE__,
 756  #endif /* DEBUG */
 757
 758     IFXOS_UNLOCKINT (flags);
 759 -
 760 +#endif
 761     return IFX_SUCCESS;
 762  }
 763
 764 @@ -3194,6 +3214,9 @@ Probably already in use.\r\n", __FILE__,
 765   */
 766  IFX_void_t ifx_mps_shutdown_gpt (IFX_void_t)
 767  {
 768 +#if defined(SYSTEM_FALCON)
 769 +   sys1_hw_deactivate (ACTS_MPS);
 770 +#else
 771     IFX_uint32_t timer;
 772  #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 773     timer = TIMER1A;
 774 @@ -3202,6 +3225,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi
 775  #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
 776
 777     ifx_gptu_timer_free (timer);
 778 +#endif
 779  }
 780
 781  /**
 782 --- a/src/mps/drv_mps_vmmc_device.h
 783 +++ b/src/mps/drv_mps_vmmc_device.h
 784 @@ -22,7 +22,12 @@
 785  #  include <lantiq_soc.h>
 786  #  include <gpio.h>
 787  #define IFXMIPS_MPS_SRAM               ((u32 *)(KSEG1 + 0x1F200000))
 788 +#if defined(SYSTEM_FALCON)
 789 +#define IFXMIPS_MPS_BASE_ADDR          (KSEG1 + 0x1D004000)
 790 +#else
 791  #define IFXMIPS_MPS_BASE_ADDR          (KSEG1 + 0x1F107000)
 792 +#endif
 793 +
 794  #define IFXMIPS_MPS_CHIPID             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
 795  #define IFXMIPS_MPS_VC0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
 796  #define IFXMIPS_MPS_RVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
 797 @@ -73,10 +78,11 @@
 798  /* MPS Common defines            */
 799  /* ============================= */
 800
 801 -#define MPS_BASEADDRESS 0xBF107000
 802 -#define MPS_RAD0SR      MPS_BASEADDRESS + 0x0004
 803 -
 804 +#if defined(SYSTEM_FALCON)
 805 +#define MBX_BASEADDRESS 0xBF200040
 806 +#else
 807  #define MBX_BASEADDRESS 0xBF200000
 808 +#endif
 809  #define VCPU_BASEADDRESS 0xBF208000     /* 0xBF108000 */
 810  /*---------------------------------------------------------------------------*/
 811  #if !defined(CONFIG_LANTIQ)
 812 @@ -118,7 +124,6 @@
 813  /*---------------------------------------------------------------------------*/
 814
 815  #ifdef CONFIG_MPS_EVENT_MBX
 816 -
 817  #define MBX_CMD_FIFO_SIZE  64 /**< Size of command FIFO in bytes */
 818  #define MBX_DATA_UPSTRM_FIFO_SIZE 64
 819  #define MBX_DATA_DNSTRM_FIFO_SIZE 128
 820 @@ -294,6 +299,10 @@ typedef struct
 821  #ifdef CONFIG_MPS_EVENT_MBX
 822  typedef struct
 823  {
 824 +#if defined(SYSTEM_FALCON)
 825 +   mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
 826 +   mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
 827 +#endif
 828     volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE;  /**< Upstream Command FIFO Base Address */
 829     volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE;   /**< Upstream Command FIFO size in byte */
 830     volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE;  /**< Downstream Command FIFO Base Address */
 831 @@ -317,13 +326,19 @@ typedef struct
 832     volatile IFX_uint32_t MBX_UPSTR_EVENT_WRITE; /**< Upstream Event FIFO Write Index */
 833     volatile IFX_uint32_t MBX_EVENT[MBX_EVENT_DATA_WORDS];
 834     volatile IFX_uint32_t reserved[4];
 835 +#if !defined(SYSTEM_FALCON)
 836     mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
 837     mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
 838 +#endif
 839  } mps_mbx_reg;
 840
 841  #else /* */
 842  typedef struct
 843  {
 844 +#if defined(SYSTEM_FALCON)
 845 +   mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
 846 +   mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
 847 +#endif
 848     volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE;  /**< Upstream Command FIFO Base Address */
 849     volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE;   /**< Upstream Command FIFO size in byte */
 850     volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE;  /**< Downstream Command FIFO Base Address */
 851 @@ -341,8 +356,10 @@ typedef struct
 852     volatile IFX_uint32_t MBX_DNSTR_DATA_READ;   /**< Downstream Data FIFO Read Index */
 853     volatile IFX_uint32_t MBX_DNSTR_DATA_WRITE;  /**< Downstream Data FIFO Write Index */
 854     volatile IFX_uint32_t MBX_DATA[MBX_DATA_WORDS];
 855 +#if !defined(SYSTEM_FALCON)
 856     mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
 857     mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
 858 +#endif
 859  } mps_mbx_reg;
 860  #endif /* CONFIG_MPS_EVENT_MBX */
 861
 862 --- a/src/drv_api.h
 863 +++ b/src/drv_api.h
 864 @@ -183,7 +183,7 @@
 865  #endif
 866
 867  /* TAPI FXS Phone Detection feature is not available for Danube platform */
 868 -#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9))
 869 +#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON))
 870  #define VMMC_CFG_ADD_FEAT_PHONE_DETECTION VMMC_FEAT_PHONE_DETECTION
 871  #else
 872  #define VMMC_CFG_ADD_FEAT_PHONE_DETECTION 0
 873 --- a/src/drv_vmmc_alm.c
 874 +++ b/src/drv_vmmc_alm.c
 875 @@ -800,7 +800,7 @@ IFX_void_t VMMC_ALM_Free_Ch_Structures (
 876  }
 877
 878
 879 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 880 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 881  /**
 882     Check whether SmartSLIC is connected
 883
 884 @@ -836,7 +836,7 @@ IFX_boolean_t VMMC_ALM_SmartSLIC_IsConne
 885  #endif /*SYSTEM_AR9 || SYSTEM_VR9*/
 886
 887
 888 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 889 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 890  /**
 891     Read the number of channels on the SmartSLIC.
 892
 893 @@ -1876,7 +1876,7 @@ IFX_int32_t VMMC_TAPI_LL_ALM_VMMC_Test_L
 894        /* write updated message contents */
 895        ret = CmdWrite (pDev, (IFX_uint32_t *)((IFX_void_t *)&debugCfg),
 896                        DCCTL_CMD_LEN);
 897 -#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 898 +#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 899        IFX_uint32_t dcctrlLoop[2];
 900        IFX_uint32_t ch = (IFX_uint32_t)(pCh->nChannel - 1);
 901
 902 --- a/src/drv_vmmc_alm.h
 903 +++ b/src/drv_vmmc_alm.h
 904 @@ -65,7 +65,7 @@ extern IFX_void_t irq_VMMC_ALM_LineDisab
 905  extern IFX_void_t VMMC_ALM_CorrectLinemodeCache (VMMC_CHANNEL *pCh,
 906                                                   IFX_uint16_t lm);
 907
 908 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 909 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 910  extern IFX_boolean_t VMMC_ALM_SmartSLIC_IsConnected (
 911                          VMMC_DEVICE *pDev);
 912
 913 --- a/src/drv_vmmc_init.c
 914 +++ b/src/drv_vmmc_init.c
 915 @@ -52,15 +52,6 @@
 916  #include "ifx_pmu.h"
 917  #endif /* PMU_SUPPORTED */
 918
 919 -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 920 -#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
 921 -#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
 922 -#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
 923 -#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
 924 -#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
 925 -#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
 926 -#endif
 927 -
 928  /* ============================= */
 929  /* Local Macros & Definitions    */
 930  /* ============================= */
 931 @@ -820,7 +811,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(
 932                                             MIN_FW_HOTFIXSTEP};
 933     IFX_uint8_t          tmp1, tmp2;
 934     IFX_TAPI_RESOURCE    nResource;
 935 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 936 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 937     IFX_uint8_t          nChannels, nFXOChannels;
 938  #endif /*SYSTEM_AR9 || SYSTEM_VR9*/
 939     IFX_int32_t          ret = VMMC_statusOk;
 940 @@ -874,7 +865,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(
 941     pDev->bSmartSlic = IFX_FALSE;
 942     pDev->bSlicSupportsIdleMode = IFX_FALSE;
 943
 944 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 945 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 946     if (VMMC_SUCCESS(ret))
 947     {
 948        /* Reduce the number of ALM channels in the capabilities if the SLIC
 949 --- a/src/drv_vmmc_ioctl.c
 950 +++ b/src/drv_vmmc_ioctl.c
 951 @@ -273,7 +273,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP
 952        case FIO_GET_VERS:
 953        {
 954           VMMC_IO_VERSION *pVers;
 955 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 956 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 957           VMMC_SDD_REVISION_READ_t *pSDDVersCmd = IFX_NULL;
 958  #endif /*SYSTEM_AR9 || SYSTEM_VR9*/
 959           SYS_VER_t *pCmd;
 960 @@ -322,7 +322,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP
 961              pVers->nTapiVers   = 3;
 962              pVers->nDrvVers    = MAJORSTEP << 24 | MINORSTEP << 16 |
 963                                   VERSIONSTEP << 8 | VERS_TYPE;
 964 -#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 965 +#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
 966              /* in case of SmartSLIC based systems, we can give some more
 967                 versions.*/
 968              if (VMMC_ALM_SmartSLIC_IsConnected(pDev))