1 --- a/arch/mips/ralink/common/intc.c
2 +++ b/arch/mips/ralink/common/intc.c
3 @@ -44,23 +44,25 @@ static inline u32 ramips_intc_rr(unsigne
4 return __raw_readl(ramips_intc_base + reg);
7 -static void ramips_intc_irq_unmask(unsigned int irq)
8 +static void ramips_intc_irq_unmask(struct irq_data *d)
10 - irq -= ramips_intc_irq_base;
11 + unsigned int irq = d->irq - ramips_intc_irq_base;
13 ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
16 -static void ramips_intc_irq_mask(unsigned int irq)
17 +static void ramips_intc_irq_mask(struct irq_data *d)
19 - irq -= ramips_intc_irq_base;
20 + unsigned int irq = d->irq - ramips_intc_irq_base;
22 ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
25 static struct irq_chip ramips_intc_irq_chip = {
27 - .unmask = ramips_intc_irq_unmask,
28 - .mask = ramips_intc_irq_mask,
29 - .mask_ack = ramips_intc_irq_mask,
30 + .irq_unmask = ramips_intc_irq_unmask,
31 + .irq_mask = ramips_intc_irq_mask,
32 + .irq_mask_ack = ramips_intc_irq_mask,
35 static struct irqaction ramips_intc_irqaction = {
36 @@ -83,10 +85,9 @@ void __init ramips_intc_irq_init(unsigne
37 ramips_intc_wr(0, INTC_REG_TYPE);
39 for (i = ramips_intc_irq_base;
40 - i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) {
41 - set_irq_chip_and_handler(i, &ramips_intc_irq_chip,
42 + i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++)
43 + irq_set_chip_and_handler(i, &ramips_intc_irq_chip,
47 setup_irq(irq, &ramips_intc_irqaction);
48 ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);