[atheros] remove the clz function, use fls instead
[openwrt.git] / target / linux / brcm47xx / patches-2.6.23 / 220-bcm5354.patch
1 Index: linux-2.6.23.16/drivers/ssb/driver_chipcommon.c
2 ===================================================================
3 --- linux-2.6.23.16.orig/drivers/ssb/driver_chipcommon.c 2008-02-19 13:46:08.000000000 +0100
4 +++ linux-2.6.23.16/drivers/ssb/driver_chipcommon.c 2008-02-19 13:46:17.000000000 +0100
5 @@ -270,6 +270,8 @@ void ssb_chipco_resume(struct ssb_chipco
6 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
7 u32 *plltype, u32 *n, u32 *m)
8 {
9 + if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
10 + return;
11 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
12 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
13 switch (*plltype) {
14 @@ -293,6 +295,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
15 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
16 u32 *plltype, u32 *n, u32 *m)
17 {
18 + if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
19 + return;
20 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
21 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
22 switch (*plltype) {
23 Index: linux-2.6.23.16/drivers/ssb/driver_mipscore.c
24 ===================================================================
25 --- linux-2.6.23.16.orig/drivers/ssb/driver_mipscore.c 2008-02-19 13:46:08.000000000 +0100
26 +++ linux-2.6.23.16/drivers/ssb/driver_mipscore.c 2008-02-19 13:46:17.000000000 +0100
27 @@ -160,6 +160,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
28
29 if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
30 rate = 200000000;
31 + } else if (bus->chip_id == 0x5354) {
32 + rate = 240000000;
33 } else {
34 rate = ssb_calc_clock_rate(pll_type, n, m);
35 }
36 Index: linux-2.6.23.16/drivers/ssb/main.c
37 ===================================================================
38 --- linux-2.6.23.16.orig/drivers/ssb/main.c 2008-02-19 13:46:08.000000000 +0100
39 +++ linux-2.6.23.16/drivers/ssb/main.c 2008-02-19 13:46:17.000000000 +0100
40 @@ -862,6 +862,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
41
42 if (bus->chip_id == 0x5365) {
43 rate = 100000000;
44 + } else if (bus->chip_id == 0x5354) {
45 + rate = 120000000;
46 } else {
47 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
48 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
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