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[openwrt.git] / target / linux / rdc / files / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.18"
54 #define DRV_RELDATE "13Jun2008"
55
56 /* define bits of a debug mask */
57 #define DBG_PHY (1<< 0) /*!< show PHY read/write */
58 #define DBG_FREE_BUFS (1<< 1) /*!< show calls to r6040_free_*bufs */
59 #define DBG_RING (1<< 2) /*!< debug init./freeing of descr rings */
60 #define DBG_RX_BUF (1<< 3) /*!< show alloc. of new rx buf (in IRQ context !) */
61 #define DBG_TX_BUF (1<< 4) /*!< show arrival of new tx buf */
62 #define DBG_RX_IRQ (1<< 5) /*!< show RX IRQ handling */
63 #define DBG_TX_IRQ (1<< 6) /*!< debug TX done IRQ */
64 #define DBG_RX_DESCR (1<< 7) /*!< debug rx descr to be processed */
65 #define DBG_RX_DATA (1<< 8) /*!< show some user data of incoming packet */
66 #define DBG_EXIT (1<< 9) /*!< show exit code calls */
67 #define DBG_INIT (1<<10) /*!< show init. code calls */
68 #define DBG_TX_RING_DUMP (1<<11) /*!< dump the tx ring after creation */
69 #define DBG_RX_RING_DUMP (1<<12) /*!< dump the rx ring after creation */
70 #define DBG_TX_DESCR (1<<13) /*!< dump the setting of a descr for tx */
71 #define DBG_TX_DATA (1<<14) /*!< dump some tx data */
72 #define DBG_IRQ (1<<15) /*!< print inside the irq handler */
73 #define DBG_POLL (1<<16) /*!< dump info on poll procedure */
74 #define DBG_MAC_ADDR (1<<17) /*!< debug mac address setting */
75 #define DBG_OPEN (1<<18) /*!< debug open proc. */
76
77 static int debug = 0;
78 module_param(debug, int, 0);
79 MODULE_PARM_DESC(debug, "debug mask (-1 for all)");
80
81 /* define wcd hich debugs are left in the code during compilation */
82 #define DEBUG (-1) /* all debugs */
83
84 #define dbg(l, f, ...) \
85 do { \
86 if ((DEBUG & l) && (debug & l)) { \
87 printk(KERN_INFO DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__); \
88 } \
89 } while (0)
90
91 #define err(f, ...) printk(KERN_WARNING DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__)
92
93 /* PHY CHIP Address */
94 #define PHY1_ADDR 1 /* For MAC1 */
95 #define PHY2_ADDR 2 /* For MAC2 */
96 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
97 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
98
99 /* Time in jiffies before concluding the transmitter is hung. */
100 #define TX_TIMEOUT (6000 * HZ / 1000)
101
102 /* RDC MAC I/O Size */
103 #define R6040_IO_SIZE 256
104
105 /* MAX RDC MAC */
106 #define MAX_MAC 2
107
108 /* MAC registers */
109 #define MCR0 0x00 /* Control register 0 */
110 #define MCR1 0x04 /* Control register 1 */
111 #define MAC_RST 0x0001 /* Reset the MAC */
112 #define MBCR 0x08 /* Bus control */
113 #define MT_ICR 0x0C /* TX interrupt control */
114 #define MR_ICR 0x10 /* RX interrupt control */
115 #define MTPR 0x14 /* TX poll command register */
116 #define MR_BSR 0x18 /* RX buffer size */
117 #define MR_DCR 0x1A /* RX descriptor control */
118 #define MLSR 0x1C /* Last status */
119 #define MMDIO 0x20 /* MDIO control register */
120 #define MDIO_WRITE 0x4000 /* MDIO write */
121 #define MDIO_READ 0x2000 /* MDIO read */
122 #define MMRD 0x24 /* MDIO read data register */
123 #define MMWD 0x28 /* MDIO write data register */
124 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
125 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
126 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
127 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
128 #define MISR 0x3C /* Status register */
129 #define MIER 0x40 /* INT enable register */
130 #define MSK_INT 0x0000 /* Mask off interrupts */
131 #define RX_FINISH 0x0001 /* rx finished irq */
132 #define RX_NO_DESC 0x0002 /* rx no descr. avail. irq */
133 #define RX_FIFO_FULL 0x0004 /* rx fifo full irq */
134 #define RX_EARLY 0x0008 /* rx early irq */
135 #define TX_FINISH 0x0010 /* tx finished irq */
136 #define TX_EARLY 0x0080 /* tx early irq */
137 #define EVENT_OVRFL 0x0100 /* event counter overflow irq */
138 #define LINK_CHANGED 0x0200 /* PHY link changed irq */
139
140 #define ME_CISR 0x44 /* Event counter INT status */
141 #define ME_CIER 0x48 /* Event counter INT enable */
142 #define MR_CNT 0x50 /* Successfully received packet counter */
143 #define ME_CNT0 0x52 /* Event counter 0 */
144 #define ME_CNT1 0x54 /* Event counter 1 */
145 #define ME_CNT2 0x56 /* Event counter 2 */
146 #define ME_CNT3 0x58 /* Event counter 3 */
147 #define MT_CNT 0x5A /* Successfully transmit packet counter */
148 #define ME_CNT4 0x5C /* Event counter 4 */
149 #define MP_CNT 0x5E /* Pause frame counter register */
150 #define MAR0 0x60 /* Hash table 0 */
151 #define MAR1 0x62 /* Hash table 1 */
152 #define MAR2 0x64 /* Hash table 2 */
153 #define MAR3 0x66 /* Hash table 3 */
154 #define MID_0L 0x68 /* Multicast address MID0 Low */
155 #define MID_0M 0x6A /* Multicast address MID0 Medium */
156 #define MID_0H 0x6C /* Multicast address MID0 High */
157 #define MID_1L 0x70 /* MID1 Low */
158 #define MID_1M 0x72 /* MID1 Medium */
159 #define MID_1H 0x74 /* MID1 High */
160 #define MID_2L 0x78 /* MID2 Low */
161 #define MID_2M 0x7A /* MID2 Medium */
162 #define MID_2H 0x7C /* MID2 High */
163 #define MID_3L 0x80 /* MID3 Low */
164 #define MID_3M 0x82 /* MID3 Medium */
165 #define MID_3H 0x84 /* MID3 High */
166 #define PHY_CC 0x88 /* PHY status change configuration register */
167 #define PHY_ST 0x8A /* PHY status register */
168 #define MAC_SM 0xAC /* MAC status machine */
169 #define MAC_ID 0xBE /* Identifier register */
170
171 #define TX_DCNT 0x80 /* TX descriptor count */
172 #define RX_DCNT 0x80 /* RX descriptor count */
173 #define MAX_BUF_SIZE 0x600
174 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
175 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
176 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register:
177 - wait 1 host clock until SDRAM bus request
178 becomes high priority
179 - RX FIFO: 32 byte
180 - TX FIFO: 64 byte
181 - FIFO transfer length: 16 byte */
182 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
183
184 /* PHY settings */
185 #define ICPLUS_PHY_ID 0x0243
186
187 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
188 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
189 "Florian Fainelli <florian@openwrt.org>");
190 MODULE_LICENSE("GPL");
191 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
192
193 /*! which rx interrupts do we allow */
194 #define RX_INTS (RX_FIFO_FULL|RX_NO_DESC|RX_FINISH)
195 /*! which tx interrupts do we allow */
196 #define TX_INTS (TX_FINISH)
197 #define INT_MASK (RX_INTS | TX_INTS)
198
199 struct r6040_descriptor {
200 u16 status, len; /* 0-3 */
201 __le32 buf; /* 4-7 */
202 __le32 ndesc; /* 8-B */
203 u32 rev1; /* C-F */
204 char *vbufp; /* 10-13 */
205 struct r6040_descriptor *vndescp; /* 14-17 */
206 struct sk_buff *skb_ptr; /* 18-1B */
207 u32 rev2; /* 1C-1F */
208 } __attribute__((aligned(32)));
209
210 struct r6040_private {
211 spinlock_t lock; /* driver lock */
212 struct timer_list timer;
213 struct pci_dev *pdev;
214 struct r6040_descriptor *rx_insert_ptr;
215 struct r6040_descriptor *rx_remove_ptr;
216 struct r6040_descriptor *tx_insert_ptr;
217 struct r6040_descriptor *tx_remove_ptr;
218 struct r6040_descriptor *rx_ring;
219 struct r6040_descriptor *tx_ring;
220 dma_addr_t rx_ring_dma;
221 dma_addr_t tx_ring_dma;
222 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
223 u16 mcr0, mcr1;
224 u16 switch_sig;
225 struct net_device *dev;
226 struct mii_if_info mii_if;
227 struct napi_struct napi;
228 void __iomem *base;
229 };
230
231 struct net_device *parent_dev;
232 static char *parent;
233 module_param(parent, charp, 0444);
234 MODULE_PARM_DESC(parent, "Parent network device name to get the MAC address from");
235
236 static char version[] __devinitdata = KERN_INFO DRV_NAME
237 ": RDC R6040 NAPI net driver,"
238 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
239
240 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
241
242 /* forward declarations */
243 void r6040_multicast_list(struct net_device *dev);
244
245 /* jal2: comment out to get more symbols for debugging */
246 //#define STATIC static
247 #define STATIC
248
249 #if DEBUG
250 /*! hexdump an memory area into a string. delim is taken as the delimiter between two bytes.
251 It is omitted if delim == '\0' */
252 STATIC char *hex2str(void *addr, char *buf, int nr_bytes, int delim)
253 {
254 unsigned char *dst = addr;
255 char *outb = buf;
256
257 #define BIN2HEXDIGIT(x) ((x) < 10 ? '0'+(x) : 'A'-10+(x))
258
259 while (nr_bytes > 0) {
260 *outb++ = BIN2HEXDIGIT(*dst>>4);
261 *outb++ = BIN2HEXDIGIT(*dst&0xf);
262 if (delim)
263 *outb++ = delim;
264 nr_bytes--;
265 dst++;
266 }
267
268 if (delim)
269 dst--;
270 *dst = '\0';
271 return buf;
272 }
273
274 #endif /* #if DEBUG */
275
276 /* Read a word data from PHY Chip */
277 STATIC int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
278 {
279 int limit = 2048;
280 u16 cmd;
281 int rc;
282
283 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
284 /* Wait for the read bit to be cleared */
285 while (limit--) {
286 cmd = ioread16(ioaddr + MMDIO);
287 if (cmd & MDIO_READ)
288 break;
289 }
290
291 if (limit <= 0)
292 err("phy addr x%x reg x%x timed out\n",
293 phy_addr, reg);
294
295 rc=ioread16(ioaddr + MMRD);
296
297 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, rc);
298 return rc;
299 }
300
301 /* Write a word data from PHY Chip */
302 STATIC void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
303 {
304 int limit = 2048;
305 u16 cmd;
306
307 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, val);
308
309 iowrite16(val, ioaddr + MMWD);
310 /* Write the command to the MDIO bus */
311 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
312 /* Wait for the write bit to be cleared */
313 while (limit--) {
314 cmd = ioread16(ioaddr + MMDIO);
315 if (cmd & MDIO_WRITE)
316 break;
317 }
318 if (limit <= 0)
319 err("phy addr x%x reg x%x val x%x timed out\n",
320 phy_addr, reg, val);
321 }
322
323 STATIC int mdio_read(struct net_device *dev, int mii_id, int reg)
324 {
325 struct r6040_private *lp = netdev_priv(dev);
326 void __iomem *ioaddr = lp->base;
327
328 return (phy_read(ioaddr, lp->phy_addr, reg));
329 }
330
331 STATIC void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
332 {
333 struct r6040_private *lp = netdev_priv(dev);
334 void __iomem *ioaddr = lp->base;
335
336 phy_write(ioaddr, lp->phy_addr, reg, val);
337 }
338
339 void r6040_free_txbufs(struct net_device *dev)
340 {
341 struct r6040_private *lp = netdev_priv(dev);
342 int i;
343
344 dbg(DBG_FREE_BUFS, "ENTER\n");
345 for (i = 0; i < TX_DCNT; i++) {
346 if (lp->tx_insert_ptr->skb_ptr) {
347 pci_unmap_single(lp->pdev,
348 le32_to_cpu(lp->tx_insert_ptr->buf),
349 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
350 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
351 lp->rx_insert_ptr->skb_ptr = NULL;
352 }
353 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
354 }
355 dbg(DBG_FREE_BUFS, "EXIT\n");
356 }
357
358 void r6040_free_rxbufs(struct net_device *dev)
359 {
360 struct r6040_private *lp = netdev_priv(dev);
361 int i;
362
363 dbg(DBG_FREE_BUFS, "ENTER\n");
364 for (i = 0; i < RX_DCNT; i++) {
365 if (lp->rx_insert_ptr->skb_ptr) {
366 pci_unmap_single(lp->pdev,
367 le32_to_cpu(lp->rx_insert_ptr->buf),
368 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
369 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
370 lp->rx_insert_ptr->skb_ptr = NULL;
371 }
372 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
373 }
374 dbg(DBG_FREE_BUFS, "EXIT\n");
375
376 }
377
378 void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
379 dma_addr_t desc_dma, int size)
380 {
381 struct r6040_descriptor *desc = desc_ring;
382 dma_addr_t mapping = desc_dma;
383
384 dbg(DBG_RING, "desc_ring %p desc_dma %08x size x%x\n",
385 desc_ring, desc_dma, size);
386
387 while (size-- > 0) {
388 mapping += sizeof(*desc);
389 desc->ndesc = cpu_to_le32(mapping);
390 desc->vndescp = desc + 1;
391 desc++;
392 }
393 desc--;
394 desc->ndesc = cpu_to_le32(desc_dma);
395 desc->vndescp = desc_ring;
396 }
397
398 /* Allocate skb buffer for rx descriptor */
399 STATIC void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
400 {
401 struct r6040_descriptor *descptr;
402
403 dbg(DBG_RX_BUF, "rx_insert %p rx_free_desc x%x dev %p\n",
404 lp->rx_insert_ptr, lp->rx_free_desc, dev);
405
406 descptr = lp->rx_insert_ptr;
407 while (lp->rx_free_desc < RX_DCNT) {
408 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
409
410 dbg(DBG_RX_BUF, "alloc'ed skb %p for rx descptr %p\n",
411 descptr->skb_ptr, descptr);
412
413 if (!descptr->skb_ptr)
414 break;
415 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
416 descptr->skb_ptr->data,
417 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
418 descptr->status = 0x8000;
419 /* debug before descptr goes to next ! */
420 dbg(DBG_RX_BUF, "descptr %p skb->data %p buf %08x rx_free_desc x%x\n",
421 descptr, descptr->skb_ptr->data, descptr->buf, lp->rx_free_desc);
422 descptr = descptr->vndescp;
423 lp->rx_free_desc++;
424 }
425 lp->rx_insert_ptr = descptr;
426 }
427
428 #if (DEBUG & DBG_TX_RING_DUMP)
429 /*! dump the tx ring to syslog */
430 STATIC void
431 dump_tx_ring(struct r6040_private *lp)
432 {
433 int i;
434 struct r6040_descriptor *ptr;
435
436 printk(KERN_INFO "%s: nr_desc x%x tx_ring %p tx_ring_dma %08x "
437 "tx_insert %p tx_remove %p\n",
438 DRV_NAME, TX_DCNT, lp->tx_ring, lp->tx_ring_dma,
439 lp->tx_insert_ptr, lp->tx_remove_ptr);
440
441 if (lp->tx_ring) {
442 for(i=0, ptr=lp->tx_ring; i < TX_DCNT; i++, ptr++) {
443 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
444 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
445 DRV_NAME, i, ptr->status, ptr->len,
446 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
447 }
448 }
449 }
450 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
451
452 void r6040_alloc_txbufs(struct net_device *dev)
453 {
454 struct r6040_private *lp = netdev_priv(dev);
455
456 lp->tx_free_desc = TX_DCNT;
457
458 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
459 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
460
461 #if (DEBUG & DBG_TX_RING_DUMP)
462 if (debug & DBG_TX_RING_DUMP) {
463 dump_tx_ring(lp);
464 }
465 #endif
466 }
467
468 #if (DEBUG & DBG_RX_RING_DUMP)
469 /*! dump the rx ring to syslog */
470 STATIC void
471 dump_rx_ring(struct r6040_private *lp)
472 {
473 int i;
474 struct r6040_descriptor *ptr;
475
476 printk(KERN_INFO "%s: nr_desc x%x rx_ring %p rx_ring_dma %08x "
477 "rx_insert %p rx_remove %p\n",
478 DRV_NAME, RX_DCNT, lp->rx_ring, lp->rx_ring_dma,
479 lp->rx_insert_ptr, lp->rx_remove_ptr);
480
481 if (lp->rx_ring) {
482 for(i=0, ptr=lp->rx_ring; i < RX_DCNT; i++, ptr++) {
483 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
484 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
485 DRV_NAME, i, ptr->status, ptr->len,
486 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
487 }
488 }
489 }
490 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
491
492 void r6040_alloc_rxbufs(struct net_device *dev)
493 {
494 struct r6040_private *lp = netdev_priv(dev);
495
496 lp->rx_free_desc = 0;
497
498 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
499 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
500
501 rx_buf_alloc(lp, dev);
502
503 #if (DEBUG & DBG_RX_RING_DUMP)
504 if (debug & DBG_RX_RING_DUMP) {
505 dump_rx_ring(lp);
506 }
507 #endif
508 }
509
510 /*! reset MAC and set all registers */
511 void r6040_init_mac_regs(struct r6040_private *lp)
512 {
513 void __iomem *ioaddr = lp->base;
514 int limit;
515 char obuf[3*ETH_ALEN] __attribute__ ((unused));
516
517 /* Mask Off Interrupt */
518 iowrite16(MSK_INT, ioaddr + MIER);
519
520 /* reset MAC */
521 iowrite16(MAC_RST, ioaddr + MCR1);
522 udelay(100);
523 limit=2048;
524 while ((ioread16(ioaddr + MCR1) & MAC_RST) && limit-- > 0);
525
526 /* Reset internal state machine */
527 iowrite16(2, ioaddr + MAC_SM);
528 iowrite16(0, ioaddr + MAC_SM);
529 udelay(5000);
530
531 /* Restore MAC Addresses */
532 r6040_multicast_list(lp->dev);
533
534 /* TODO: restore multcast and hash table */
535
536 /* MAC Bus Control Register */
537 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
538
539 /* Buffer Size Register */
540 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
541
542 /* write tx ring start address */
543 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
544 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
545
546 /* write rx ring start address */
547 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
548 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
549
550 /* set interrupt waiting time and packet numbers */
551 iowrite16(0x0F06, ioaddr + MT_ICR);
552 iowrite16(0x0F06, ioaddr + MR_ICR);
553
554 /* enable interrupts */
555 iowrite16(INT_MASK, ioaddr + MIER);
556
557 /* enable tx and rx */
558 iowrite16(lp->mcr0 | 0x0002, ioaddr);
559
560 /* let TX poll the descriptors - we may got called by r6040_tx_timeout which has left
561 some unsent tx buffers */
562 iowrite16(0x01, ioaddr + MTPR);
563 }
564
565 void r6040_tx_timeout(struct net_device *dev)
566 {
567 struct r6040_private *priv = netdev_priv(dev);
568 void __iomem *ioaddr = priv->base;
569
570 /* we read MISR, which clears on read (i.e. we may loose an RX interupt,
571 but this is an error anyhow ... */
572 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
573 "status %4.4x, PHY status %4.4x\n",
574 dev->name, ioread16(ioaddr + MIER),
575 ioread16(ioaddr + MISR),
576 mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
577
578 dev->stats.tx_errors++;
579
580 /* Reset MAC and re-init all registers */
581 r6040_init_mac_regs(priv);
582 }
583
584 struct net_device_stats *r6040_get_stats(struct net_device *dev)
585 {
586 struct r6040_private *priv = netdev_priv(dev);
587 void __iomem *ioaddr = priv->base;
588 unsigned long flags;
589
590 spin_lock_irqsave(&priv->lock, flags);
591 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
592 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
593 spin_unlock_irqrestore(&priv->lock, flags);
594
595 return &dev->stats;
596 }
597
598 /* Stop RDC MAC and Free the allocated resource */
599 void r6040_down(struct net_device *dev)
600 {
601 struct r6040_private *lp = netdev_priv(dev);
602 void __iomem *ioaddr = lp->base;
603 struct pci_dev *pdev = lp->pdev;
604 int limit = 2048;
605
606 dbg(DBG_EXIT, "ENTER\n");
607
608 /* Stop MAC */
609 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
610 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
611 udelay(100);
612 while ((ioread16(ioaddr+MCR1) & 1) && limit-- > 0);
613
614 if (limit <= 0)
615 err("timeout while waiting for reset done.\n");
616
617 free_irq(dev->irq, dev);
618
619 /* Free RX buffer */
620 r6040_free_rxbufs(dev);
621
622 /* Free TX buffer */
623 r6040_free_txbufs(dev);
624
625 /* Free Descriptor memory */
626 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
627 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
628
629 dbg(DBG_EXIT, "EXIT\n");
630 }
631
632 int r6040_close(struct net_device *dev)
633 {
634 struct r6040_private *lp = netdev_priv(dev);
635
636 dbg(DBG_EXIT, "ENTER\n");
637
638 /* deleted timer */
639 del_timer_sync(&lp->timer);
640
641 spin_lock_irq(&lp->lock);
642 netif_stop_queue(dev);
643 r6040_down(dev);
644 spin_unlock_irq(&lp->lock);
645
646 dbg(DBG_EXIT, "EXIT\n");
647 return 0;
648 }
649
650 /* Status of PHY CHIP. Returns 0x8000 for full duplex, 0 for half duplex */
651 STATIC int phy_mode_chk(struct net_device *dev)
652 {
653 struct r6040_private *lp = netdev_priv(dev);
654 void __iomem *ioaddr = lp->base;
655 int phy_dat;
656
657 /* PHY Link Status Check */
658 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
659 if (!(phy_dat & 0x4))
660 phy_dat = 0x8000; /* Link Failed, full duplex */
661
662 /* PHY Chip Auto-Negotiation Status */
663 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
664 if (phy_dat & 0x0020) {
665 /* Auto Negotiation Mode */
666 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
667 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
668 if (phy_dat & 0x140)
669 /* Force full duplex */
670 phy_dat = 0x8000;
671 else
672 phy_dat = 0;
673 } else {
674 /* Force Mode */
675 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
676 if (phy_dat & 0x100)
677 phy_dat = 0x8000;
678 else
679 phy_dat = 0x0000;
680 }
681
682 dbg(DBG_PHY, "RETURN x%x\n", phy_dat);
683 return phy_dat;
684 };
685
686 void r6040_set_carrier(struct mii_if_info *mii)
687 {
688 if (phy_mode_chk(mii->dev)) {
689 /* autoneg is off: Link is always assumed to be up */
690 if (!netif_carrier_ok(mii->dev))
691 netif_carrier_on(mii->dev);
692 } else
693 phy_mode_chk(mii->dev);
694 }
695
696 int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
697 {
698 struct r6040_private *lp = netdev_priv(dev);
699 struct mii_ioctl_data *data = if_mii(rq);
700 int rc;
701
702 if (!netif_running(dev))
703 return -EINVAL;
704 spin_lock_irq(&lp->lock);
705 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
706 spin_unlock_irq(&lp->lock);
707 r6040_set_carrier(&lp->mii_if);
708 return rc;
709 }
710
711 int r6040_rx(struct net_device *dev, int limit)
712 {
713 struct r6040_private *priv = netdev_priv(dev);
714 int count;
715 void __iomem *ioaddr = priv->base;
716 u16 err;
717
718 for (count = 0; count < limit; ++count) {
719 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
720 struct sk_buff *skb_ptr;
721
722 descptr = priv->rx_remove_ptr;
723
724 /* Check for errors */
725 err = ioread16(ioaddr + MLSR);
726 if (err & 0x0400)
727 dev->stats.rx_errors++;
728 /* RX FIFO over-run */
729 if (err & 0x8000)
730 dev->stats.rx_fifo_errors++;
731 /* RX descriptor unavailable */
732 if (err & 0x0080)
733 dev->stats.rx_frame_errors++;
734 /* Received packet with length over buffer lenght */
735 if (err & 0x0020)
736 dev->stats.rx_over_errors++;
737 /* Received packet with too long or short */
738 if (err & (0x0010 | 0x0008))
739 dev->stats.rx_length_errors++;
740 /* Received packet with CRC errors */
741 if (err & 0x0004) {
742 spin_lock(&priv->lock);
743 dev->stats.rx_crc_errors++;
744 spin_unlock(&priv->lock);
745 }
746
747 dbg(DBG_RX_IRQ, "descptr %p status x%x err x%x\n",
748 descptr, descptr->status, err);
749
750 while (priv->rx_free_desc) {
751 /* No RX packet */
752 if (descptr->status & 0x8000)
753 break;
754 skb_ptr = descptr->skb_ptr;
755 if (!skb_ptr) {
756 printk(KERN_ERR "%s: Inconsistent RX"
757 "descriptor chain\n",
758 dev->name);
759 break;
760 }
761 descptr->skb_ptr = NULL;
762 skb_ptr->dev = priv->dev;
763 /* Do not count the CRC */
764 skb_put(skb_ptr, descptr->len - 4);
765 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
766 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
767 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
768
769 dbg(DBG_RX_DESCR, "descptr %p status x%x err x%x data len x%x\n",
770 descptr, descptr->status, err, descptr->len);
771
772 {
773 char obuf[2*32+1] __attribute__ ((unused));
774 dbg(DBG_RX_DATA, "rx len x%x: %s...\n",
775 descptr->len,
776 hex2str(skb_ptr->data, obuf, sizeof(obuf)/2, '\0'));
777 }
778
779 /* Send to upper layer */
780 netif_receive_skb(skb_ptr);
781 dev->last_rx = jiffies;
782 dev->stats.rx_packets++;
783 dev->stats.rx_bytes += descptr->len;
784 /* To next descriptor */
785 descptr = descptr->vndescp;
786 priv->rx_free_desc--;
787 }
788 priv->rx_remove_ptr = descptr;
789 }
790 /* Allocate new RX buffer */
791 if (priv->rx_free_desc < RX_DCNT)
792 rx_buf_alloc(priv, priv->dev);
793
794 return count;
795 }
796
797 void r6040_tx(struct net_device *dev)
798 {
799 struct r6040_private *priv = netdev_priv(dev);
800 struct r6040_descriptor *descptr;
801 void __iomem *ioaddr = priv->base;
802 struct sk_buff *skb_ptr;
803 u16 err;
804
805 spin_lock(&priv->lock);
806 descptr = priv->tx_remove_ptr;
807 while (priv->tx_free_desc < TX_DCNT) {
808 /* Check for errors */
809 err = ioread16(ioaddr + MLSR);
810
811 if (err & 0x0200)
812 dev->stats.rx_fifo_errors++;
813 if (err & (0x2000 | 0x4000))
814 dev->stats.tx_carrier_errors++;
815
816 dbg(DBG_TX_IRQ, "descptr %p status x%x err x%x\n",
817 descptr, descptr->status, err);
818
819 if (descptr->status & 0x8000)
820 break; /* Not complete */
821 skb_ptr = descptr->skb_ptr;
822 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
823 skb_ptr->len, PCI_DMA_TODEVICE);
824 /* Free buffer */
825 dev_kfree_skb_irq(skb_ptr);
826 descptr->skb_ptr = NULL;
827 /* To next descriptor */
828 descptr = descptr->vndescp;
829 priv->tx_free_desc++;
830 }
831 priv->tx_remove_ptr = descptr;
832
833 if (priv->tx_free_desc)
834 netif_wake_queue(dev);
835 spin_unlock(&priv->lock);
836 }
837
838 int r6040_poll(struct napi_struct *napi, int budget)
839 {
840 struct r6040_private *priv =
841 container_of(napi, struct r6040_private, napi);
842 struct net_device *dev = priv->dev;
843 void __iomem *ioaddr = priv->base;
844 int work_done;
845
846 work_done = r6040_rx(dev, budget);
847
848 dbg(DBG_POLL, "budget x%x done x%x\n", budget, work_done);
849
850 if (work_done < budget) {
851 netif_rx_complete(dev, napi);
852 /* Enable RX interrupt */
853 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
854 }
855 return work_done;
856 }
857
858 /* The RDC interrupt handler. */
859 irqreturn_t r6040_interrupt(int irq, void *dev_id)
860 {
861 struct net_device *dev = dev_id;
862 struct r6040_private *lp = netdev_priv(dev);
863 void __iomem *ioaddr = lp->base;
864 u16 status;
865
866 /* Read MISR status and clear */
867 status = ioread16(ioaddr + MISR);
868
869 dbg(DBG_IRQ, "status x%x\n", status);
870
871 if (status == 0x0000 || status == 0xffff)
872 return IRQ_NONE;
873
874 /* rx early / rx finish interrupt
875 or rx descriptor unavail. */
876 if (status & RX_INTS) {
877 if (status & RX_NO_DESC) {
878 /* rx descriptor unavail. */
879 dev->stats.rx_dropped++;
880 dev->stats.rx_missed_errors++;
881 }
882 /* Mask off RX interrupts */
883 iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
884 netif_rx_schedule(dev, &lp->napi);
885 }
886
887 /* rx FIFO full */
888 if (status & (1<<2)) {
889 dev->stats.rx_fifo_errors++;
890 }
891
892 /* TX interrupt request */
893 if (status & 0x10)
894 r6040_tx(dev);
895
896 return IRQ_HANDLED;
897 }
898
899 #ifdef CONFIG_NET_POLL_CONTROLLER
900 void r6040_poll_controller(struct net_device *dev)
901 {
902 disable_irq(dev->irq);
903 r6040_interrupt(dev->irq, dev);
904 enable_irq(dev->irq);
905 }
906 #endif
907
908 /* Init RDC MAC */
909 void r6040_up(struct net_device *dev)
910 {
911 struct r6040_private *lp = netdev_priv(dev);
912 void __iomem *ioaddr = lp->base;
913
914 dbg(DBG_INIT, "ENTER\n");
915
916 /* Initialise and alloc RX/TX buffers */
917 r6040_alloc_txbufs(dev);
918 r6040_alloc_rxbufs(dev);
919
920 /* Read the PHY ID */
921 lp->switch_sig = phy_read(ioaddr, 0, 2);
922
923 if (lp->switch_sig == ICPLUS_PHY_ID) {
924 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
925 lp->phy_mode = 0x8000;
926 } else {
927 /* PHY Mode Check */
928 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
929 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
930
931 if (PHY_MODE == 0x3100)
932 lp->phy_mode = phy_mode_chk(dev);
933 else
934 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
935 }
936
937 /* configure duplex mode */
938 lp->mcr0 |= lp->phy_mode;
939
940 /* improve performance (by RDC guys) */
941 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
942 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
943 phy_write(ioaddr, 0, 19, 0x0000);
944 phy_write(ioaddr, 0, 30, 0x01F0);
945
946 /* Reset MAC and init all registers */
947 r6040_init_mac_regs(lp);
948 }
949
950 /*
951 A periodic timer routine
952 Polling PHY Chip Link Status
953 */
954 void r6040_timer(unsigned long data)
955 {
956 struct net_device *dev = (struct net_device *)data;
957 struct r6040_private *lp = netdev_priv(dev);
958 void __iomem *ioaddr = lp->base;
959 u16 phy_mode;
960
961 /* Polling PHY Chip Status */
962 if (PHY_MODE == 0x3100)
963 phy_mode = phy_mode_chk(dev);
964 else
965 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
966
967 if (phy_mode != lp->phy_mode) {
968 lp->phy_mode = phy_mode;
969 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
970 iowrite16(lp->mcr0, ioaddr);
971 printk(KERN_INFO "Link Change x%x \n", ioread16(ioaddr));
972 }
973
974 /* Timer active again */
975 mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
976 }
977
978 int r6040_open(struct net_device *dev)
979 {
980 struct r6040_private *lp = netdev_priv(dev);
981 int ret;
982
983 dbg(DBG_OPEN, "ENTER\n");
984 /* Request IRQ and Register interrupt handler */
985 ret = request_irq(dev->irq, &r6040_interrupt,
986 IRQF_SHARED, dev->name, dev);
987 if (ret)
988 return ret;
989
990 dbg(DBG_OPEN, "got irq %d\n", dev->irq);
991
992 /* Allocate Descriptor memory */
993 lp->rx_ring =
994 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
995 if (!lp->rx_ring)
996 return -ENOMEM;
997
998 dbg(DBG_OPEN, "allocated rx ring\n");
999
1000 lp->tx_ring =
1001 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
1002 if (!lp->tx_ring) {
1003 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
1004 lp->rx_ring_dma);
1005 return -ENOMEM;
1006 }
1007
1008 dbg(DBG_OPEN, "allocated tx ring\n");
1009
1010 r6040_up(dev);
1011
1012 napi_enable(&lp->napi);
1013 netif_start_queue(dev);
1014
1015 /* set and active a timer process */
1016 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
1017 if (lp->switch_sig != ICPLUS_PHY_ID)
1018 mod_timer(&lp->timer, jiffies + HZ);
1019 return 0;
1020 }
1021
1022 int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
1023 {
1024 struct r6040_private *lp = netdev_priv(dev);
1025 struct r6040_descriptor *descptr;
1026 void __iomem *ioaddr = lp->base;
1027 unsigned long flags;
1028 int ret = NETDEV_TX_OK;
1029
1030 /* Critical Section */
1031 spin_lock_irqsave(&lp->lock, flags);
1032
1033 /* TX resource check */
1034 if (!lp->tx_free_desc) {
1035 spin_unlock_irqrestore(&lp->lock, flags);
1036 netif_stop_queue(dev);
1037 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
1038 ret = NETDEV_TX_BUSY;
1039 return ret;
1040 }
1041
1042 /* Statistic Counter */
1043 dev->stats.tx_packets++;
1044 dev->stats.tx_bytes += skb->len;
1045 /* Set TX descriptor & Transmit it */
1046 lp->tx_free_desc--;
1047 descptr = lp->tx_insert_ptr;
1048 if (skb->len < MISR)
1049 descptr->len = MISR;
1050 else
1051 descptr->len = skb->len;
1052
1053 descptr->skb_ptr = skb;
1054 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
1055 skb->data, skb->len, PCI_DMA_TODEVICE));
1056
1057 dbg(DBG_TX_DESCR, "desc @ %p: len x%x buf %08x skb->data %p skb->len x%x\n",
1058 descptr, descptr->len, descptr->buf, skb->data, skb->len);
1059
1060 {
1061 char obuf[2*32+1];
1062 dbg(DBG_TX_DATA, "tx len x%x: %s\n",
1063 descptr->len, hex2str(skb->data, obuf, sizeof(obuf)/2, '\0'));
1064 }
1065
1066 descptr->status = 0x8000;
1067 /* Trigger the MAC to check the TX descriptor */
1068 iowrite16(0x01, ioaddr + MTPR);
1069 lp->tx_insert_ptr = descptr->vndescp;
1070
1071 /* If no tx resource, stop */
1072 if (!lp->tx_free_desc)
1073 netif_stop_queue(dev);
1074
1075 dev->trans_start = jiffies;
1076 spin_unlock_irqrestore(&lp->lock, flags);
1077 return ret;
1078 }
1079
1080 /*! set MAC addresses and promiscous mode */
1081 void r6040_multicast_list(struct net_device *dev)
1082 {
1083 struct r6040_private *lp = netdev_priv(dev);
1084 void __iomem *ioaddr = lp->base;
1085 u16 *adrp;
1086 u16 reg;
1087 unsigned long flags;
1088 struct dev_mc_list *dmi = dev->mc_list;
1089 int i;
1090 char obuf[3*ETH_ALEN] __attribute__ ((unused));
1091
1092 /* MAC Address */
1093 adrp = (u16 *)dev->dev_addr;
1094 iowrite16(adrp[0], ioaddr + MID_0L);
1095 iowrite16(adrp[1], ioaddr + MID_0M);
1096 iowrite16(adrp[2], ioaddr + MID_0H);
1097
1098 dbg(DBG_MAC_ADDR, "%s: set MAC addr %s\n",
1099 dev->name, hex2str(dev->dev_addr, obuf, ETH_ALEN, ':'));
1100
1101 /* Promiscous Mode */
1102 spin_lock_irqsave(&lp->lock, flags);
1103
1104 /* Clear AMCP & PROM bits */
1105 reg = ioread16(ioaddr) & ~0x0120;
1106 if (dev->flags & IFF_PROMISC) {
1107 reg |= 0x0020;
1108 lp->mcr0 |= 0x0020;
1109 }
1110 /* Too many multicast addresses
1111 * accept all traffic */
1112 else if ((dev->mc_count > MCAST_MAX)
1113 || (dev->flags & IFF_ALLMULTI))
1114 reg |= 0x0020;
1115
1116 iowrite16(reg, ioaddr);
1117 spin_unlock_irqrestore(&lp->lock, flags);
1118
1119 /* Build the hash table */
1120 if (dev->mc_count > MCAST_MAX) {
1121 u16 hash_table[4];
1122 u32 crc;
1123
1124 for (i = 0; i < 4; i++)
1125 hash_table[i] = 0;
1126
1127 for (i = 0; i < dev->mc_count; i++) {
1128 char *addrs = dmi->dmi_addr;
1129
1130 dmi = dmi->next;
1131
1132 if (!(*addrs & 1))
1133 continue;
1134
1135 crc = ether_crc_le(6, addrs);
1136 crc >>= 26;
1137 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1138 }
1139 /* Write the index of the hash table */
1140 for (i = 0; i < 4; i++)
1141 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
1142 /* Fill the MAC hash tables with their values */
1143 iowrite16(hash_table[0], ioaddr + MAR0);
1144 iowrite16(hash_table[1], ioaddr + MAR1);
1145 iowrite16(hash_table[2], ioaddr + MAR2);
1146 iowrite16(hash_table[3], ioaddr + MAR3);
1147 }
1148 /* Multicast Address 1~4 case */
1149 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
1150 adrp = (u16 *)dmi->dmi_addr;
1151 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
1152 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
1153 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
1154 dmi = dmi->next;
1155 }
1156 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1157 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1158 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1159 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1160 }
1161 }
1162
1163 STATIC void netdev_get_drvinfo(struct net_device *dev,
1164 struct ethtool_drvinfo *info)
1165 {
1166 struct r6040_private *rp = netdev_priv(dev);
1167
1168 strcpy(info->driver, DRV_NAME);
1169 strcpy(info->version, DRV_VERSION);
1170 strcpy(info->bus_info, pci_name(rp->pdev));
1171 }
1172
1173 STATIC int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1174 {
1175 struct r6040_private *rp = netdev_priv(dev);
1176 int rc;
1177
1178 spin_lock_irq(&rp->lock);
1179 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1180 spin_unlock_irq(&rp->lock);
1181
1182 return rc;
1183 }
1184
1185 STATIC int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1186 {
1187 struct r6040_private *rp = netdev_priv(dev);
1188 int rc;
1189
1190 spin_lock_irq(&rp->lock);
1191 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1192 spin_unlock_irq(&rp->lock);
1193 r6040_set_carrier(&rp->mii_if);
1194
1195 return rc;
1196 }
1197
1198 STATIC u32 netdev_get_link(struct net_device *dev)
1199 {
1200 struct r6040_private *rp = netdev_priv(dev);
1201
1202 return mii_link_ok(&rp->mii_if);
1203 }
1204
1205 static struct ethtool_ops netdev_ethtool_ops = {
1206 .get_drvinfo = netdev_get_drvinfo,
1207 .get_settings = netdev_get_settings,
1208 .set_settings = netdev_set_settings,
1209 .get_link = netdev_get_link,
1210 };
1211
1212 int __devinit r6040_init_one(struct pci_dev *pdev,
1213 const struct pci_device_id *ent)
1214 {
1215 struct net_device *dev;
1216 struct r6040_private *lp;
1217 void __iomem *ioaddr;
1218 int err, io_size = R6040_IO_SIZE;
1219 static int card_idx = -1;
1220 int bar = 0;
1221 long pioaddr;
1222
1223 printk(KERN_INFO "%s\n", version);
1224 printk(KERN_INFO DRV_NAME ": debug %x\n", debug);
1225
1226 err = pci_enable_device(pdev);
1227 if (err)
1228 return err;
1229
1230 /* this should always be supported */
1231 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1232 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1233 "not supported by the card\n");
1234 return -ENODEV;
1235 }
1236 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1237 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1238 "not supported by the card\n");
1239 return -ENODEV;
1240 }
1241
1242 /* IO Size check */
1243 if (pci_resource_len(pdev, 0) < io_size) {
1244 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1245 return -EIO;
1246 }
1247
1248 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1249 pci_set_master(pdev);
1250
1251 dev = alloc_etherdev(sizeof(struct r6040_private));
1252 if (!dev) {
1253 printk(KERN_ERR "Failed to allocate etherdev\n");
1254 return -ENOMEM;
1255 }
1256 SET_NETDEV_DEV(dev, &pdev->dev);
1257 lp = netdev_priv(dev);
1258 lp->pdev = pdev;
1259 lp->dev = dev;
1260
1261 if (pci_request_regions(pdev, DRV_NAME)) {
1262 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1263 err = -ENODEV;
1264 goto err_out_disable;
1265 }
1266
1267 ioaddr = pci_iomap(pdev, bar, io_size);
1268 if (!ioaddr) {
1269 printk(KERN_ERR "ioremap failed for device %s\n",
1270 pci_name(pdev));
1271 return -EIO;
1272 }
1273
1274 /* Init system & device */
1275 lp->base = ioaddr;
1276 dev->irq = pdev->irq;
1277
1278 spin_lock_init(&lp->lock);
1279 pci_set_drvdata(pdev, dev);
1280
1281 card_idx++;
1282
1283 /* Link new device into r6040_root_dev */
1284 lp->pdev = pdev;
1285
1286 /* Init RDC private data */
1287 lp->mcr0 = 0x1002;
1288 lp->phy_addr = phy_table[card_idx];
1289 lp->switch_sig = 0;
1290
1291 /* The RDC-specific entries in the device structure. */
1292 dev->open = &r6040_open;
1293 dev->hard_start_xmit = &r6040_start_xmit;
1294 dev->stop = &r6040_close;
1295 dev->get_stats = r6040_get_stats;
1296 dev->set_multicast_list = &r6040_multicast_list;
1297 dev->do_ioctl = &r6040_ioctl;
1298 dev->ethtool_ops = &netdev_ethtool_ops;
1299 dev->tx_timeout = &r6040_tx_timeout;
1300 dev->watchdog_timeo = TX_TIMEOUT;
1301
1302 {
1303 /* TODO: fix the setting of the MAC address.
1304 Right now you must either specify a netdevice with "parent=", whose
1305 address is copied or the (default) address of the Sitecom WL-153
1306 bootloader is used */
1307 static const u8 dflt_addr[ETH_ALEN] = {0,0x50,0xfc,2,3,4};
1308 if (parent_dev) {
1309 memcpy(dev->dev_addr, parent_dev->dev_addr, ETH_ALEN);
1310 } else {
1311 printk(KERN_WARNING "%s: no parent - using default mac address\n",
1312 dev->name);
1313 memcpy(dev->dev_addr, dflt_addr, ETH_ALEN);
1314 }
1315 dev->dev_addr[ETH_ALEN-1] += card_idx; /* + 0 or 1 */
1316 }
1317
1318 #ifdef CONFIG_NET_POLL_CONTROLLER
1319 dev->poll_controller = r6040_poll_controller;
1320 #endif
1321 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1322 lp->mii_if.dev = dev;
1323 lp->mii_if.mdio_read = mdio_read;
1324 lp->mii_if.mdio_write = mdio_write;
1325 lp->mii_if.phy_id = lp->phy_addr;
1326 lp->mii_if.phy_id_mask = 0x1f;
1327 lp->mii_if.reg_num_mask = 0x1f;
1328
1329 /* Register net device. After this dev->name assign */
1330 err = register_netdev(dev);
1331 if (err) {
1332 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1333 goto err_out_res;
1334 }
1335
1336 dbg(DBG_INIT, "%s successfully registered\n", dev->name);
1337 return 0;
1338
1339 err_out_res:
1340 pci_release_regions(pdev);
1341 err_out_disable:
1342 pci_disable_device(pdev);
1343 pci_set_drvdata(pdev, NULL);
1344 free_netdev(dev);
1345
1346 return err;
1347 }
1348
1349 void __devexit r6040_remove_one(struct pci_dev *pdev)
1350 {
1351 struct net_device *dev = pci_get_drvdata(pdev);
1352
1353 unregister_netdev(dev);
1354 pci_release_regions(pdev);
1355 free_netdev(dev);
1356 pci_disable_device(pdev);
1357 pci_set_drvdata(pdev, NULL);
1358 }
1359
1360
1361 static struct pci_device_id r6040_pci_tbl[] = {
1362 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1363 { 0 }
1364 };
1365 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1366
1367 static struct pci_driver r6040_driver = {
1368 .name = DRV_NAME,
1369 .id_table = r6040_pci_tbl,
1370 .probe = r6040_init_one,
1371 .remove = __devexit_p(r6040_remove_one),
1372 };
1373
1374
1375 static int __init r6040_init(void)
1376 {
1377 if (parent)
1378 parent_dev = dev_get_by_name(&init_net, parent);
1379
1380 return pci_register_driver(&r6040_driver);
1381 }
1382
1383
1384 static void __exit r6040_cleanup(void)
1385 {
1386 pci_unregister_driver(&r6040_driver);
1387 }
1388
1389 module_init(r6040_init);
1390 module_exit(r6040_cleanup);
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