2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/serial_8250.h>
20 #include <linux/bootmem.h>
22 #include <asm/bootinfo.h>
23 #include <asm/traps.h>
24 #include <asm/time.h> /* for mips_hpt_frequency */
25 #include <asm/reboot.h> /* for _machine_{restart,halt} */
26 #include <asm/mips_machine.h>
28 #include <asm/mach-ar71xx/ar71xx.h>
29 #include <asm/mach-ar71xx/pci.h>
30 #include <asm/mach-ar71xx/platform.h>
32 #define AR71XX_SYS_TYPE_LEN 64
33 #define AR71XX_BASE_FREQ 40000000
34 #define AR91XX_BASE_FREQ 5000000
36 unsigned long ar71xx_mach_type
;
39 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq
);
42 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq
);
45 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq
);
47 enum ar71xx_soc_type ar71xx_soc
;
48 EXPORT_SYMBOL_GPL(ar71xx_soc
);
50 int (*ar71xx_pci_bios_init
)(unsigned nr_irqs
,
51 struct ar71xx_pci_irq
*map
) __initdata
;
53 int (*ar71xx_pci_be_handler
)(int is_fixup
);
55 static char ar71xx_sys_type
[AR71XX_SYS_TYPE_LEN
];
57 static void ar71xx_restart(char *command
)
59 ar71xx_device_stop(RESET_MODULE_FULL_CHIP
);
65 static void ar71xx_halt(void)
71 static int ar71xx_be_handler(struct pt_regs
*regs
, int is_fixup
)
75 if (ar71xx_pci_be_handler
)
76 err
= ar71xx_pci_be_handler(is_fixup
);
78 return (is_fixup
&& !err
) ? MIPS_BE_FIXUP
: MIPS_BE_FATAL
;
81 int __init
ar71xx_pci_init(unsigned nr_irqs
, struct ar71xx_pci_irq
*map
)
83 if (!ar71xx_pci_bios_init
)
86 return ar71xx_pci_bios_init(nr_irqs
, map
);
89 static void __init
ar71xx_detect_mem_size(void)
93 for (size
= AR71XX_MEM_SIZE_MIN
; size
< AR71XX_MEM_SIZE_MAX
;
95 if (!memcmp(ar71xx_detect_mem_size
,
96 ar71xx_detect_mem_size
+ size
, 1024))
100 add_memory_region(0, size
, BOOT_MEM_RAM
);
103 static void __init
ar71xx_detect_sys_type(void)
109 id
= ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID
) & REV_ID_MASK
;
110 rev
= (id
>> REV_ID_REVISION_SHIFT
) & REV_ID_REVISION_MASK
;
112 switch (id
& REV_ID_CHIP_MASK
) {
113 case REV_ID_CHIP_AR7130
:
114 ar71xx_soc
= AR71XX_SOC_AR7130
;
118 case REV_ID_CHIP_AR7141
:
119 ar71xx_soc
= AR71XX_SOC_AR7141
;
123 case REV_ID_CHIP_AR7161
:
124 ar71xx_soc
= AR71XX_SOC_AR7161
;
128 case REV_ID_CHIP_AR9130
:
129 ar71xx_soc
= AR71XX_SOC_AR9130
;
133 case REV_ID_CHIP_AR9132
:
134 ar71xx_soc
= AR71XX_SOC_AR9132
;
139 panic("ar71xx: unknown chip id:0x%02x\n", id
);
142 sprintf(ar71xx_sys_type
, "Atheros AR%s rev %u (id:0x%02x)",
146 static void __init
ar91xx_detect_sys_frequency(void)
152 pll
= ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG
);
154 div
= ((pll
>> AR91XX_PLL_DIV_SHIFT
) & AR91XX_PLL_DIV_MASK
);
155 freq
= div
* AR91XX_BASE_FREQ
;
157 ar71xx_cpu_freq
= freq
;
159 div
= ((pll
>> AR91XX_DDR_DIV_SHIFT
) & AR91XX_DDR_DIV_MASK
) + 1;
160 ar71xx_ddr_freq
= freq
/ div
;
162 div
= (((pll
>> AR91XX_AHB_DIV_SHIFT
) & AR91XX_AHB_DIV_MASK
) + 1) * 2;
163 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
166 static void __init
ar71xx_detect_sys_frequency(void)
172 pll
= ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG
);
174 div
= ((pll
>> AR71XX_PLL_DIV_SHIFT
) & AR71XX_PLL_DIV_MASK
) + 1;
175 freq
= div
* AR71XX_BASE_FREQ
;
177 div
= ((pll
>> AR71XX_CPU_DIV_SHIFT
) & AR71XX_CPU_DIV_MASK
) + 1;
178 ar71xx_cpu_freq
= freq
/ div
;
180 div
= ((pll
>> AR71XX_DDR_DIV_SHIFT
) & AR71XX_DDR_DIV_MASK
) + 1;
181 ar71xx_ddr_freq
= freq
/ div
;
183 div
= (((pll
>> AR71XX_AHB_DIV_SHIFT
) & AR71XX_AHB_DIV_MASK
) + 1) * 2;
184 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
187 static void __init
detect_sys_frequency(void)
189 switch (ar71xx_soc
) {
190 case AR71XX_SOC_AR7130
:
191 case AR71XX_SOC_AR7141
:
192 case AR71XX_SOC_AR7161
:
193 ar71xx_detect_sys_frequency();
196 case AR71XX_SOC_AR9130
:
197 case AR71XX_SOC_AR9132
:
198 ar91xx_detect_sys_frequency();
206 #ifdef CONFIG_AR71XX_EARLY_SERIAL
207 static void __init
ar71xx_early_serial_setup(void)
211 memset(&p
, 0, sizeof(p
));
213 p
.flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_IOREMAP
;
214 p
.iotype
= UPIO_MEM32
;
215 p
.uartclk
= ar71xx_ahb_freq
;
216 p
.irq
= AR71XX_MISC_IRQ_UART
;
218 p
.mapbase
= AR71XX_UART_BASE
;
220 early_serial_setup(&p
);
223 static inline void ar71xx_early_serial_setup(void) {};
224 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
226 const char *get_system_type(void)
228 return ar71xx_sys_type
;
231 unsigned int __cpuinit
get_c0_compare_irq(void)
233 return CP0_LEGACY_COMPARE_IRQ
;
236 void __init
plat_mem_setup(void)
238 set_io_port_base(KSEG1
);
240 ar71xx_ddr_base
= ioremap_nocache(AR71XX_DDR_CTRL_BASE
,
241 AR71XX_DDR_CTRL_SIZE
);
243 ar71xx_pll_base
= ioremap_nocache(AR71XX_PLL_BASE
,
246 ar71xx_reset_base
= ioremap_nocache(AR71XX_RESET_BASE
,
249 ar71xx_gpio_base
= ioremap_nocache(AR71XX_GPIO_BASE
, AR71XX_GPIO_SIZE
);
251 ar71xx_usb_ctrl_base
= ioremap_nocache(AR71XX_USB_CTRL_BASE
,
252 AR71XX_USB_CTRL_SIZE
);
254 ar71xx_detect_mem_size();
255 ar71xx_detect_sys_type();
256 detect_sys_frequency();
259 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
261 ar71xx_cpu_freq
/ 1000000, (ar71xx_cpu_freq
/ 1000) % 1000,
262 ar71xx_ahb_freq
/ 1000000, (ar71xx_ahb_freq
/ 1000) % 1000,
263 ar71xx_ddr_freq
/ 1000000, (ar71xx_ddr_freq
/ 1000) % 1000);
265 _machine_restart
= ar71xx_restart
;
266 _machine_halt
= ar71xx_halt
;
267 pm_power_off
= ar71xx_halt
;
269 board_be_handler
= ar71xx_be_handler
;
271 ar71xx_early_serial_setup();
274 void __init
plat_time_init(void)
276 mips_hpt_frequency
= ar71xx_cpu_freq
/ 2;
279 static int __init
ar71xx_machine_setup(void)
283 ar71xx_add_device_uart();
284 ar71xx_add_device_wdt();
286 mips_machine_setup(ar71xx_mach_type
);
290 arch_initcall(ar71xx_machine_setup
);