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0cb200bf94d2489592adcc6ec153bb40252e502c
[openwrt.git] / target / linux / storm / patches / 1005-gmac-napi-mask-intrs.patch
1 Index: linux-2.6.23.17/drivers/net/sl351x_gmac.c
2 ===================================================================
3 --- linux-2.6.23.17.orig/drivers/net/sl351x_gmac.c
4 +++ linux-2.6.23.17/drivers/net/sl351x_gmac.c
5 @@ -127,6 +127,7 @@ static char _debug_prefetch_buf[_DEBUG_P
6 static int gmac_initialized = 0;
7 TOE_INFO_T toe_private_data;
8 static int do_again = 0;
9 +static int rx_poll_enabled;
10 spinlock_t gmac_fq_lock;
11 unsigned int FLAG_SWITCH;
12
13 @@ -1065,7 +1066,8 @@ static void toe_init_gmac(struct net_dev
14 tp->intr3_enabled = 0xffffffff;
15 tp->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
16 HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
17 - tp->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
18 + tp->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT| GMAC0_RX_OVERRUN_INT_BIT;
19 + // GMAC0_TX_PAUSE_OFF_INT_BIT| GMAC0_MIB_INT_BIT;
20
21 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
22 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
23 @@ -1115,7 +1117,7 @@ static void toe_init_gmac(struct net_dev
24 tp->intr3_enabled |= 0xffffffff;
25 tp->intr4_selected |= CLASS_RX_FULL_INT_BITS |
26 HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
27 - tp->intr4_enabled |= SWFQ_EMPTY_INT_BIT;
28 + tp->intr4_enabled |= SWFQ_EMPTY_INT_BIT | GMAC1_RX_OVERRUN_INT_BIT;
29 }
30 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
31 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
32 @@ -2408,7 +2410,7 @@ static inline void toe_gmac_fill_free_q(
33 // unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
34
35 fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
36 - spin_lock_irqsave(&gmac_fq_lock, flags);
37 + // spin_lock_irqsave(&gmac_fq_lock, flags);
38 //while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
39 // TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
40 while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
41 @@ -2428,10 +2430,47 @@ static inline void toe_gmac_fill_free_q(
42 SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
43 toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
44 }
45 - spin_unlock_irqrestore(&gmac_fq_lock, flags);
46 + // spin_unlock_irqrestore(&gmac_fq_lock, flags);
47 }
48 // EXPORT_SYMBOL(toe_gmac_fill_free_q);
49
50 +static void gmac_registers(const char *message)
51 +{
52 + unsigned int status0;
53 + unsigned int status1;
54 + unsigned int status2;
55 + unsigned int status3;
56 + unsigned int status4;
57 +
58 + printk("%s\n", message);
59 +
60 + status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
61 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
62 + status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
63 + status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
64 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
65 +
66 + printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
67 + status0, status1, status2, status3, status4);
68 +
69 + status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
70 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
71 + status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
72 + status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
73 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
74 +
75 + printk("mask : s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
76 + status0, status1, status2, status3, status4);
77 +
78 + status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
79 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
80 + status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
81 + status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
82 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
83 +
84 + printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
85 + status0, status1, status2, status3, status4);
86 +}
87 /*----------------------------------------------------------------------
88 * toe_gmac_interrupt
89 *----------------------------------------------------------------------*/
90 @@ -2492,6 +2531,7 @@ if (1)
91 writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
92 if (status4)
93 writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
94 +
95 #if 0
96 /* handle freeq interrupt first */
97 if (status4 & tp->intr4_enabled) {
98 @@ -2536,10 +2576,31 @@ if (1)
99 }
100 if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
101 {
102 - if (likely(netif_rx_schedule_prep(dev)))
103 + if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
104 {
105 - // unsigned int data32;
106 - // disable GMAC-0 rx interrupt
107 + unsigned int data32;
108 +
109 + if (rx_poll_enabled)
110 + gmac_registers("check #1");
111 +
112 + BUG_ON(rx_poll_enabled == 1);
113 +
114 +#if 0
115 + /* Masks GMAC-0 rx interrupt */
116 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
117 + data32 &= ~(DEFAULT_Q0_INT_BIT);
118 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
119 +
120 + /* Masks GMAC-0 queue empty interrupt */
121 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
122 + data32 &= ~DEFAULT_Q0_INT_BIT;
123 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
124 +
125 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
126 + data32 &= ~DEFAULT_Q0_INT_BIT;
127 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
128 +#endif
129 +
130 // class-Q & TOE-Q are implemented in future
131 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
132 //data32 &= ~DEFAULT_Q0_INT_BIT;
133 @@ -2549,7 +2610,8 @@ if (1)
134 //tp->total_q_cnt_napi=0;
135 //rx_time = jiffies;
136 //rx_old_bytes = isPtr->rx_bytes;
137 - __netif_rx_schedule(dev);
138 + __netif_rx_schedule(dev);
139 + rx_poll_enabled = 1;
140 }
141 }
142 }
143 @@ -2569,9 +2631,31 @@ if (1)
144
145 if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
146 {
147 - if (likely(netif_rx_schedule_prep(dev)))
148 + if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
149 {
150 - // unsigned int data32;
151 + unsigned int data32;
152 +
153 + if (rx_poll_enabled)
154 + gmac_registers("check #2");
155 +
156 + BUG_ON(rx_poll_enabled == 1);
157 +
158 +#if 0
159 + /* Masks GMAC-1 rx interrupt */
160 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
161 + data32 &= ~(DEFAULT_Q1_INT_BIT);
162 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
163 +
164 + /* Masks GMAC-1 queue empty interrupt */
165 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
166 + data32 &= ~DEFAULT_Q1_INT_BIT;
167 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
168 +
169 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
170 + data32 &= ~DEFAULT_Q1_INT_BIT;
171 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
172 +#endif
173 +
174 // disable GMAC-0 rx interrupt
175 // class-Q & TOE-Q are implemented in future
176 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
177 @@ -2583,9 +2667,13 @@ if (1)
178 //rx_time = jiffies;
179 //rx_old_bytes = isPtr->rx_bytes;
180 __netif_rx_schedule(dev);
181 + rx_poll_enabled = 1;
182 }
183 }
184 }
185 + } else {
186 +
187 + gmac_registers("check #3");
188 }
189
190 // Interrupt Status 0
191 @@ -3306,8 +3394,10 @@ next_rx:
192 SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
193 tp->rx_rwptr.bits32 = rwptr.bits32;
194
195 - toe_gmac_fill_free_q();
196 }
197 +
198 + /* Handles first available packets only then refill the queue. */
199 + toe_gmac_fill_free_q();
200 }
201
202 /*----------------------------------------------------------------------
203 @@ -4217,6 +4307,7 @@ static int gmac_rx_poll(struct net_devic
204 GMAC_RXDESC_T *curr_desc;
205 struct sk_buff *skb;
206 DMA_RWPTR_T rwptr;
207 + unsigned int data32;
208 unsigned int pkt_size;
209 unsigned int desc_count;
210 unsigned int good_frame, chksum_status, rx_status;
211 @@ -4231,7 +4322,7 @@ static int gmac_rx_poll(struct net_devic
212 //unsigned long long rx_time;
213
214
215 -
216 + BUG_ON(rx_poll_enabled == 0);
217 #if 1
218 if (do_again)
219 {
220 @@ -4516,6 +4607,30 @@ static int gmac_rx_poll(struct net_devic
221 #endif
222 //toe_gmac_fill_free_q();
223 netif_rx_complete(dev);
224 +
225 + rx_poll_enabled = 0;
226 +
227 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
228 + if (tp->port_id == 0)
229 + data32 |= DEFAULT_Q0_INT_BIT;
230 + else
231 + data32 |= DEFAULT_Q1_INT_BIT;
232 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
233 +
234 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
235 + if (tp->port_id == 0)
236 + data32 |= DEFAULT_Q0_INT_BIT;
237 + else
238 + data32 |= DEFAULT_Q1_INT_BIT;
239 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
240 +
241 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
242 + if (tp->port_id == 0)
243 + data32 |= DEFAULT_Q0_INT_BIT;
244 + else
245 + data32 |= DEFAULT_Q1_INT_BIT;
246 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
247 +
248 // enable GMAC-0 rx interrupt
249 // class-Q & TOE-Q are implemented in future
250 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
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