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[openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ahcd fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
17 *
18 * This file is licenced under the GPL.
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "v0.04"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #define ADMHC_VERBOSE_DEBUG /* not always helpful */
55 #define ADMHC_POLL_RH
56 #undef ADMHC_LOCK_DMA
57
58 /* For initializing controller (mask in an HCFS mode too) */
59 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
60
61 #define ADMHC_INTR_INIT \
62 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
63 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
64
65 /*-------------------------------------------------------------------------*/
66
67 static const char hcd_name [] = "admhc-hcd";
68
69 #define STATECHANGE_DELAY msecs_to_jiffies(300)
70
71 #include "adm5120.h"
72
73 static void admhc_dump(struct admhcd *ahcd, int verbose);
74 static int admhc_init(struct admhcd *ahcd);
75 static void admhc_stop(struct usb_hcd *hcd);
76
77 #include "adm5120-dbg.c"
78 #include "adm5120-mem.c"
79 #include "adm5120-pm.c"
80 #include "adm5120-hub.c"
81 #include "adm5120-q.c"
82
83 /*-------------------------------------------------------------------------*/
84
85 /*
86 * queue up an urb for anything except the root hub
87 */
88 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
89 struct urb *urb, gfp_t mem_flags)
90 {
91 struct admhcd *ahcd = hcd_to_admhcd(hcd);
92 struct ed *ed;
93 struct urb_priv *urb_priv;
94 unsigned int pipe = urb->pipe;
95 int td_cnt = 0;
96 unsigned long flags;
97 int ret = 0;
98
99 #ifdef ADMHC_VERBOSE_DEBUG
100 spin_lock_irqsave(&ahcd->lock, flags);
101 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
102 spin_unlock_irqrestore(&ahcd->lock, flags);
103 #endif
104
105 /* every endpoint has an ed, locate and maybe (re)initialize it */
106 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
107 if (!ed)
108 return -ENOMEM;
109
110 /* for the private part of the URB we need the number of TDs */
111 switch (ed->type) {
112 case PIPE_CONTROL:
113 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
114 /* td_submit_urb() doesn't yet handle these */
115 return -EMSGSIZE;
116
117 /* 1 TD for setup, 1 for ACK, plus ... */
118 td_cnt = 2;
119 if (urb->transfer_buffer_length)
120 td_cnt++;
121 break;
122 case PIPE_BULK:
123 /* one TD for every 4096 Bytes (can be upto 8K) */
124 td_cnt = urb->transfer_buffer_length / TD_DATALEN_MAX;
125 /* ... and for any remaining bytes ... */
126 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
127 td_cnt++;
128 /* ... and maybe a zero length packet to wrap it up */
129 if (td_cnt == 0)
130 td_cnt++;
131 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
132 && (urb->transfer_buffer_length
133 % usb_maxpacket(urb->dev, pipe,
134 usb_pipeout (pipe))) == 0)
135 td_cnt++;
136 break;
137 case PIPE_INTERRUPT:
138 /*
139 * for Interrupt IN/OUT transactions, each ED contains
140 * only 1 TD.
141 * TODO: check transfer_buffer_length?
142 */
143 td_cnt = 1;
144 break;
145 case PIPE_ISOCHRONOUS:
146 /* number of packets from URB */
147 td_cnt = urb->number_of_packets;
148 break;
149 default:
150 /* paranoia */
151 admhc_err(ahcd, "bad EP type %d", ed->type);
152 return -EINVAL;
153 }
154
155 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
156 if (!urb_priv)
157 return -ENOMEM;
158
159 urb_priv->ed = ed;
160 urb_priv->urb = urb;
161
162 spin_lock_irqsave(&ahcd->lock, flags);
163 /* don't submit to a dead HC */
164 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
165 ret = -ENODEV;
166 goto fail;
167 }
168 if (!HC_IS_RUNNING(hcd->state)) {
169 ret = -ENODEV;
170 goto fail;
171 }
172
173 /* in case of unlink-during-submit */
174 spin_lock(&urb->lock);
175 if (urb->status != -EINPROGRESS) {
176 spin_unlock(&urb->lock);
177 urb->hcpriv = urb_priv;
178 finish_urb(ahcd, urb);
179 ret = 0;
180 goto fail;
181 }
182
183 if (ed->type == PIPE_ISOCHRONOUS) {
184 if (ed->state == ED_NEW) {
185 u16 frame = admhc_frame_no(ahcd);
186
187 /* delay a few frames before the first TD */
188 frame += max_t (u16, 8, ed->interval);
189 frame &= ~(ed->interval - 1);
190 frame |= ed->branch;
191 urb->start_frame = frame;
192
193 /* yes, only URB_ISO_ASAP is supported, and
194 * urb->start_frame is never used as input.
195 */
196 } else
197 urb->start_frame = ed->last_iso + ed->interval;
198 }
199
200 urb->hcpriv = urb_priv;
201 td_submit_urb(ahcd, urb_priv->urb);
202
203 /* append it to the ED's queue */
204 list_add_tail(&urb_priv->pending, &ed->urb_pending);
205
206 /* schedule the ED */
207 ret = ed_schedule(ahcd, ed);
208
209 fail0:
210 spin_unlock(&urb->lock);
211 fail:
212 if (ret) {
213 urb_priv = urb->hcpriv;
214 urb_priv_free(ahcd, urb_priv);
215 }
216
217 spin_unlock_irqrestore(&ahcd->lock, flags);
218 return ret;
219 }
220
221 /*
222 * decouple the URB from the HC queues (TDs, urb_priv); it's
223 * already marked using urb->status. reporting is always done
224 * asynchronously, and we might be dealing with an urb that's
225 * partially transferred, or an ED with other urbs being unlinked.
226 */
227 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
228 {
229 struct admhcd *ahcd = hcd_to_admhcd(hcd);
230 struct urb_priv *up;
231 unsigned long flags;
232
233 up = urb->hcpriv;
234 if (!up)
235 return 0;
236
237 spin_lock_irqsave(&ahcd->lock, flags);
238
239 #ifdef ADMHC_VERBOSE_DEBUG
240 urb_print(ahcd, urb, "DEQEUE", 1);
241 #endif
242
243 if (HC_IS_RUNNING(hcd->state)) {
244 /* Unless an IRQ completed the unlink while it was being
245 * handed to us, flag it for unlink and giveback, and force
246 * some upcoming INTR_SF to call finish_unlinks()
247 */
248 if (up->ed->urb_active != up) {
249 list_del(&up->pending);
250 finish_urb(ahcd, urb);
251 } else {
252 ed_start_deschedule(ahcd, up->ed);
253 }
254 } else {
255 /*
256 * with HC dead, we won't respect hc queue pointers
257 * any more ... just clean up every urb's memory.
258 */
259 if (up->ed->urb_active != up) {
260 list_del(&up->pending);
261 finish_urb(ahcd, urb);
262 } else {
263 finish_urb(ahcd, urb);
264 up->ed->urb_active = NULL;
265 up->ed->state = ED_IDLE;
266 }
267 }
268 spin_unlock_irqrestore(&ahcd->lock, flags);
269
270 return 0;
271 }
272
273 /*-------------------------------------------------------------------------*/
274
275 /* frees config/altsetting state for endpoints,
276 * including ED memory, dummy TD, and bulk/intr data toggle
277 */
278 static void admhc_endpoint_disable(struct usb_hcd *hcd,
279 struct usb_host_endpoint *ep)
280 {
281 struct admhcd *ahcd = hcd_to_admhcd(hcd);
282 unsigned long flags;
283 struct ed *ed = ep->hcpriv;
284 unsigned limit = 1000;
285
286 /* ASSERT: any requests/urbs are being unlinked */
287 /* ASSERT: nobody can be submitting urbs for this any more */
288
289 if (!ed)
290 return;
291
292 #ifdef ADMHC_VERBOSE_DEBUG
293 spin_lock_irqsave(&ahcd->lock, flags);
294 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
295 spin_unlock_irqrestore(&ahcd->lock, flags);
296 #endif
297
298 rescan:
299 spin_lock_irqsave(&ahcd->lock, flags);
300
301 if (!HC_IS_RUNNING(hcd->state)) {
302 sanitize:
303 ed->state = ED_UNLINK;
304 admhc_finish_unlinks(ahcd, 0);
305 }
306
307 switch (ed->state) {
308 case ED_UNLINK: /* wait for hw to finish? */
309 /* major IRQ delivery trouble loses INTR_SOFI too... */
310 if (limit-- == 0) {
311 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
312 goto sanitize;
313 }
314 spin_unlock_irqrestore(&ahcd->lock, flags);
315 schedule_timeout_uninterruptible(1);
316 goto rescan;
317 case ED_IDLE:
318 case ED_NEW: /* fully unlinked */
319 if (list_empty(&ed->urb_pending)) {
320 td_free(ahcd, ed->dummy);
321 ed_free(ahcd, ed);
322 break;
323 }
324 /* else FALL THROUGH */
325 default:
326 /* caller was supposed to have unlinked any requests;
327 * that's not our job. can't recover; must leak ed.
328 */
329 admhc_err(ahcd, "leak ed %p (#%02x) %s act %p%s\n",
330 ed, ep->desc.bEndpointAddress,
331 ed_statestring(ed->state),
332 ed->urb_active,
333 list_empty(&ed->urb_pending) ? "" : " (has urbs)");
334 break;
335 }
336
337 ep->hcpriv = NULL;
338
339 spin_unlock_irqrestore(&ahcd->lock, flags);
340 return;
341 }
342
343 static int admhc_get_frame_number(struct usb_hcd *hcd)
344 {
345 struct admhcd *ahcd = hcd_to_admhcd(hcd);
346
347 return admhc_frame_no(ahcd);
348 }
349
350 static void admhc_usb_reset(struct admhcd *ahcd)
351 {
352 ahcd->host_control = ADMHC_BUSS_RESET;
353 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
354 }
355
356 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
357 * other cases where the next software may expect clean state from the
358 * "firmware". this is bus-neutral, unlike shutdown() methods.
359 */
360 static void
361 admhc_shutdown(struct usb_hcd *hcd)
362 {
363 struct admhcd *ahcd;
364
365 ahcd = hcd_to_admhcd(hcd);
366 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
367 admhc_dma_disable(ahcd);
368 admhc_usb_reset(ahcd);
369 }
370
371 /*-------------------------------------------------------------------------*
372 * HC functions
373 *-------------------------------------------------------------------------*/
374
375 static void admhc_eds_cleanup(struct admhcd *ahcd)
376 {
377 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
378 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
379 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
380 }
381
382 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
383 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
384 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
385 }
386
387 if (ahcd->ed_tails[PIPE_CONTROL]) {
388 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
389 ahcd->ed_tails[PIPE_CONTROL] = NULL;
390 }
391
392 if (ahcd->ed_tails[PIPE_BULK]) {
393 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
394 ahcd->ed_tails[PIPE_BULK] = NULL;
395 }
396
397 ahcd->ed_head = NULL;
398 }
399
400 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
401
402 static int admhc_eds_init(struct admhcd *ahcd)
403 {
404 struct ed *ed;
405
406 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
407 if (!ed)
408 goto err;
409
410 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
411
412 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
413 if (!ed)
414 goto err;
415
416 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
417 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
418 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
419 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
420
421 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
422 if (!ed)
423 goto err;
424
425 ahcd->ed_tails[PIPE_CONTROL] = ed;
426 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
427 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
428 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
429
430 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
431 if (!ed)
432 goto err;
433
434 ahcd->ed_tails[PIPE_BULK] = ed;
435 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
436 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
437 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
438
439 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
440
441 #ifdef ADMHC_VERBOSE_DEBUG
442 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
443 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
444 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
445 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
446 #endif
447
448 return 0;
449
450 err:
451 admhc_eds_cleanup(ahcd);
452 return -ENOMEM;
453 }
454
455 /* init memory, and kick BIOS/SMM off */
456
457 static int admhc_init(struct admhcd *ahcd)
458 {
459 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
460 int ret;
461
462 admhc_disable(ahcd);
463 ahcd->regs = hcd->regs;
464
465 /* Disable HC interrupts */
466 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
467
468 /* Read the number of ports unless overridden */
469 if (ahcd->num_ports == 0)
470 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
471
472 ret = admhc_mem_init(ahcd);
473 if (ret)
474 goto err;
475
476 /* init dummy endpoints */
477 ret = admhc_eds_init(ahcd);
478 if (ret)
479 goto err;
480
481 create_debug_files(ahcd);
482
483 return 0;
484
485 err:
486 admhc_stop(hcd);
487 return ret;
488 }
489
490 /*-------------------------------------------------------------------------*/
491
492 /* Start an OHCI controller, set the BUS operational
493 * resets USB and controller
494 * enable interrupts
495 */
496 static int admhc_run(struct admhcd *ahcd)
497 {
498 u32 temp;
499 int first = ahcd->fminterval == 0;
500 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
501
502 admhc_disable(ahcd);
503
504 /* boot firmware should have set this up (5.1.1.3.1) */
505 if (first) {
506 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
507 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
508 if (ahcd->fminterval != FI)
509 admhc_dbg(ahcd, "fminterval delta %d\n",
510 ahcd->fminterval - FI);
511 ahcd->fminterval |=
512 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
513 /* also: power/overcurrent flags in rhdesc */
514 }
515
516 switch (ahcd->host_control & ADMHC_HC_BUSS) {
517 case ADMHC_BUSS_OPER:
518 temp = 0;
519 break;
520 case ADMHC_BUSS_SUSPEND:
521 /* FALLTHROUGH ? */
522 case ADMHC_BUSS_RESUME:
523 ahcd->host_control = ADMHC_BUSS_RESUME;
524 temp = 10 /* msec wait */;
525 break;
526 /* case ADMHC_BUSS_RESET: */
527 default:
528 ahcd->host_control = ADMHC_BUSS_RESET;
529 temp = 50 /* msec wait */;
530 break;
531 }
532 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
533
534 msleep(temp);
535 temp = admhc_read_rhdesc(ahcd);
536 if (!(temp & ADMHC_RH_NPS)) {
537 /* power down each port */
538 for (temp = 0; temp < ahcd->num_ports; temp++)
539 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
540 }
541
542 /* 2msec timelimit here means no irqs/preempt */
543 spin_lock_irq(&ahcd->lock);
544
545 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
546 temp = 30; /* ... allow extra time */
547 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
548 if (--temp == 0) {
549 spin_unlock_irq(&ahcd->lock);
550 admhc_err(ahcd, "USB HC reset timed out!\n");
551 return -1;
552 }
553 udelay (1);
554 }
555
556 /* enable HOST mode, before access any host specific register */
557 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
558
559 /* Tell the controller where the descriptor list is */
560 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
561
562 periodic_reinit(ahcd);
563
564 /* use rhsc irqs after khubd is fully initialized */
565 hcd->poll_rh = 1;
566 hcd->uses_new_polling = 1;
567
568 #if 0
569 /* wake on ConnectStatusChange, matching external hubs */
570 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
571 #else
572 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
573 #endif
574
575 /* Choose the interrupts we care about now, others later on demand */
576 admhc_intr_ack(ahcd, ~0);
577 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
578
579 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
580
581 /* start controller operations */
582 ahcd->host_control = ADMHC_BUSS_OPER;
583 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
584
585 temp = 20;
586 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
587 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
588 if (--temp == 0) {
589 spin_unlock_irq(&ahcd->lock);
590 admhc_err(ahcd, "unable to setup operational mode!\n");
591 return -1;
592 }
593 mdelay(1);
594 }
595
596 hcd->state = HC_STATE_RUNNING;
597 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
598
599 spin_unlock_irq(&ahcd->lock);
600
601 mdelay(ADMHC_POTPGT);
602
603 return 0;
604 }
605
606 /*-------------------------------------------------------------------------*/
607
608 /* an interrupt happens */
609
610 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
611 {
612 struct admhcd *ahcd = hcd_to_admhcd(hcd);
613 struct admhcd_regs __iomem *regs = ahcd->regs;
614 u32 ints;
615
616 ints = admhc_readl(ahcd, &regs->int_status);
617 if (!(ints & ADMHC_INTR_INTA))
618 /* no unmasked interrupt status is set */
619 return IRQ_NONE;
620
621 ints &= admhc_readl(ahcd, &regs->int_enable);
622 if (!ints)
623 return IRQ_NONE;
624
625 if (ints & ADMHC_INTR_FATI) {
626 admhc_disable(ahcd);
627 admhc_err(ahcd, "Fatal Error, controller disabled\n");
628 admhc_usb_reset(ahcd);
629 }
630
631 if (ints & ADMHC_INTR_BABI) {
632 admhc_disable(ahcd);
633 admhc_err(ahcd, "Babble Detected\n");
634 admhc_usb_reset(ahcd);
635 }
636
637 if (ints & ADMHC_INTR_INSM) {
638 admhc_vdbg(ahcd, "Root Hub Status Change\n");
639 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
640 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
641
642 /* NOTE: Vendors didn't always make the same implementation
643 * choices for RHSC. Many followed the spec; RHSC triggers
644 * on an edge, like setting and maybe clearing a port status
645 * change bit. With others it's level-triggered, active
646 * until khubd clears all the port status change bits. We'll
647 * always disable it here and rely on polling until khubd
648 * re-enables it.
649 */
650 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
651 usb_hcd_poll_rh_status(hcd);
652 } else if (ints & ADMHC_INTR_RESI) {
653 /* For connect and disconnect events, we expect the controller
654 * to turn on RHSC along with RD. But for remote wakeup events
655 * this might not happen.
656 */
657 admhc_vdbg(ahcd, "Resume Detect\n");
658 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
659 hcd->poll_rh = 1;
660 if (ahcd->autostop) {
661 admhc_rh_resume(ahcd);
662 } else
663 usb_hcd_resume_root_hub(hcd);
664 }
665
666 if (ints & ADMHC_INTR_TDC) {
667 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
668 if (HC_IS_RUNNING(hcd->state))
669 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
670 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
671 spin_lock(&ahcd->lock);
672 admhc_td_complete(ahcd);
673 spin_unlock(&ahcd->lock);
674 if (HC_IS_RUNNING(hcd->state))
675 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
676 }
677
678 if (ints & ADMHC_INTR_SO) {
679 /* could track INTR_SO to reduce available PCI/... bandwidth */
680 admhc_vdbg(ahcd, "Schedule Overrun\n");
681 }
682
683 if (ints & ADMHC_INTR_SOFI) {
684 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
685 /* handle any pending ED removes */
686 admhc_finish_unlinks(ahcd, admhc_frame_no(ahcd));
687 spin_lock(&ahcd->lock);
688 admhc_sof_refill(ahcd);
689 spin_unlock(&ahcd->lock);
690 }
691
692 if (HC_IS_RUNNING(hcd->state)) {
693 admhc_intr_ack(ahcd, ints);
694 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
695 }
696
697 return IRQ_HANDLED;
698 }
699
700 /*-------------------------------------------------------------------------*/
701
702 static void admhc_stop(struct usb_hcd *hcd)
703 {
704 struct admhcd *ahcd = hcd_to_admhcd(hcd);
705
706 admhc_dump(ahcd, 1);
707
708 flush_scheduled_work();
709
710 admhc_usb_reset(ahcd);
711 admhc_intr_disable(ahcd, ~0);
712
713 free_irq(hcd->irq, hcd);
714 hcd->irq = -1;
715
716 remove_debug_files(ahcd);
717 admhc_eds_cleanup(ahcd);
718 admhc_mem_cleanup(ahcd);
719 }
720
721 /*-------------------------------------------------------------------------*/
722
723 #ifdef CONFIG_MIPS_ADM5120
724 #include "adm5120-drv.c"
725 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
726 #endif
727
728 #if !defined(PLATFORM_DRIVER)
729 #error "missing bus glue for admhc-hcd"
730 #endif
731
732 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
733
734 static int __init admhc_hcd_mod_init(void)
735 {
736 int ret = 0;
737
738 if (usb_disabled())
739 return -ENODEV;
740
741 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
742 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
743 sizeof (struct ed), sizeof (struct td));
744
745 #ifdef PLATFORM_DRIVER
746 ret = platform_driver_register(&PLATFORM_DRIVER);
747 if (ret < 0)
748 goto error_platform;
749 #endif
750
751 return ret;
752
753 #ifdef PLATFORM_DRIVER
754 platform_driver_unregister(&PLATFORM_DRIVER);
755 error_platform:
756 #endif
757 return ret;
758 }
759 module_init(admhc_hcd_mod_init);
760
761 static void __exit admhc_hcd_mod_exit(void)
762 {
763 platform_driver_unregister(&PLATFORM_DRIVER);
764 }
765 module_exit(admhc_hcd_mod_exit);
766
767 MODULE_AUTHOR(DRIVER_AUTHOR);
768 MODULE_DESCRIPTION(DRIVER_INFO);
769 MODULE_LICENSE("GPL");
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