target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch

   1 --- a/arch/mips/lantiq/irq.c
   2 +++ b/arch/mips/lantiq/irq.c
   3 @@ -51,6 +51,7 @@
   4  #define ltq_eiu_w32(x, y)      ltq_w32((x), ltq_eiu_membase + (y))
   5  #define ltq_eiu_r32(x)         ltq_r32(ltq_eiu_membase + (x))
   6
   7 +#ifdef CONFIG_SOC_XWAY
   8  static unsigned short ltq_eiu_irq[MAX_EIU] = {
   9         LTQ_EIU_IR0,
  10         LTQ_EIU_IR1,
  11 @@ -59,6 +60,7 @@
  12         LTQ_EIU_IR4,
  13         LTQ_EIU_IR5,
  14  };
  15 +#endif
  16
  17  static struct resource ltq_icu_resource = {
  18         .name   = "icu",
  19 @@ -67,15 +69,19 @@
  20         .flags  = IORESOURCE_MEM,
  21  };
  22
  23 +#ifdef CONFIG_SOC_XWAY
  24  static struct resource ltq_eiu_resource = {
  25         .name   = "eiu",
  26         .start  = LTQ_EIU_BASE_ADDR,
  27         .end    = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
  28         .flags  = IORESOURCE_MEM,
  29  };
  30 +#endif
  31
  32  static void __iomem *ltq_icu_membase;
  33 +#ifdef CONFIG_SOC_XWAY
  34  static void __iomem *ltq_eiu_membase;
  35 +#endif
  36
  37  void ltq_disable_irq(struct irq_data *d)
  38  {
  39 @@ -120,6 +126,7 @@
  40         ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
  41  }
  42
  43 +#ifdef CONFIG_SOC_XWAY
  44  static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
  45  {
  46         int i;
  47 @@ -159,6 +166,7 @@
  48                 }
  49         }
  50  }
  51 +#endif
  52
  53  static struct irq_chip ltq_irq_type = {
  54         "icu",
  55 @@ -170,6 +178,7 @@
  56         .irq_mask_ack = ltq_mask_and_ack_irq,
  57  };
  58
  59 +#ifdef CONFIG_SOC_XWAY
  60  static struct irq_chip ltq_eiu_type = {
  61         "eiu",
  62         .irq_startup = ltq_startup_eiu_irq,
  63 @@ -181,6 +190,7 @@
  64         .irq_mask = ltq_disable_irq,
  65         .irq_mask_ack = ltq_mask_and_ack_irq,
  66  };
  67 +#endif
  68
  69  static void ltq_hw_irqdispatch(int module)
  70  {
  71 @@ -196,10 +206,12 @@
  72         irq = __fls(irq);
  73         do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
  74
  75 +#ifdef CONFIG_SOC_XWAY
  76         /* if this is a EBU irq, we need to ack it or get a deadlock */
  77         if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
  78                 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
  79                         LTQ_EBU_PCC_ISTAT);
  80 +#endif
  81  }
  82
  83  #define DEFINE_HWx_IRQDISPATCH(x)                                      \
  84 @@ -262,6 +274,7 @@
  85         if (!ltq_icu_membase)
  86                 panic("Failed to remap icu memory\n");
  87
  88 +#ifdef CONFIG_SOC_XWAY
  89         if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
  90                 panic("Failed to insert eiu memory\n");
  91
  92 @@ -273,6 +286,7 @@
  93                                 resource_size(&ltq_eiu_resource));
  94         if (!ltq_eiu_membase)
  95                 panic("Failed to remap eiu memory\n");
  96 +#endif
  97
  98         /* make sure all irqs are turned off by default */
  99         for (i = 0; i < 5; i++)
 100 @@ -298,6 +312,7 @@
 101
 102         for (i = INT_NUM_IRQ0;
 103                 i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 104 +#ifdef CONFIG_SOC_XWAY
 105                 if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
 106                         (i == LTQ_EIU_IR2))
 107                         irq_set_chip_and_handler(i, &ltq_eiu_type,
 108 @@ -308,6 +323,7 @@
 109                         irq_set_chip_and_handler(i, &ltq_eiu_type,
 110                                 handle_level_irq);
 111                 else
 112 +#endif
 113                         irq_set_chip_and_handler(i, &ltq_irq_type,
 114                                 handle_level_irq);
 115
 116 --- a/arch/mips/lantiq/clk.c
 117 +++ b/arch/mips/lantiq/clk.c
 118 @@ -46,6 +46,7 @@
 119         },
 120  };
 121
 122 +#ifdef CONFIG_SOC_XWAY
 123  static struct resource ltq_cgu_resource = {
 124         .name   = "cgu",
 125         .start  = LTQ_CGU_BASE_ADDR,
 126 @@ -55,6 +56,7 @@
 127
 128  /* remapped clock register range */
 129  void __iomem *ltq_cgu_membase;
 130 +#endif
 131
 132  void clk_init(void)
 133  {
 134 @@ -120,6 +122,7 @@
 135  {
 136         struct clk *clk;
 137
 138 +#ifdef CONFIG_SOC_XWAY
 139         if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
 140                 panic("Failed to insert cgu memory\n");
 141
 142 @@ -133,6 +136,7 @@
 143                 pr_err("Failed to remap cgu memory\n");
 144                 unreachable();
 145         }
 146 +#endif
 147         clk = clk_get(0, "cpu");
 148         mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
 149         write_c0_compare(read_c0_count());
 150 --- a/arch/mips/lantiq/early_printk.c
 151 +++ b/arch/mips/lantiq/early_printk.c
 152 @@ -13,7 +13,11 @@
 153  #include <lantiq_soc.h>
 154
 155  /* no ioremap possible at this early stage, lets use KSEG1 instead  */
 156 +#ifdef CONFIG_SOC_FALCON
 157 +#define LTQ_ASC_BASE   KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
 158 +#else
 159  #define LTQ_ASC_BASE   KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
 160 +#endif
 161  #define ASC_BUF                1024
 162  #define LTQ_ASC_FSTAT  ((u32 *)(LTQ_ASC_BASE + 0x0048))
 163  #define LTQ_ASC_TBUF   ((u32 *)(LTQ_ASC_BASE + 0x0020))