target/linux/ifxmips/files/arch/mips/ifxmips/ar9/irq.c

   1 #include <linux/init.h>
   2 #include <linux/sched.h>
   3 #include <linux/slab.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/kernel_stat.h>
   6 #include <linux/module.h>
   7
   8 #include <asm/bootinfo.h>
   9 #include <asm/irq.h>
  10 #include <asm/irq_cpu.h>
  11
  12 #include <ifxmips.h>
  13 #include <ifxmips_irq.h>
  14
  15 void
  16 ifxmips_disable_irq(unsigned int irq_nr)
  17 {
  18         int i;
  19         u32 *ier = IFXMIPS_ICU_IM0_IER;
  20
  21         irq_nr -= INT_NUM_IRQ0;
  22         for (i = 0; i <= 4; i++)
  23         {
  24                 if (irq_nr < INT_NUM_IM_OFFSET)
  25                 {
  26                         ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
  27                         return;
  28                 }
  29                 ier += IFXMIPS_ICU_OFFSET;
  30                 irq_nr -= INT_NUM_IM_OFFSET;
  31         }
  32 }
  33 EXPORT_SYMBOL(ifxmips_disable_irq);
  34
  35 void
  36 ifxmips_mask_and_ack_irq(unsigned int irq_nr)
  37 {
  38         int i;
  39         u32 *ier = IFXMIPS_ICU_IM0_IER;
  40         u32 *isr = IFXMIPS_ICU_IM0_ISR;
  41
  42         irq_nr -= INT_NUM_IRQ0;
  43         for (i = 0; i <= 4; i++)
  44         {
  45                 if (irq_nr < INT_NUM_IM_OFFSET)
  46                 {
  47                         ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
  48                         ifxmips_w32((1 << irq_nr), isr);
  49                         return;
  50                 }
  51                 ier += IFXMIPS_ICU_OFFSET;
  52                 isr += IFXMIPS_ICU_OFFSET;
  53                 irq_nr -= INT_NUM_IM_OFFSET;
  54         }
  55 }
  56 EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
  57
  58 void
  59 ifxmips_enable_irq(unsigned int irq_nr)
  60 {
  61         int i;
  62         u32 *ier = IFXMIPS_ICU_IM0_IER;
  63
  64         irq_nr -= INT_NUM_IRQ0;
  65         for (i = 0; i <= 4; i++)
  66         {
  67                 if (irq_nr < INT_NUM_IM_OFFSET)
  68                 {
  69                         ifxmips_w32(ifxmips_r32(ier) | (1 << irq_nr), ier);
  70                         return;
  71                 }
  72                 ier += IFXMIPS_ICU_OFFSET;
  73                 irq_nr -= INT_NUM_IM_OFFSET;
  74         }
  75 }
  76 EXPORT_SYMBOL(ifxmips_enable_irq);
  77
  78 static unsigned int
  79 ifxmips_startup_irq(unsigned int irq)
  80 {
  81         ifxmips_enable_irq(irq);
  82         return 0;
  83 }
  84
  85 static void
  86 ifxmips_end_irq(unsigned int irq)
  87 {
  88         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  89                 ifxmips_enable_irq(irq);
  90 }
  91
  92 static struct irq_chip
  93 ifxmips_irq_type = {
  94         "ifxmips",
  95         .startup = ifxmips_startup_irq,
  96         .enable = ifxmips_enable_irq,
  97         .disable = ifxmips_disable_irq,
  98         .unmask = ifxmips_enable_irq,
  99         .ack = ifxmips_end_irq,
 100         .mask = ifxmips_disable_irq,
 101         .mask_ack = ifxmips_mask_and_ack_irq,
 102         .end = ifxmips_end_irq,
 103 };
 104
 105 /* silicon bug causes only the msb set to 1 to be valid. all
 106    other bits might be bogus */
 107 static inline int
 108 ls1bit32(unsigned long x)
 109 {
 110         __asm__ (
 111                 ".set push \n"
 112                 ".set mips32 \n"
 113                 "clz %0, %1 \n"
 114                 ".set pop \n"
 115                 : "=r" (x)
 116                 : "r" (x));
 117         return 31 - x;
 118 }
 119
 120 static void
 121 ifxmips_hw_irqdispatch(int module)
 122 {
 123         u32 irq;
 124
 125         irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
 126         if (irq == 0)
 127                 return;
 128
 129         /* we need to do this due to a silicon bug */
 130         irq = ls1bit32(irq);
 131         do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 132
 133         if ((irq == 22) && (module == 0))
 134                 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
 135                         IFXMIPS_EBU_PCC_ISTAT);
 136 }
 137
 138 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
 139 #define DEFINE_HWx_IRQDISPATCH(x) \
 140 static void ifxmips_hw ## x ## _irqdispatch(void)\
 141 {\
 142         ifxmips_hw_irqdispatch(x); \
 143 }
 144 static void ifxmips_hw5_irqdispatch(void)
 145 {
 146         do_IRQ(MIPS_CPU_TIMER_IRQ);
 147 }
 148 DEFINE_HWx_IRQDISPATCH(0)
 149 DEFINE_HWx_IRQDISPATCH(1)
 150 DEFINE_HWx_IRQDISPATCH(2)
 151 DEFINE_HWx_IRQDISPATCH(3)
 152 DEFINE_HWx_IRQDISPATCH(4)
 153 /*DEFINE_HWx_IRQDISPATCH(5)*/
 154 #endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
 155
 156 asmlinkage void
 157 plat_irq_dispatch(void)
 158 {
 159         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 160         unsigned int i;
 161
 162         if (pending & CAUSEF_IP7)
 163         {
 164                 do_IRQ(MIPS_CPU_TIMER_IRQ);
 165                 goto out;
 166         } else {
 167                 for (i = 0; i < 5; i++)
 168                 {
 169                         if (pending & (CAUSEF_IP2 << i))
 170                         {
 171                                 ifxmips_hw_irqdispatch(i);
 172                                 goto out;
 173                         }
 174                 }
 175         }
 176         printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 177
 178 out:
 179         return;
 180 }
 181
 182 static struct irqaction
 183 cascade = {
 184         .handler = no_action,
 185         .flags = IRQF_DISABLED,
 186         .name = "cascade",
 187 };
 188
 189 void __init
 190 arch_init_irq(void)
 191 {
 192         int i;
 193
 194         for (i = 0; i < 5; i++)
 195                 ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
 196
 197         mips_cpu_irq_init();
 198
 199         for (i = 2; i <= 6; i++)
 200                 setup_irq(i, &cascade);
 201
 202 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
 203         if (cpu_has_vint) {
 204                 printk(KERN_INFO "Setting up vectored interrupts\n");
 205                 set_vi_handler(2, ifxmips_hw0_irqdispatch);
 206                 set_vi_handler(3, ifxmips_hw1_irqdispatch);
 207                 set_vi_handler(4, ifxmips_hw2_irqdispatch);
 208                 set_vi_handler(5, ifxmips_hw3_irqdispatch);
 209                 set_vi_handler(6, ifxmips_hw4_irqdispatch);
 210                 set_vi_handler(7, ifxmips_hw5_irqdispatch);
 211         }
 212 #endif
 213
 214         for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 215                 set_irq_chip_and_handler(i, &ifxmips_irq_type,
 216                         handle_level_irq);
 217
 218         #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
 219         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
 220                 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 221         #else
 222         set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
 223                 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 224         #endif
 225 }
 226
 227 void __cpuinit
 228 arch_fixup_c0_irqs(void)
 229 {
 230         /* FIXME: check for CPUID and only do fix for specific chips/versions */
 231         cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 232         cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 233 }