target/linux/ar7/patches-2.6.35/930-titan-platform.patch

   1 --- a/arch/mips/ar7/platform.c
   2 +++ b/arch/mips/ar7/platform.c
   3 @@ -154,6 +154,60 @@ static struct resource vlynq_high_res[]
   4         },
   5  };
   6
   7 +static struct resource vlynq_low_res_titan[] = {
   8 +       {
   9 +               .name = "regs",
  10 +               .flags = IORESOURCE_MEM,
  11 +               .start = TITAN_REGS_VLYNQ0,
  12 +               .end = TITAN_REGS_VLYNQ0 + 0xff,
  13 +       },
  14 +       {
  15 +               .name = "irq",
  16 +               .flags = IORESOURCE_IRQ,
  17 +               .start = 33,
  18 +               .end = 33,
  19 +       },
  20 +       {
  21 +               .name = "mem",
  22 +               .flags = IORESOURCE_MEM,
  23 +               .start = 0x0c000000,
  24 +               .end = 0x0fffffff,
  25 +       },
  26 +       {
  27 +               .name = "devirq",
  28 +               .flags = IORESOURCE_IRQ,
  29 +               .start = 80,
  30 +               .end = 111,
  31 +       },
  32 +};
  33 +
  34 +static struct resource vlynq_high_res_titan[] = {
  35 +       {
  36 +               .name = "regs",
  37 +               .flags = IORESOURCE_MEM,
  38 +               .start = TITAN_REGS_VLYNQ1,
  39 +               .end = TITAN_REGS_VLYNQ1 + 0xff,
  40 +       },
  41 +       {
  42 +               .name = "irq",
  43 +               .flags = IORESOURCE_IRQ,
  44 +               .start = 34,
  45 +               .end = 34,
  46 +       },
  47 +       {
  48 +               .name = "mem",
  49 +               .flags = IORESOURCE_MEM,
  50 +               .start = 0x40000000,
  51 +               .end = 0x43ffffff,
  52 +       },
  53 +       {
  54 +               .name = "devirq",
  55 +               .flags = IORESOURCE_IRQ,
  56 +               .start = 112,
  57 +               .end = 143,
  58 +       },
  59 +};
  60 +
  61  static struct plat_vlynq_data vlynq_low_data = {
  62         .ops = {
  63                 .on     = vlynq_on,
  64 @@ -192,6 +246,44 @@ static struct platform_device vlynq_high
  65         .num_resources  = ARRAY_SIZE(vlynq_high_res),
  66  };
  67
  68 +static struct plat_vlynq_data vlynq_low_data_titan = {
  69 +       .ops = {
  70 +               .on     = vlynq_on,
  71 +               .off    = vlynq_off,
  72 +       },
  73 +       .reset_bit      = 15,
  74 +       .gpio_bit       = 14,
  75 +};
  76 +
  77 +static struct plat_vlynq_data vlynq_high_data_titan = {
  78 +       .ops = {
  79 +               .on     = vlynq_on,
  80 +               .off    = vlynq_off,
  81 +       },
  82 +       .reset_bit      = 16,
  83 +       .gpio_bit       = 7,
  84 +};
  85 +
  86 +static struct platform_device vlynq_low_titan = {
  87 +       .id             = 0,
  88 +       .name           = "vlynq",
  89 +       .dev = {
  90 +               .platform_data = &vlynq_low_data_titan,
  91 +       },
  92 +       .resource       = vlynq_low_res_titan,
  93 +       .num_resources  = ARRAY_SIZE(vlynq_low_res_titan),
  94 +};
  95 +
  96 +static struct platform_device vlynq_high_titan = {
  97 +       .id             = 1,
  98 +       .name           = "vlynq",
  99 +       .dev = {
 100 +               .platform_data = &vlynq_high_data_titan,
 101 +       },
 102 +       .resource       = vlynq_high_res_titan,
 103 +       .num_resources  = ARRAY_SIZE(vlynq_high_res_titan),
 104 +};
 105 +
 106  /*****************************************************************************
 107   * Flash
 108   ****************************************************************************/
 109 @@ -248,6 +340,36 @@ static struct resource cpmac_high_res[]
 110         },
 111  };
 112
 113 +static struct resource cpmac_low_res_titan[] = {
 114 +       {
 115 +               .name = "regs",
 116 +               .flags = IORESOURCE_MEM,
 117 +               .start = TITAN_REGS_MAC0,
 118 +               .end = TITAN_REGS_MAC0 + 0x7ff,
 119 +       },
 120 +       {
 121 +               .name = "irq",
 122 +               .flags = IORESOURCE_IRQ,
 123 +               .start = 27,
 124 +               .end = 27,
 125 +       },
 126 +};
 127 +
 128 +static struct resource cpmac_high_res_titan[] = {
 129 +       {
 130 +               .name = "regs",
 131 +               .flags = IORESOURCE_MEM,
 132 +               .start = TITAN_REGS_MAC1,
 133 +               .end = TITAN_REGS_MAC1 + 0x7ff,
 134 +       },
 135 +       {
 136 +               .name = "irq",
 137 +               .flags = IORESOURCE_IRQ,
 138 +               .start = 41,
 139 +               .end = 41,
 140 +       },
 141 +};
 142 +
 143  static struct fixed_phy_status fixed_phy_status __initdata = {
 144         .link           = 1,
 145         .speed          = 100,
 146 @@ -292,6 +414,42 @@ static struct platform_device cpmac_high
 147         .num_resources  = ARRAY_SIZE(cpmac_high_res),
 148  };
 149
 150 +static struct plat_cpmac_data cpmac_low_data_titan = {
 151 +       .reset_bit = 17,
 152 +       .power_bit = 20,
 153 +       .phy_mask = 0x40000000,
 154 +};
 155 +
 156 +static struct plat_cpmac_data cpmac_high_data_titan = {
 157 +       .reset_bit = 21,
 158 +       .power_bit = 22,
 159 +       .phy_mask = 0x80000000,
 160 +};
 161 +
 162 +static struct platform_device cpmac_low_titan = {
 163 +       .id             = 0,
 164 +       .name           = "cpmac",
 165 +       .dev = {
 166 +               .dma_mask               = &cpmac_dma_mask,
 167 +               .coherent_dma_mask      = DMA_BIT_MASK(32),
 168 +               .platform_data          = &cpmac_low_data_titan,
 169 +       },
 170 +       .resource       = cpmac_low_res_titan,
 171 +       .num_resources  = ARRAY_SIZE(cpmac_low_res_titan),
 172 +};
 173 +
 174 +static struct platform_device cpmac_high_titan = {
 175 +       .id             = 1,
 176 +       .name           = "cpmac",
 177 +       .dev = {
 178 +               .dma_mask               = &cpmac_dma_mask,
 179 +               .coherent_dma_mask      = DMA_BIT_MASK(32),
 180 +               .platform_data          = &cpmac_high_data_titan,
 181 +       },
 182 +       .resource       = cpmac_high_res_titan,
 183 +       .num_resources  = ARRAY_SIZE(cpmac_high_res_titan),
 184 +};
 185 +
 186  static inline unsigned char char2hex(char h)
 187  {
 188         switch (h) {
 189 @@ -369,6 +527,11 @@ static struct gpio_led default_leds[] =
 190         },
 191  };
 192
 193 +static struct gpio_led titan_leds[] = {
 194 +       { .name = "status", .gpio = 8, .active_low = 1, },
 195 +       { .name = "wifi", .gpio = 13, .active_low = 1, },
 196 +};
 197 +
 198  static struct gpio_led dsl502t_leds[] = {
 199         {
 200                 .name                   = "status",
 201 @@ -507,6 +670,9 @@ static void __init detect_leds(void)
 202         } else if (strstr(prid, "DG834")) {
 203                 ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
 204                 ar7_led_data.leds = dg834g_leds;
 205 +       } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
 206 +               ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
 207 +               ar7_led_data.leds = titan_leds;
 208         }
 209  }
 210
 211 @@ -586,14 +752,18 @@ static int __init ar7_register_devices(v
 212         if (res)
 213                 pr_warning("unable to register physmap-flash: %d\n", res);
 214
 215 -       ar7_device_disable(vlynq_low_data.reset_bit);
 216 -       res = platform_device_register(&vlynq_low);
 217 +       ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit :
 218 +                                               vlynq_low_data.reset_bit);
 219 +       res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan :
 220 +                                                       &vlynq_low);
 221         if (res)
 222                 pr_warning("unable to register vlynq-low: %d\n", res);
 223
 224         if (ar7_has_high_vlynq()) {
 225 -               ar7_device_disable(vlynq_high_data.reset_bit);
 226 -               res = platform_device_register(&vlynq_high);
 227 +               ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit :
 228 +                                                       vlynq_high_data.reset_bit);
 229 +               res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan :
 230 +                                                               &vlynq_high);
 231                 if (res)
 232                         pr_warning("unable to register vlynq-high: %d\n", res);
 233         }
 234 --- a/arch/mips/ar7/gpio.c
 235 +++ b/arch/mips/ar7/gpio.c
 236 @@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpi
 237         return readl(gpio_in) & (1 << gpio);
 238  }
 239
 240 +static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
 241 +{
 242 +       void __iomem *gpio_in0 =
 243 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 244 +       void __iomem *gpio_in1 =
 245 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1);
 246 +
 247 +       return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
 248 +}
 249 +
 250  static void ar7_gpio_set_value(struct gpio_chip *chip,
 251                                 unsigned gpio, int value)
 252  {
 253 @@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gp
 254         writel(tmp, gpio_out);
 255  }
 256
 257 +static void titan_gpio_set_value(struct gpio_chip *chip,
 258 +                               unsigned gpio, int value)
 259 +{
 260 +       void __iomem *gpio_out0 =
 261 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0);
 262 +       void __iomem *gpio_out1 =
 263 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1);
 264 +       unsigned tmp;
 265 +
 266 +       tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
 267 +       if (value)
 268 +               tmp |= 1 << (gpio & 0x1f);
 269 +       writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
 270 +}
 271 +
 272  static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 273  {
 274         struct ar7_gpio_chip *gpch =
 275 @@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(stru
 276         return 0;
 277  }
 278
 279 +static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 280 +{
 281 +       void __iomem *gpio_dir0 =
 282 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
 283 +       void __iomem *gpio_dir1 =
 284 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
 285 +
 286 +       if (gpio >= TITAN_GPIO_MAX)
 287 +               return -EINVAL;
 288 +
 289 +       writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
 290 +                       gpio >> 5 ? gpio_dir1 : gpio_dir0);
 291 +       return 0;
 292 +}
 293 +
 294  static int ar7_gpio_direction_output(struct gpio_chip *chip,
 295                                         unsigned gpio, int value)
 296  {
 297 @@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(str
 298         return 0;
 299  }
 300
 301 +static int titan_gpio_direction_output(struct gpio_chip *chip,
 302 +                                       unsigned gpio, int value)
 303 +{
 304 +       void __iomem *gpio_dir0 =
 305 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
 306 +       void __iomem *gpio_dir1 =
 307 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
 308 +
 309 +       if (gpio >= TITAN_GPIO_MAX)
 310 +               return -EINVAL;
 311 +
 312 +       titan_gpio_set_value(chip, gpio, value);
 313 +       writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
 314 +               (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
 315 +
 316 +       return 0;
 317 +}
 318 +
 319  static struct ar7_gpio_chip ar7_gpio_chip = {
 320         .chip = {
 321                 .label                  = "ar7-gpio",
 322 @@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chi
 323         }
 324  };
 325
 326 -int ar7_gpio_enable(unsigned gpio)
 327 +static struct ar7_gpio_chip titan_gpio_chip = {
 328 +       .chip = {
 329 +               .label                  = "titan-gpio",
 330 +               .direction_input        = titan_gpio_direction_input,
 331 +               .direction_output       = titan_gpio_direction_output,
 332 +               .set                    = titan_gpio_set_value,
 333 +               .get                    = titan_gpio_get_value,
 334 +               .base                   = 0,
 335 +               .ngpio                  = TITAN_GPIO_MAX,
 336 +       }
 337 +};
 338 +
 339 +static inline int ar7_gpio_enable_ar7(unsigned gpio)
 340  {
 341         void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
 342
 343 @@ -95,9 +165,28 @@ int ar7_gpio_enable(unsigned gpio)
 344
 345         return 0;
 346  }
 347 +
 348 +static inline int ar7_gpio_enable_titan(unsigned gpio)
 349 +{
 350 +       void __iomem *gpio_en0 =
 351 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
 352 +       void __iomem *gpio_en1 =
 353 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
 354 +
 355 +       writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
 356 +               gpio >> 5 ? gpio_en1 : gpio_en0);
 357 +
 358 +       return 0;
 359 +}
 360 +
 361 +int ar7_gpio_enable(unsigned gpio)
 362 +{
 363 +       return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
 364 +                               ar7_gpio_enable_ar7(gpio);
 365 +}
 366  EXPORT_SYMBOL(ar7_gpio_enable);
 367
 368 -int ar7_gpio_disable(unsigned gpio)
 369 +static inline int ar7_gpio_disable_ar7(unsigned gpio)
 370  {
 371         void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
 372
 373 @@ -105,27 +194,57 @@ int ar7_gpio_disable(unsigned gpio)
 374
 375         return 0;
 376  }
 377 +
 378 +static inline int ar7_gpio_disable_titan(unsigned gpio)
 379 +{
 380 +       void __iomem *gpio_en0 =
 381 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
 382 +       void __iomem *gpio_en1 =
 383 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
 384 +
 385 +       writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
 386 +                gpio >> 5 ? gpio_en1 : gpio_en0);
 387 +
 388 +       return 0;
 389 +}
 390 +
 391 +int ar7_gpio_disable(unsigned gpio)
 392 +{
 393 +       return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
 394 +                               ar7_gpio_disable_ar7(gpio);
 395 +}
 396 +
 397  EXPORT_SYMBOL(ar7_gpio_disable);
 398
 399  static int __init ar7_gpio_init(void)
 400  {
 401         int ret;
 402
 403 -       ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
 404 +       if (!ar7_is_titan()) {
 405 +               ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
 406                                         AR7_REGS_GPIO + 0x10);
 407
 408 -       if (!ar7_gpio_chip.regs) {
 409 -               printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
 410 -               return -ENOMEM;
 411 -       }
 412 -
 413 -       ret = gpiochip_add(&ar7_gpio_chip.chip);
 414 -       if (ret) {
 415 -               printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
 416 -               return ret;
 417 +               if (!ar7_gpio_chip.regs) {
 418 +                       printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
 419 +                       return -ENOMEM;
 420 +               }
 421 +
 422 +               ret = gpiochip_add(&ar7_gpio_chip.chip);
 423 +               if (ret) {
 424 +                       printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
 425 +                       return ret;
 426 +               }
 427 +               printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
 428 +                                       ar7_gpio_chip.chip.ngpio);
 429 +       } else {
 430 +               ret = gpiochip_add(&titan_gpio_chip.chip);
 431 +               if (ret) {
 432 +                       printk(KERN_ERR "titan-gpio: failed to add gpiochip\n");
 433 +                       return ret;
 434 +               }
 435 +               printk(KERN_INFO "titan-gpio: registered %d GPIOs\n",
 436 +                                       titan_gpio_chip.chip.ngpio);
 437         }
 438 -       printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
 439 -                               ar7_gpio_chip.chip.ngpio);
 440         return ret;
 441  }
 442  arch_initcall(ar7_gpio_init);
 443 --- a/arch/mips/ar7/setup.c
 444 +++ b/arch/mips/ar7/setup.c
 445 @@ -23,6 +23,9 @@
 446  #include <asm/reboot.h>
 447  #include <asm/mach-ar7/ar7.h>
 448  #include <asm/mach-ar7/prom.h>
 449 +#include <asm/mach-ar7/gpio.h>
 450 +
 451 +static int titan_variant;
 452
 453  static void ar7_machine_restart(char *command)
 454  {
 455 @@ -56,6 +59,18 @@ const char *get_system_type(void)
 456                 return "TI AR7 (TNETD7200)";
 457         case AR7_CHIP_7300:
 458                 return "TI AR7 (TNETD7300)";
 459 +       case AR7_CHIP_TITAN:
 460 +               titan_variant = ar7_init_titan_variant();
 461 +               switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) {
 462 +               case TITAN_CHIP_1050:
 463 +                       return "TI AR7 (TNETV1050)";
 464 +               case TITAN_CHIP_1055:
 465 +                       return "TI AR7 (TNETV1055)";
 466 +               case TITAN_CHIP_1056:
 467 +                       return "TI AR7 (TNETV1056)";
 468 +               case TITAN_CHIP_1060:
 469 +                       return "TI AR7 (TNETV1060)";
 470 +               }
 471         default:
 472                 return "TI AR7 (unknown)";
 473         }
 474 --- a/arch/mips/include/asm/mach-ar7/ar7.h
 475 +++ b/arch/mips/include/asm/mach-ar7/ar7.h
 476 @@ -50,6 +50,11 @@
 477  #define UR8_REGS_WDT   (AR7_REGS_BASE + 0x0b00)
 478  #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
 479
 480 +#define TITAN_REGS_MAC0        (0x08640000)
 481 +#define TITAN_REGS_MAC1        (TITAN_REGS_MAC0 + 0x0800)
 482 +#define TITAN_REGS_VLYNQ0      (AR7_REGS_BASE + 0x1c00)
 483 +#define TITAN_REGS_VLYNQ1      (AR7_REGS_BASE + 0x1300)
 484 +
 485  #define AR7_RESET_PERIPHERAL   0x0
 486  #define AR7_RESET_SOFTWARE     0x4
 487  #define AR7_RESET_STATUS       0x8
 488 @@ -59,15 +64,30 @@
 489  #define AR7_RESET_BIT_MDIO     22
 490  #define AR7_RESET_BIT_EPHY     26
 491
 492 +#define TITAN_RESET_BIT_EPHY1  28
 493 +
 494  /* GPIO control registers */
 495  #define AR7_GPIO_INPUT 0x0
 496  #define AR7_GPIO_OUTPUT        0x4
 497  #define AR7_GPIO_DIR   0x8
 498  #define AR7_GPIO_ENABLE        0xc
 499 +#define TITAN_GPIO_INPUT_0     0x0
 500 +#define TITAN_GPIO_INPUT_1     0x4
 501 +#define TITAN_GPIO_OUTPUT_0    0x8
 502 +#define TITAN_GPIO_OUTPUT_1    0xc
 503 +#define TITAN_GPIO_DIR_0       0x10
 504 +#define TITAN_GPIO_DIR_1       0x14
 505 +#define TITAN_GPIO_ENBL_0      0x18
 506 +#define TITAN_GPIO_ENBL_1      0x1c
 507
 508  #define AR7_CHIP_7100  0x18
 509  #define AR7_CHIP_7200  0x2b
 510  #define AR7_CHIP_7300  0x05
 511 +#define AR7_CHIP_TITAN 0x07
 512 +#define TITAN_CHIP_1050        0x0f
 513 +#define TITAN_CHIP_1055        0x0e
 514 +#define TITAN_CHIP_1056        0x0d
 515 +#define TITAN_CHIP_1060        0x07
 516
 517  /* Interrupts */
 518  #define AR7_IRQ_UART0  15
 519 @@ -95,14 +115,22 @@ struct plat_dsl_data {
 520
 521  extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 522
 523 +static inline int ar7_is_titan(void)
 524 +{
 525 +       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
 526 +               AR7_CHIP_TITAN;
 527 +}
 528 +
 529  static inline u16 ar7_chip_id(void)
 530  {
 531 -       return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
 532 +       return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
 533 +               KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
 534  }
 535
 536  static inline u8 ar7_chip_rev(void)
 537  {
 538 -       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
 539 +       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
 540 +               0x14))) >> 16) & 0xff;
 541  }
 542
 543  struct clk {
 544 --- a/arch/mips/include/asm/mach-ar7/gpio.h
 545 +++ b/arch/mips/include/asm/mach-ar7/gpio.h
 546 @@ -20,9 +20,13 @@
 547  #define __AR7_GPIO_H__
 548
 549  #include <asm/mach-ar7/ar7.h>
 550 +#ifndef __AR7_TITAN_H__
 551 +#include <asm/mach-ar7/titan.h>
 552 +#endif
 553
 554  #define AR7_GPIO_MAX 32
 555 -#define NR_BUILTIN_GPIO AR7_GPIO_MAX
 556 +#define TITAN_GPIO_MAX 51
 557 +#define NR_BUILTIN_GPIO TITAN_GPIO_MAX
 558
 559  #define gpio_to_irq(gpio)      -1
 560
 561 @@ -35,6 +39,41 @@
 562  int ar7_gpio_enable(unsigned gpio);
 563  int ar7_gpio_disable(unsigned gpio);
 564
 565 +static inline int ar7_init_titan_variant(void)
 566 +{
 567 +       /*UINT32 new_val;*/
 568 +       unsigned new_val;
 569 +
 570 +       /* set GPIO 44 - 47 as input */
 571 +       /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */
 572 +       /*define titan_gpio_ctrl in titan.h*/
 573 +       titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN);
 574 +       titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN);
 575 +       titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN);
 576 +       titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN);
 577 +
 578 +       /* read GPIO to get Titan variant type */
 579 +       /*fix this*/
 580 +       titan_sysGpioInValue( &new_val, 1 );
 581 +
 582 +       new_val >>= 12;
 583 +       new_val &= 0x0f;
 584 +
 585 +       switch ( new_val )
 586 +       {
 587 +       case TITAN_CHIP_1050:
 588 +       case TITAN_CHIP_1055:
 589 +       case TITAN_CHIP_1056:
 590 +       case TITAN_CHIP_1060:
 591 +               return new_val;
 592 +
 593 +       default:
 594 +               break;
 595 +       }
 596 +       /* In case we get an invalid value, return the default Titan chip */
 597 +       return TITAN_CHIP_1050;
 598 +}
 599 +
 600  #include <asm-generic/gpio.h>
 601
 602  #endif
 603 --- /dev/null
 604 +++ b/arch/mips/include/asm/mach-ar7/titan.h
 605 @@ -0,0 +1,176 @@
 606 +/*
 607 + * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
 608 + *
 609 + * This program is free software; you can redistribute it and/or modify
 610 + * it under the terms of the GNU General Public License as published by
 611 + * the Free Software Foundation; either version 2 of the License, or
 612 + * (at your option) any later version.
 613 + *
 614 + * This program is distributed in the hope that it will be useful,
 615 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 616 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 617 + * GNU General Public License for more details.
 618 + *
 619 + * You should have received a copy of the GNU General Public License
 620 + * along with this program; if not, write to the Free Software
 621 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 622 + */
 623 +#ifndef __AR7_TITAN_H__
 624 +#define __AR7_TITAN_H__
 625 +
 626 +#include <asm/mach-ar7/gpio.h>
 627 +
 628 +typedef enum TITAN_GPIO_PIN_MODE_tag
 629 +{
 630 +    FUNCTIONAL_PIN = 0,
 631 +    GPIO_PIN = 1
 632 +} TITAN_GPIO_PIN_MODE_T;
 633 +
 634 +typedef enum TITAN_GPIO_PIN_DIRECTION_tag
 635 +{
 636 +    GPIO_OUTPUT_PIN = 0,
 637 +    GPIO_INPUT_PIN = 1
 638 +} TITAN_GPIO_PIN_DIRECTION_T;
 639 +
 640 +/**********************************************************************
 641 + *  GPIO Control
 642 + **********************************************************************/
 643 +
 644 +typedef struct
 645 +{
 646 +    int pinSelReg;
 647 +    int shift;
 648 +    int func;
 649 +
 650 +} GPIO_CFG;
 651 +
 652 +static GPIO_CFG gptable[]= {
 653 +                     /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
 654 +                     {4,24,1},
 655 +                     {4,26,1},
 656 +                     {4,28,1},
 657 +                     {4,30,1},
 658 +                     {5,6,1},
 659 +                     {5,8,1},
 660 +                     {5,10,1},
 661 +                     {5,12,1},
 662 +                     {7,14,3},
 663 +                     {7,16,3},
 664 +                     {7,18,3},
 665 +                     {7,20,3},
 666 +                     {7,22,3},
 667 +                     {7,26,3},
 668 +                     {7,28,3},
 669 +                     {7,30,3},
 670 +                      {8,0,3},
 671 +                     {8,2,3},
 672 +                     {8,4,3},
 673 +                     {8,10,3},
 674 +                     {8,14,3},
 675 +                     {8,16,3},
 676 +                     {8,18,3},
 677 +                     {8,20,3},
 678 +                     {9,8,3},
 679 +                     {9,10,3},
 680 +                     {9,12,3},
 681 +                     {9,14,3},
 682 +                     {9,18,3},
 683 +                     {9,20,3},
 684 +                     {9,24,3},
 685 +                     {9,26,3},
 686 +                     {9,28,3},
 687 +                     {9,30,3},
 688 +                     {10,0,3},
 689 +                     {10,2,3},
 690 +                     {10,8,3},
 691 +                     {10,10,3},
 692 +                     {10,12,3},
 693 +                     {10,14,3},
 694 +                     {13,12,3},
 695 +                     {13,14,3},
 696 +                     {13,16,3},
 697 +                     {13,18,3},
 698 +                     {13,24,3},
 699 +                     {13,26,3},
 700 +                     {13,28,3},
 701 +                     {13,30,3},
 702 +                     {14,2,3},
 703 +                     {14,6,3},
 704 +                     {14,8,3},
 705 +                     {14,12,3}
 706 +};
 707 +
 708 +typedef struct
 709 +{
 710 +    volatile unsigned int reg[21];
 711 +}
 712 +PIN_SEL_REG_ARRAY_T;
 713 +
 714 +typedef struct
 715 +{
 716 +    unsigned int data_in [2];
 717 +    unsigned int data_out[2];
 718 +    unsigned int dir[2];
 719 +    unsigned int enable[2];
 720 +
 721 +} TITAN_GPIO_CONTROL_T;
 722 +
 723 +#define AVALANCHE_PIN_SEL_BASE        0xA861160C /*replace with KSEG1ADDR()*/
 724 +
 725 +static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
 726 +                        TITAN_GPIO_PIN_DIRECTION_T pin_direction)
 727 +{
 728 +    int reg_index = 0;
 729 +    int mux_status;
 730 +    GPIO_CFG  gpio_cfg;
 731 +    volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
 732 +    volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 733 +
 734 +    if (gpio_pin > 51 )
 735 +        return(-1);
 736 +
 737 +    gpio_cfg = gptable[gpio_pin];
 738 +    mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
 739 +    if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
 740 +    {
 741 +        return(-1); /* Pin have been configured for non GPIO funcs. */
 742 +    }
 743 +
 744 +    /* Set the pin to be used as GPIO. */
 745 +    pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
 746 +
 747 +    /* Check whether gpio refers to the first GPIO reg or second. */
 748 +    if(gpio_pin > 31)
 749 +    {
 750 +       reg_index = 1;
 751 +       gpio_pin -= 32;
 752 +    }
 753 +
 754 +    if(pin_mode)
 755 +        gpio_cntl->enable[reg_index] |=  (1 << gpio_pin); /* Enable */
 756 +    else
 757 +       gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
 758 +
 759 +    if(pin_direction)
 760 +        gpio_cntl->dir[reg_index] |=  (1 << gpio_pin); /* Input */
 761 +    else
 762 +       gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
 763 +
 764 +    return(0);
 765 +
 766 +}/* end of function titan_gpio_ctrl */
 767 +
 768 +static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
 769 +{
 770 +    volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 771 +
 772 +    if(reg_index > 1)
 773 +       return (-1);
 774 +
 775 +    *in_val = gpio_cntl->data_in[reg_index];
 776 +
 777 +    return (0);
 778 +}
 779 +
 780 +
 781 +#endif