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[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_AT_CTRL 0x5c
61 #define AR7240_AT_CTRL_ARP_EN BIT(20)
62
63 #define AR7240_REG_TAG_PRIORITY 0x70
64
65 #define AR7240_REG_SERVICE_TAG 0x74
66 #define AR7240_SERVICE_TAG_M BITM(16)
67
68 #define AR7240_REG_CPU_PORT 0x78
69 #define AR7240_MIRROR_PORT_S 4
70 #define AR7240_CPU_PORT_EN BIT(8)
71
72 #define AR7240_REG_MIB_FUNCTION0 0x80
73 #define AR7240_MIB_TIMER_M BITM(16)
74 #define AR7240_MIB_AT_HALF_EN BIT(16)
75 #define AR7240_MIB_BUSY BIT(17)
76 #define AR7240_MIB_FUNC_S 24
77 #define AR7240_MIB_FUNC_NO_OP 0x0
78 #define AR7240_MIB_FUNC_FLUSH 0x1
79 #define AR7240_MIB_FUNC_CAPTURE 0x3
80
81 #define AR7240_REG_MDIO_CTRL 0x98
82 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
83 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
84 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
85 #define AR7240_MDIO_CTRL_CMD_WRITE 0
86 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
87 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
88 #define AR7240_MDIO_CTRL_BUSY BIT(31)
89
90 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
91
92 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
93 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
94 #define AR7240_PORT_STATUS_SPEED_10 0
95 #define AR7240_PORT_STATUS_SPEED_100 1
96 #define AR7240_PORT_STATUS_SPEED_1000 2
97 #define AR7240_PORT_STATUS_TXMAC BIT(2)
98 #define AR7240_PORT_STATUS_RXMAC BIT(3)
99 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
100 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
101 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
102 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
103 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
104 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
105
106 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
107 #define AR7240_PORT_CTRL_STATE_M BITM(3)
108 #define AR7240_PORT_CTRL_STATE_DISABLED 0
109 #define AR7240_PORT_CTRL_STATE_BLOCK 1
110 #define AR7240_PORT_CTRL_STATE_LISTEN 2
111 #define AR7240_PORT_CTRL_STATE_LEARN 3
112 #define AR7240_PORT_CTRL_STATE_FORWARD 4
113 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
114 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
115 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
116 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
117 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
118 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
119 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
120 #define AR7240_PORT_CTRL_HEADER BIT(11)
121 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
122 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
123 #define AR7240_PORT_CTRL_LEARN BIT(14)
124 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
125 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
126 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
127
128 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
129
130 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
131 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
132 #define AR7240_PORT_VLAN_MODE_S 30
133 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
134 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
135 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
136 #define AR7240_PORT_VLAN_MODE_SECURE 3
137
138
139 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
140
141 #define AR7240_STATS_RXBROAD 0x00
142 #define AR7240_STATS_RXPAUSE 0x04
143 #define AR7240_STATS_RXMULTI 0x08
144 #define AR7240_STATS_RXFCSERR 0x0c
145 #define AR7240_STATS_RXALIGNERR 0x10
146 #define AR7240_STATS_RXRUNT 0x14
147 #define AR7240_STATS_RXFRAGMENT 0x18
148 #define AR7240_STATS_RX64BYTE 0x1c
149 #define AR7240_STATS_RX128BYTE 0x20
150 #define AR7240_STATS_RX256BYTE 0x24
151 #define AR7240_STATS_RX512BYTE 0x28
152 #define AR7240_STATS_RX1024BYTE 0x2c
153 #define AR7240_STATS_RX1518BYTE 0x30
154 #define AR7240_STATS_RXMAXBYTE 0x34
155 #define AR7240_STATS_RXTOOLONG 0x38
156 #define AR7240_STATS_RXGOODBYTE 0x3c
157 #define AR7240_STATS_RXBADBYTE 0x44
158 #define AR7240_STATS_RXOVERFLOW 0x4c
159 #define AR7240_STATS_FILTERED 0x50
160 #define AR7240_STATS_TXBROAD 0x54
161 #define AR7240_STATS_TXPAUSE 0x58
162 #define AR7240_STATS_TXMULTI 0x5c
163 #define AR7240_STATS_TXUNDERRUN 0x60
164 #define AR7240_STATS_TX64BYTE 0x64
165 #define AR7240_STATS_TX128BYTE 0x68
166 #define AR7240_STATS_TX256BYTE 0x6c
167 #define AR7240_STATS_TX512BYTE 0x70
168 #define AR7240_STATS_TX1024BYTE 0x74
169 #define AR7240_STATS_TX1518BYTE 0x78
170 #define AR7240_STATS_TXMAXBYTE 0x7c
171 #define AR7240_STATS_TXOVERSIZE 0x80
172 #define AR7240_STATS_TXBYTE 0x84
173 #define AR7240_STATS_TXCOLLISION 0x8c
174 #define AR7240_STATS_TXABORTCOL 0x90
175 #define AR7240_STATS_TXMULTICOL 0x94
176 #define AR7240_STATS_TXSINGLECOL 0x98
177 #define AR7240_STATS_TXEXCDEFER 0x9c
178 #define AR7240_STATS_TXDEFER 0xa0
179 #define AR7240_STATS_TXLATECOL 0xa4
180
181 #define AR7240_PORT_CPU 0
182 #define AR7240_NUM_PORTS 6
183 #define AR7240_NUM_PHYS 5
184
185 #define AR7240_PHY_ID1 0x004d
186 #define AR7240_PHY_ID2 0xd041
187
188 #define AR7240_PORT_MASK(_port) BIT((_port))
189 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
190 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
191
192 #define AR7240_MAX_VLANS 16
193
194 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
195
196 struct ar7240sw {
197 struct mii_bus *mii_bus;
198 struct switch_dev swdev;
199 bool vlan;
200 u16 vlan_id[AR7240_MAX_VLANS];
201 u8 vlan_table[AR7240_MAX_VLANS];
202 u8 vlan_tagged;
203 u16 pvid[AR7240_NUM_PORTS];
204 };
205
206 struct ar7240sw_hw_stat {
207 char string[ETH_GSTRING_LEN];
208 int sizeof_stat;
209 int reg;
210 };
211
212 static DEFINE_MUTEX(reg_mutex);
213
214 static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
215 {
216 as->mii_bus = mii;
217 }
218
219 static inline u16 mk_phy_addr(u32 reg)
220 {
221 return 0x17 & ((reg >> 4) | 0x10);
222 }
223
224 static inline u16 mk_phy_reg(u32 reg)
225 {
226 return (reg << 1) & 0x1e;
227 }
228
229 static inline u16 mk_high_addr(u32 reg)
230 {
231 return (reg >> 7) & 0x1ff;
232 }
233
234 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
235 {
236 unsigned long flags;
237 u16 phy_addr;
238 u16 phy_reg;
239 u32 hi, lo;
240
241 reg = (reg & 0xfffffffc) >> 2;
242 phy_addr = mk_phy_addr(reg);
243 phy_reg = mk_phy_reg(reg);
244
245 local_irq_save(flags);
246 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
247 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
248 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
249 local_irq_restore(flags);
250
251 return (hi << 16) | lo;
252 }
253
254 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
255 {
256 unsigned long flags;
257 u16 phy_addr;
258 u16 phy_reg;
259
260 reg = (reg & 0xfffffffc) >> 2;
261 phy_addr = mk_phy_addr(reg);
262 phy_reg = mk_phy_reg(reg);
263
264 local_irq_save(flags);
265 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
266 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
267 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
268 local_irq_restore(flags);
269 }
270
271 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
272 {
273 u32 ret;
274
275 mutex_lock(&reg_mutex);
276 ret = __ar7240sw_reg_read(mii, reg_addr);
277 mutex_unlock(&reg_mutex);
278
279 return ret;
280 }
281
282 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
283 {
284 mutex_lock(&reg_mutex);
285 __ar7240sw_reg_write(mii, reg_addr, reg_val);
286 mutex_unlock(&reg_mutex);
287 }
288
289 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
290 {
291 u32 t;
292
293 mutex_lock(&reg_mutex);
294 t = __ar7240sw_reg_read(mii, reg);
295 t &= ~mask;
296 t |= val;
297 __ar7240sw_reg_write(mii, reg, t);
298 mutex_unlock(&reg_mutex);
299
300 return t;
301 }
302
303 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
304 {
305 u32 t;
306
307 mutex_lock(&reg_mutex);
308 t = __ar7240sw_reg_read(mii, reg);
309 t |= val;
310 __ar7240sw_reg_write(mii, reg, t);
311 mutex_unlock(&reg_mutex);
312 }
313
314 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
315 unsigned timeout)
316 {
317 int i;
318
319 for (i = 0; i < timeout; i++) {
320 u32 t;
321
322 t = __ar7240sw_reg_read(mii, reg);
323 if ((t & mask) == val)
324 return 0;
325
326 msleep(1);
327 }
328
329 return -ETIMEDOUT;
330 }
331
332 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
333 unsigned timeout)
334 {
335 int ret;
336
337 mutex_lock(&reg_mutex);
338 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
339 mutex_unlock(&reg_mutex);
340 return ret;
341 }
342
343 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
344 unsigned reg_addr)
345 {
346 u32 t, val = 0xffff;
347 int err;
348
349 if (phy_addr >= AR7240_NUM_PHYS)
350 return 0xffff;
351
352 mutex_lock(&reg_mutex);
353 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
354 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
355 AR7240_MDIO_CTRL_MASTER_EN |
356 AR7240_MDIO_CTRL_BUSY |
357 AR7240_MDIO_CTRL_CMD_READ;
358
359 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
360 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
361 AR7240_MDIO_CTRL_BUSY, 0, 5);
362 if (!err)
363 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
364 mutex_unlock(&reg_mutex);
365
366 return val & AR7240_MDIO_CTRL_DATA_M;
367 }
368
369 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
370 unsigned reg_addr, u16 reg_val)
371 {
372 u32 t;
373 int ret;
374
375 if (phy_addr >= AR7240_NUM_PHYS)
376 return -EINVAL;
377
378 mutex_lock(&reg_mutex);
379 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
380 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
381 AR7240_MDIO_CTRL_MASTER_EN |
382 AR7240_MDIO_CTRL_BUSY |
383 AR7240_MDIO_CTRL_CMD_WRITE |
384 reg_val;
385
386 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
387 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
388 AR7240_MDIO_CTRL_BUSY, 0, 5);
389 mutex_unlock(&reg_mutex);
390
391 return ret;
392 }
393
394 static int ar7240sw_capture_stats(struct ar7240sw *as)
395 {
396 struct mii_bus *mii = as->mii_bus;
397 int ret;
398
399 /* Capture the hardware statistics for all ports */
400 ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
401 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
402
403 /* Wait for the capturing to complete. */
404 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
405 AR7240_MIB_BUSY, 0, 10);
406 return ret;
407 }
408
409 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
410 {
411 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
412 AR7240_PORT_CTRL_STATE_DISABLED);
413 }
414
415 static int ar7240sw_reset(struct ar7240sw *as)
416 {
417 struct mii_bus *mii = as->mii_bus;
418 int ret;
419 int i;
420
421 /* Set all ports to disabled state. */
422 for (i = 0; i < AR7240_NUM_PORTS; i++)
423 ar7240sw_disable_port(as, i);
424
425 /* Wait for transmit queues to drain. */
426 msleep(2);
427
428 /* Reset the switch. */
429 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
430 AR7240_MASK_CTRL_SOFT_RESET);
431
432 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
433 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
434 return ret;
435 }
436
437 static void ar7240sw_setup(struct ar7240sw *as)
438 {
439 struct mii_bus *mii = as->mii_bus;
440
441 /* Enable CPU port, and disable mirror port */
442 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
443 AR7240_CPU_PORT_EN |
444 (15 << AR7240_MIRROR_PORT_S));
445
446 /* Setup TAG priority mapping */
447 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
448
449 /* Enable ARP frame acknowledge */
450 ar7240sw_reg_set(mii, AR7240_REG_AT_CTRL, AR7240_AT_CTRL_ARP_EN);
451
452 /* Enable Broadcast frames transmitted to the CPU */
453 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
454 AR7240_FLOOD_MASK_BROAD_TO_CPU);
455
456 /* setup MTU */
457 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
458 1536);
459
460 /* setup Service TAG */
461 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
462 }
463
464 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
465 {
466 struct mii_bus *mii = as->mii_bus;
467 u32 ctrl;
468 u32 dest_ports;
469 u32 vlan;
470
471 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
472 AR7240_PORT_CTRL_SINGLE_VLAN;
473
474 if (port == AR7240_PORT_CPU) {
475 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
476 AR7240_PORT_STATUS_SPEED_1000 |
477 AR7240_PORT_STATUS_TXFLOW |
478 AR7240_PORT_STATUS_RXFLOW |
479 AR7240_PORT_STATUS_TXMAC |
480 AR7240_PORT_STATUS_RXMAC |
481 AR7240_PORT_STATUS_DUPLEX);
482 } else {
483 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
484 AR7240_PORT_STATUS_LINK_AUTO);
485 }
486
487 /* Set the default VID for this port */
488 if (as->vlan) {
489 vlan = as->vlan_id[as->pvid[port]];
490 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
491 AR7240_PORT_VLAN_MODE_S;
492 } else {
493 vlan = port;
494 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
495 AR7240_PORT_VLAN_MODE_S;
496 }
497
498 if (as->vlan && (as->vlan_tagged & BIT(port))) {
499 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
500 AR7240_PORT_CTRL_VLAN_MODE_S;
501 } else {
502 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
503 AR7240_PORT_CTRL_VLAN_MODE_S;
504 }
505
506 if (!portmask) {
507 if (port == AR7240_PORT_CPU)
508 portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
509 else
510 portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
511 }
512
513 /* allow the port to talk to all other ports, but exclude its
514 * own ID to prevent frames from being reflected back to the
515 * port that they came from */
516 dest_ports = AR7240_PORT_MASK_BUT(port);
517
518 /* set default VID and and destination ports for this VLAN */
519 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
520
521 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
522 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
523 }
524
525 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
526 {
527 struct mii_bus *mii = as->mii_bus;
528 u32 t;
529
530 t = (addr[4] << 8) | addr[5];
531 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
532
533 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
534 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
535
536 return 0;
537 }
538
539 static int
540 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
541 struct switch_val *val)
542 {
543 struct ar7240sw *as = sw_to_ar7240(dev);
544 as->vlan_id[val->port_vlan] = val->value.i;
545 return 0;
546 }
547
548 static int
549 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
550 struct switch_val *val)
551 {
552 struct ar7240sw *as = sw_to_ar7240(dev);
553 val->value.i = as->vlan_id[val->port_vlan];
554 return 0;
555 }
556
557 static int
558 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
559 {
560 struct ar7240sw *as = sw_to_ar7240(dev);
561
562 /* make sure no invalid PVIDs get set */
563
564 if (vlan >= dev->vlans)
565 return -EINVAL;
566
567 as->pvid[port] = vlan;
568 return 0;
569 }
570
571 static int
572 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
573 {
574 struct ar7240sw *as = sw_to_ar7240(dev);
575 *vlan = as->pvid[port];
576 return 0;
577 }
578
579 static int
580 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
581 {
582 struct ar7240sw *as = sw_to_ar7240(dev);
583 u8 ports = as->vlan_table[val->port_vlan];
584 int i;
585
586 val->len = 0;
587 for (i = 0; i < AR7240_NUM_PORTS; i++) {
588 struct switch_port *p;
589
590 if (!(ports & (1 << i)))
591 continue;
592
593 p = &val->value.ports[val->len++];
594 p->id = i;
595 if (as->vlan_tagged & (1 << i))
596 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
597 else
598 p->flags = 0;
599 }
600 return 0;
601 }
602
603 static int
604 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
605 {
606 struct ar7240sw *as = sw_to_ar7240(dev);
607 u8 *vt = &as->vlan_table[val->port_vlan];
608 int i, j;
609
610 *vt = 0;
611 for (i = 0; i < val->len; i++) {
612 struct switch_port *p = &val->value.ports[i];
613
614 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
615 as->vlan_tagged |= (1 << p->id);
616 else {
617 as->vlan_tagged &= ~(1 << p->id);
618 as->pvid[p->id] = val->port_vlan;
619
620 /* make sure that an untagged port does not
621 * appear in other vlans */
622 for (j = 0; j < AR7240_MAX_VLANS; j++) {
623 if (j == val->port_vlan)
624 continue;
625 as->vlan_table[j] &= ~(1 << p->id);
626 }
627 }
628
629 *vt |= 1 << p->id;
630 }
631 return 0;
632 }
633
634 static int
635 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
636 struct switch_val *val)
637 {
638 struct ar7240sw *as = sw_to_ar7240(dev);
639 as->vlan = !!val->value.i;
640 return 0;
641 }
642
643 static int
644 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
645 struct switch_val *val)
646 {
647 struct ar7240sw *as = sw_to_ar7240(dev);
648 val->value.i = as->vlan;
649 return 0;
650 }
651
652
653 static void
654 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
655 {
656 struct mii_bus *mii = as->mii_bus;
657
658 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
659 return;
660
661 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
662 val &= AR7240_VTUDATA_MEMBER;
663 val |= AR7240_VTUDATA_VALID;
664 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
665 }
666 op |= AR7240_VTU_ACTIVE;
667 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
668 }
669
670 static int
671 ar7240_hw_apply(struct switch_dev *dev)
672 {
673 struct ar7240sw *as = sw_to_ar7240(dev);
674 u8 portmask[AR7240_NUM_PORTS];
675 int i, j;
676
677 /* flush all vlan translation unit entries */
678 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
679
680 memset(portmask, 0, sizeof(portmask));
681 if (as->vlan) {
682 /* calculate the port destination masks and load vlans
683 * into the vlan translation unit */
684 for (j = 0; j < AR7240_MAX_VLANS; j++) {
685 u8 vp = as->vlan_table[j];
686
687 if (!vp)
688 continue;
689
690 for (i = 0; i < AR7240_NUM_PORTS; i++) {
691 u8 mask = (1 << i);
692 if (vp & mask)
693 portmask[i] |= vp & ~mask;
694 }
695
696 ar7240_vtu_op(as,
697 AR7240_VTU_OP_LOAD |
698 (as->vlan_id[j] << AR7240_VTU_VID_S),
699 as->vlan_table[j]);
700 }
701 } else {
702 /* vlan disabled:
703 * isolate all ports, but connect them to the cpu port */
704 for (i = 0; i < AR7240_NUM_PORTS; i++) {
705 if (i == AR7240_PORT_CPU)
706 continue;
707
708 portmask[i] = 1 << AR7240_PORT_CPU;
709 portmask[AR7240_PORT_CPU] |= (1 << i);
710 }
711 }
712
713 /* update the port destination mask registers and tag settings */
714 for (i = 0; i < AR7240_NUM_PORTS; i++)
715 ar7240sw_setup_port(as, i, portmask[i]);
716
717 return 0;
718 }
719
720 static int
721 ar7240_reset_switch(struct switch_dev *dev)
722 {
723 struct ar7240sw *as = sw_to_ar7240(dev);
724 ar7240sw_reset(as);
725 return 0;
726 }
727
728 static struct switch_attr ar7240_globals[] = {
729 {
730 .type = SWITCH_TYPE_INT,
731 .name = "enable_vlan",
732 .description = "Enable VLAN mode",
733 .set = ar7240_set_vlan,
734 .get = ar7240_get_vlan,
735 .max = 1
736 },
737 };
738
739 static struct switch_attr ar7240_port[] = {
740 };
741
742 static struct switch_attr ar7240_vlan[] = {
743 {
744 .type = SWITCH_TYPE_INT,
745 .name = "vid",
746 .description = "VLAN ID",
747 .set = ar7240_set_vid,
748 .get = ar7240_get_vid,
749 .max = 4094,
750 },
751 };
752
753 static const struct switch_dev_ops ar7240_ops = {
754 .attr_global = {
755 .attr = ar7240_globals,
756 .n_attr = ARRAY_SIZE(ar7240_globals),
757 },
758 .attr_port = {
759 .attr = ar7240_port,
760 .n_attr = ARRAY_SIZE(ar7240_port),
761 },
762 .attr_vlan = {
763 .attr = ar7240_vlan,
764 .n_attr = ARRAY_SIZE(ar7240_vlan),
765 },
766 .get_port_pvid = ar7240_get_pvid,
767 .set_port_pvid = ar7240_set_pvid,
768 .get_vlan_ports = ar7240_get_ports,
769 .set_vlan_ports = ar7240_set_ports,
770 .apply_config = ar7240_hw_apply,
771 .reset_switch = ar7240_reset_switch,
772 };
773
774 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
775 {
776 struct mii_bus *mii = ag->mii_bus;
777 struct ar7240sw *as;
778 struct switch_dev *swdev;
779 u32 ctrl;
780 u16 phy_id1;
781 u16 phy_id2;
782 u8 ver;
783 int i;
784
785 as = kzalloc(sizeof(*as), GFP_KERNEL);
786 if (!as)
787 return NULL;
788
789 ar7240sw_init(as, mii);
790
791 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
792
793 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
794 if (ver != 1) {
795 pr_err("%s: unsupported chip, ctrl=%08x\n",
796 ag->dev->name, ctrl);
797 return NULL;
798 }
799
800 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
801 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
802 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
803 pr_err("%s: unknown phy id '%04x:%04x'\n",
804 ag->dev->name, phy_id1, phy_id2);
805 return NULL;
806 }
807
808 swdev = &as->swdev;
809 swdev->name = "AR7240 built-in switch";
810 swdev->ports = AR7240_NUM_PORTS;
811 swdev->cpu_port = AR7240_PORT_CPU;
812 swdev->vlans = AR7240_MAX_VLANS;
813 swdev->ops = &ar7240_ops;
814
815 if (register_switch(&as->swdev, ag->dev) < 0) {
816 kfree(as);
817 return NULL;
818 }
819
820 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
821
822 /* initialize defaults */
823 for (i = 0; i < AR7240_MAX_VLANS; i++)
824 as->vlan_id[i] = i;
825
826 as->vlan_table[0] = AR7240_PORT_MASK_ALL;
827
828 return as;
829 }
830
831 void ag71xx_ar7240_start(struct ag71xx *ag)
832 {
833 struct ar7240sw *as = ag->phy_priv;
834
835 ar7240sw_reset(as);
836 ar7240sw_setup(as);
837
838 ag->speed = SPEED_1000;
839 ag->link = 1;
840 ag->duplex = 1;
841
842 ar7240_set_addr(as, ag->dev->dev_addr);
843 ar7240_hw_apply(&as->swdev);
844 }
845
846 void ag71xx_ar7240_stop(struct ag71xx *ag)
847 {
848 }
849
850 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
851 {
852 struct ar7240sw *as;
853
854 as = ar7240_probe(ag);
855 if (!as)
856 return -ENODEV;
857
858 ag->phy_priv = as;
859 ar7240sw_reset(as);
860
861 return 0;
862 }
863
864 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
865 {
866 struct ar7240sw *as = ag->phy_priv;
867
868 if (!as)
869 return;
870
871 unregister_switch(&as->swdev);
872 kfree(as);
873 ag->phy_priv = NULL;
874 }
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