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[atheros] Implement a preliminary combined image format.
[openwrt.git] / target / linux / pxa / patches-2.6.21 / 036-270-usb-gadget-udc.patch
1 --- a/drivers/usb/gadget/Kconfig
2 +++ b/drivers/usb/gadget/Kconfig
3 @@ -129,6 +129,28 @@ config USB_PXA2XX_SMALL
4 default y if USB_ETH
5 default y if USB_G_SERIAL
6
7 +config USB_GADGET_PXA27X
8 + boolean "PXA 27x"
9 + depends on ARCH_PXA && PXA27x
10 + help
11 + Intel's PXA 27x series XScale ARM-5TE processors include
12 + an integrated full speed USB 1.1 device controller.
13 +
14 + Say "y" to link the driver statically, or "m" to build a
15 + dynamically linked module called "pxa27x_udc" and force all
16 + gadget drivers to also be dynamically linked.
17 +
18 +config USB_PXA27X
19 + tristate
20 + depends on USB_GADGET_PXA27X
21 + default USB_GADGET
22 + select USB_GADGET_SELECTED
23 +
24 +config USB_PXA27X_DMA
25 + bool # "Use DMA support"
26 + depends on USB_GADGET_PXA27X
27 + default n
28 +
29 config USB_GADGET_GOKU
30 boolean "Toshiba TC86C001 'Goku-S'"
31 depends on PCI
32 --- a/drivers/usb/gadget/Makefile
33 +++ b/drivers/usb/gadget/Makefile
34 @@ -7,6 +7,7 @@ obj-$(CONFIG_USB_PXA2XX) += pxa2xx_udc.o
35 obj-$(CONFIG_USB_GOKU) += goku_udc.o
36 obj-$(CONFIG_USB_OMAP) += omap_udc.o
37 obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
38 +obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o
39 obj-$(CONFIG_USB_AT91) += at91_udc.o
40 obj-$(CONFIG_USB_GADGET_GUMSTIX) += gumstix_gadget.o
41
42 --- /dev/null
43 +++ b/drivers/usb/gadget/pxa27x_udc.c
44 @@ -0,0 +1,2352 @@
45 +/*
46 + * linux/drivers/usb/gadget/pxa27x_udc.c
47 + * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
48 + *
49 + * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
50 + * Copyright (C) 2003 Robert Schwebel, Pengutronix
51 + * Copyright (C) 2003 Benedikt Spranger, Pengutronix
52 + * Copyright (C) 2003 David Brownell
53 + * Copyright (C) 2003 Joshua Wise
54 + * Copyright (C) 2004 Intel Corporation
55 + * Copyright (C) 2005 SDG Systems, LLC (Aric Blumer)
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License as published by
59 + * the Free Software Foundation; either version 2 of the License, or
60 + * (at your option) any later version.
61 + *
62 + * This program is distributed in the hope that it will be useful,
63 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
64 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
65 + * GNU General Public License for more details.
66 + *
67 + * You should have received a copy of the GNU General Public License
68 + * along with this program; if not, write to the Free Software
69 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
70 + *
71 + */
72 +
73 +#undef DEBUG
74 + // #define DEBUG 1
75 + //#define VERBOSE DBG_VERBOSE
76 +
77 +#include <linux/module.h>
78 +#include <linux/kernel.h>
79 +#include <linux/ioport.h>
80 +#include <linux/types.h>
81 +#include <linux/version.h>
82 +#include <linux/errno.h>
83 +#include <linux/delay.h>
84 +#include <linux/sched.h>
85 +#include <linux/slab.h>
86 +#include <linux/init.h>
87 +#include <linux/timer.h>
88 +#include <linux/list.h>
89 +#include <linux/interrupt.h>
90 +#include <linux/proc_fs.h>
91 +#include <linux/mm.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/dma-mapping.h>
94 +#include <linux/irq.h>
95 +
96 +#include <asm/byteorder.h>
97 +#include <asm/dma.h>
98 +#include <asm/io.h>
99 +#include <asm/system.h>
100 +#include <asm/mach-types.h>
101 +#include <asm/unaligned.h>
102 +#include <asm/hardware.h>
103 +#include <asm/mach/irq.h>
104 +#include <asm/arch/pxa-regs.h>
105 +
106 +#include <linux/usb/ch9.h>
107 +#include <linux/usb_gadget.h>
108 +
109 +#include <asm/arch/udc.h>
110 +
111 +
112 +/*
113 + * This driver handles the USB Device Controller (UDC) in Intel's PXA 27777777x
114 + * series processors.
115 + * Such controller drivers work with a gadget driver. The gadget driver
116 + * returns descriptors, implements configuration and data protocols used
117 + * by the host to interact with this device, and allocates endpoints to
118 + * the different protocol interfaces. The controller driver virtualizes
119 + * usb hardware so that the gadget drivers will be more portable.
120 + *
121 + * This UDC hardware wants to implement a bit too much USB protocol, so
122 + * it constrains the sorts of USB configuration change events that work.
123 + * The errata for these chips are misleading; some "fixed" bugs from
124 + * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
125 + */
126 +
127 +#define DRIVER_VERSION "21-Jul-2005"
128 +#define DRIVER_DESC "PXA 27x USB Device Controller driver"
129 +
130 +
131 +static const char driver_name [] = "pxa27x_udc";
132 +
133 +static const char ep0name [] = "ep0";
134 +
135 +
136 +#define USE_DMA
137 +//#define DISABLE_TEST_MODE
138 +
139 +#ifdef CONFIG_PROC_FS
140 +#define UDC_PROC_FILE
141 +#endif
142 +
143 +#include "pxa27x_udc.h"
144 +
145 +#if 0
146 +#ifdef CONFIG_EMBEDDED
147 +/* few strings, and little code to use them */
148 +#undef DEBUG
149 +#undef UDC_PROC_FILE
150 +#endif
151 +#endif
152 +
153 +#ifdef USE_DMA
154 +static int use_dma = 1;
155 +module_param(use_dma, bool, 0);
156 +MODULE_PARM_DESC (use_dma, "true to use dma");
157 +
158 +static void dma_nodesc_handler (int dmach, void *_ep);
159 +static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req);
160 +
161 +#define DMASTR " (dma support)"
162 +
163 +#else /* !USE_DMA */
164 +#define DMASTR " (pio only)"
165 +#endif
166 +
167 +#ifdef CONFIG_USB_PXA27X_SMALL
168 +#define SIZE_STR " (small)"
169 +#else
170 +#define SIZE_STR ""
171 +#endif
172 +
173 +#ifdef DISABLE_TEST_MODE
174 +/* (mode == 0) == no undocumented chip tweaks
175 + * (mode & 1) == double buffer bulk IN
176 + * (mode & 2) == double buffer bulk OUT
177 + * ... so mode = 3 (or 7, 15, etc) does it for both
178 + */
179 +static ushort fifo_mode = 0;
180 +module_param(fifo_mode, ushort, 0);
181 +MODULE_PARM_DESC (fifo_mode, "pxa27x udc fifo mode");
182 +#endif
183 +
184 +#define UDCISR0_IR0 0x3
185 +#define UDCISR_INT_MASK (UDC_INT_FIFOERROR | UDC_INT_PACKETCMP)
186 +#define UDCICR_INT_MASK UDCISR_INT_MASK
187 +
188 +#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME)
189 +/* ---------------------------------------------------------------------------
190 + * endpoint related parts of the api to the usb controller hardware,
191 + * used by gadget driver; and the inner talker-to-hardware core.
192 + * ---------------------------------------------------------------------------
193 + */
194 +
195 +static void pxa27x_ep_fifo_flush (struct usb_ep *ep);
196 +static void nuke (struct pxa27x_ep *, int status);
197 +
198 +static void pio_irq_enable(int ep_num)
199 +{
200 + if (ep_num < 16)
201 + UDCICR0 |= 3 << (ep_num * 2);
202 + else {
203 + ep_num -= 16;
204 + UDCICR1 |= 3 << (ep_num * 2);
205 + }
206 +}
207 +
208 +static void pio_irq_disable(int ep_num)
209 +{
210 + ep_num &= 0xf;
211 + if (ep_num < 16)
212 + UDCICR0 &= ~(3 << (ep_num * 2));
213 + else {
214 + ep_num -= 16;
215 + UDCICR1 &= ~(3 << (ep_num * 2));
216 + }
217 +}
218 +
219 +/* The UDCCR reg contains mask and interrupt status bits,
220 + * so using '|=' isn't safe as it may ack an interrupt.
221 + */
222 +#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE)
223 +
224 +static inline void udc_set_mask_UDCCR(int mask)
225 +{
226 + UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
227 +}
228 +
229 +static inline void udc_clear_mask_UDCCR(int mask)
230 +{
231 + UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
232 +}
233 +
234 +static inline void udc_ack_int_UDCCR(int mask)
235 +{
236 + /* udccr contains the bits we dont want to change */
237 + __u32 udccr = UDCCR & UDCCR_MASK_BITS;
238 +
239 + UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
240 +}
241 +
242 +/*
243 + * endpoint enable/disable
244 + *
245 + * we need to verify the descriptors used to enable endpoints. since pxa27x
246 + * endpoint configurations are fixed, and are pretty much always enabled,
247 + * there's not a lot to manage here.
248 + *
249 + * because pxa27x can't selectively initialize bulk (or interrupt) endpoints,
250 + * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
251 + * for a single interface (with only the default altsetting) and for gadget
252 + * drivers that don't halt endpoints (not reset by set_interface). that also
253 + * means that if you use ISO, you must violate the USB spec rule that all
254 + * iso endpoints must be in non-default altsettings.
255 + */
256 +static int pxa27x_ep_enable (struct usb_ep *_ep,
257 + const struct usb_endpoint_descriptor *desc)
258 +{
259 + struct pxa27x_ep *ep;
260 + struct pxa27x_udc *dev;
261 +
262 + ep = container_of (_ep, struct pxa27x_ep, ep);
263 + if (!_ep || !desc || _ep->name == ep0name
264 + || desc->bDescriptorType != USB_DT_ENDPOINT
265 + || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
266 + DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
267 + return -EINVAL;
268 + }
269 +
270 + /* xfer types must match, except that interrupt ~= bulk */
271 + if( ep->ep_type != USB_ENDPOINT_XFER_BULK
272 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
273 + DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
274 + return -EINVAL;
275 + }
276 +
277 + /* hardware _could_ do smaller, but driver doesn't */
278 + if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
279 + && le16_to_cpu (desc->wMaxPacketSize)
280 + != BULK_FIFO_SIZE)
281 + || !desc->wMaxPacketSize) {
282 + DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
283 + return -ERANGE;
284 + }
285 +
286 + dev = ep->dev;
287 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
288 + DMSG("%s, bogus device state\n", __FUNCTION__);
289 + return -ESHUTDOWN;
290 + }
291 +
292 + ep->desc = desc;
293 + ep->dma = -1;
294 + ep->stopped = 0;
295 + ep->pio_irqs = ep->dma_irqs = 0;
296 + ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
297 +
298 + /* flush fifo (mostly for OUT buffers) */
299 + pxa27x_ep_fifo_flush (_ep);
300 +
301 + /* ... reset halt state too, if we could ... */
302 +
303 +#ifdef USE_DMA
304 + /* for (some) bulk and ISO endpoints, try to get a DMA channel and
305 + * bind it to the endpoint. otherwise use PIO.
306 + */
307 + DMSG("%s: called attributes=%d\n", __FUNCTION__, ep->ep_type);
308 + switch (ep->ep_type) {
309 + case USB_ENDPOINT_XFER_ISOC:
310 + if (le16_to_cpu(desc->wMaxPacketSize) % 32)
311 + break;
312 + // fall through
313 + case USB_ENDPOINT_XFER_BULK:
314 + if (!use_dma || !ep->reg_drcmr)
315 + break;
316 + ep->dma = pxa_request_dma ((char *)_ep->name,
317 + (le16_to_cpu (desc->wMaxPacketSize) > 64)
318 + ? DMA_PRIO_MEDIUM /* some iso */
319 + : DMA_PRIO_LOW,
320 + dma_nodesc_handler, ep);
321 + if (ep->dma >= 0) {
322 + *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
323 + DMSG("%s using dma%d\n", _ep->name, ep->dma);
324 + }
325 + default:
326 + break;
327 + }
328 +#endif
329 + DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
330 + return 0;
331 +}
332 +
333 +static int pxa27x_ep_disable (struct usb_ep *_ep)
334 +{
335 + struct pxa27x_ep *ep;
336 +
337 + ep = container_of (_ep, struct pxa27x_ep, ep);
338 + if (!_ep || !ep->desc) {
339 + DMSG("%s, %s not enabled\n", __FUNCTION__,
340 + _ep ? ep->ep.name : NULL);
341 + return -EINVAL;
342 + }
343 + nuke (ep, -ESHUTDOWN);
344 +
345 +#ifdef USE_DMA
346 + if (ep->dma >= 0) {
347 + *ep->reg_drcmr = 0;
348 + pxa_free_dma (ep->dma);
349 + ep->dma = -1;
350 + }
351 +#endif
352 +
353 + /* flush fifo (mostly for IN buffers) */
354 + pxa27x_ep_fifo_flush (_ep);
355 +
356 + ep->desc = 0;
357 + ep->stopped = 1;
358 +
359 + DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
360 + return 0;
361 +}
362 +
363 +/*-------------------------------------------------------------------------*/
364 +
365 +/* for the pxa27x, these can just wrap kmalloc/kfree. gadget drivers
366 + * must still pass correctly initialized endpoints, since other controller
367 + * drivers may care about how it's currently set up (dma issues etc).
368 + */
369 +
370 +/*
371 + * pxa27x_ep_alloc_request - allocate a request data structure
372 + */
373 +static struct usb_request *
374 +pxa27x_ep_alloc_request (struct usb_ep *_ep, unsigned gfp_flags)
375 +{
376 + struct pxa27x_request *req;
377 +
378 + req = kmalloc (sizeof *req, gfp_flags);
379 + if (!req)
380 + return 0;
381 +
382 + memset (req, 0, sizeof *req);
383 + INIT_LIST_HEAD (&req->queue);
384 + return &req->req;
385 +}
386 +
387 +
388 +/*
389 + * pxa27x_ep_free_request - deallocate a request data structure
390 + */
391 +static void
392 +pxa27x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
393 +{
394 + struct pxa27x_request *req;
395 +
396 + req = container_of(_req, struct pxa27x_request, req);
397 + WARN_ON (!list_empty (&req->queue));
398 + kfree(req);
399 +}
400 +
401 +
402 +/* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
403 + * no device-affinity and the heap works perfectly well for i/o buffers.
404 + * It wastes much less memory than dma_alloc_coherent() would, and even
405 + * prevents cacheline (32 bytes wide) sharing problems.
406 + */
407 +static void *
408 +pxa27x_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
409 + dma_addr_t *dma, unsigned gfp_flags)
410 +{
411 + char *retval;
412 +
413 + retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
414 + if (retval)
415 + *dma = virt_to_bus (retval);
416 + return retval;
417 +}
418 +
419 +static void
420 +pxa27x_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
421 + unsigned bytes)
422 +{
423 + kfree (buf);
424 +}
425 +
426 +/*-------------------------------------------------------------------------*/
427 +
428 +/*
429 + * done - retire a request; caller blocked irqs
430 + */
431 +static void done(struct pxa27x_ep *ep, struct pxa27x_request *req, int status)
432 +{
433 + list_del_init(&req->queue);
434 + if (likely (req->req.status == -EINPROGRESS))
435 + req->req.status = status;
436 + else
437 + status = req->req.status;
438 +
439 + if (status && status != -ESHUTDOWN)
440 + DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
441 + ep->ep.name, &req->req, status,
442 + req->req.actual, req->req.length);
443 +
444 + /* don't modify queue heads during completion callback */
445 + req->req.complete(&ep->ep, &req->req);
446 +}
447 +
448 +
449 +static inline void ep0_idle (struct pxa27x_udc *dev)
450 +{
451 + dev->ep0state = EP0_IDLE;
452 + LED_EP0_OFF;
453 +}
454 +
455 +static int
456 +write_packet(volatile u32 *uddr, struct pxa27x_request *req, unsigned max)
457 +{
458 + u32 *buf;
459 + int length, count, remain;
460 +
461 + buf = (u32*)(req->req.buf + req->req.actual);
462 + prefetch(buf);
463 +
464 + /* how big will this packet be? */
465 + length = min(req->req.length - req->req.actual, max);
466 + req->req.actual += length;
467 +
468 + remain = length & 0x3;
469 + count = length & ~(0x3);
470 +
471 + while (likely(count)) {
472 + *uddr = *buf++;
473 + count -= 4;
474 + }
475 +
476 + if (remain) {
477 + volatile u8* reg=(u8*)uddr;
478 + char *rd =(u8*)buf;
479 +
480 + while (remain--) {
481 + *reg=*rd++;
482 + }
483 + }
484 +
485 + return length;
486 +}
487 +
488 +/*
489 + * write to an IN endpoint fifo, as many packets as possible.
490 + * irqs will use this to write the rest later.
491 + * caller guarantees at least one packet buffer is ready (or a zlp).
492 + */
493 +static int
494 +write_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
495 +{
496 + unsigned max;
497 +
498 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
499 + do {
500 + int count;
501 + int is_last, is_short;
502 +
503 + count = write_packet(ep->reg_udcdr, req, max);
504 +
505 + /* last packet is usually short (or a zlp) */
506 + if (unlikely (count != max))
507 + is_last = is_short = 1;
508 + else {
509 + if (likely(req->req.length != req->req.actual)
510 + || req->req.zero)
511 + is_last = 0;
512 + else
513 + is_last = 1;
514 + /* interrupt/iso maxpacket may not fill the fifo */
515 + is_short = unlikely (max < ep->fifo_size);
516 + }
517 +
518 + DMSG("wrote %s count:%d bytes%s%s %d left %p\n",
519 + ep->ep.name, count,
520 + is_last ? "/L" : "", is_short ? "/S" : "",
521 + req->req.length - req->req.actual, &req->req);
522 +
523 + /* let loose that packet. maybe try writing another one,
524 + * double buffering might work. TSP, TPC, and TFS
525 + * bit values are the same for all normal IN endpoints.
526 + */
527 + *ep->reg_udccsr = UDCCSR_PC;
528 + if (is_short)
529 + *ep->reg_udccsr = UDCCSR_SP;
530 +
531 + /* requests complete when all IN data is in the FIFO */
532 + if (is_last) {
533 + done (ep, req, 0);
534 + if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
535 + pio_irq_disable (ep->ep_num);
536 +#ifdef USE_DMA
537 + /* unaligned data and zlps couldn't use dma */
538 + if (unlikely(!list_empty(&ep->queue))) {
539 + req = list_entry(ep->queue.next,
540 + struct pxa27x_request, queue);
541 + kick_dma(ep,req);
542 + return 0;
543 + }
544 +#endif
545 + }
546 + return 1;
547 + }
548 +
549 + // TODO experiment: how robust can fifo mode tweaking be?
550 + // double buffering is off in the default fifo mode, which
551 + // prevents TFS from being set here.
552 +
553 + } while (*ep->reg_udccsr & UDCCSR_FS);
554 + return 0;
555 +}
556 +
557 +/* caller asserts req->pending (ep0 irq status nyet cleared); starts
558 + * ep0 data stage. these chips want very simple state transitions.
559 + */
560 +static inline
561 +void ep0start(struct pxa27x_udc *dev, u32 flags, const char *tag)
562 +{
563 + UDCCSR0 = flags|UDCCSR0_SA|UDCCSR0_OPC;
564 + UDCISR0 = UDCICR_INT(0, UDC_INT_FIFOERROR | UDC_INT_PACKETCMP);
565 + dev->req_pending = 0;
566 + DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
567 + __FUNCTION__, tag, UDCCSR0, flags);
568 +}
569 +
570 +static int
571 +write_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
572 +{
573 + unsigned count;
574 + int is_short;
575 +
576 + count = write_packet(&UDCDR0, req, EP0_FIFO_SIZE);
577 + ep->dev->stats.write.bytes += count;
578 +
579 + /* last packet "must be" short (or a zlp) */
580 + is_short = (count != EP0_FIFO_SIZE);
581 +
582 + DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
583 + req->req.length - req->req.actual, &req->req);
584 +
585 + if (unlikely (is_short)) {
586 + if (ep->dev->req_pending)
587 + ep0start(ep->dev, UDCCSR0_IPR, "short IN");
588 + else
589 + UDCCSR0 = UDCCSR0_IPR;
590 +
591 + count = req->req.length;
592 + done (ep, req, 0);
593 + ep0_idle(ep->dev);
594 +#if 0
595 + /* This seems to get rid of lost status irqs in some cases:
596 + * host responds quickly, or next request involves config
597 + * change automagic, or should have been hidden, or ...
598 + *
599 + * FIXME get rid of all udelays possible...
600 + */
601 + if (count >= EP0_FIFO_SIZE) {
602 + count = 100;
603 + do {
604 + if ((UDCCSR0 & UDCCSR0_OPC) != 0) {
605 + /* clear OPC, generate ack */
606 + UDCCSR0 = UDCCSR0_OPC;
607 + break;
608 + }
609 + count--;
610 + udelay(1);
611 + } while (count);
612 + }
613 +#endif
614 + } else if (ep->dev->req_pending)
615 + ep0start(ep->dev, 0, "IN");
616 + return is_short;
617 +}
618 +
619 +
620 +/*
621 + * read_fifo - unload packet(s) from the fifo we use for usb OUT
622 + * transfers and put them into the request. caller should have made
623 + * sure there's at least one packet ready.
624 + *
625 + * returns true if the request completed because of short packet or the
626 + * request buffer having filled (and maybe overran till end-of-packet).
627 + */
628 +static int
629 +read_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
630 +{
631 + for (;;) {
632 + u32 *buf;
633 + int bufferspace, count, is_short;
634 +
635 + /* make sure there's a packet in the FIFO.*/
636 + if (unlikely ((*ep->reg_udccsr & UDCCSR_PC) == 0))
637 + break;
638 + buf =(u32*) (req->req.buf + req->req.actual);
639 + prefetchw(buf);
640 + bufferspace = req->req.length - req->req.actual;
641 +
642 + /* read all bytes from this packet */
643 + if (likely (*ep->reg_udccsr & UDCCSR_BNE)) {
644 + count = 0x3ff & *ep->reg_udcbcr;
645 + req->req.actual += min (count, bufferspace);
646 + } else /* zlp */
647 + count = 0;
648 +
649 + is_short = (count < ep->ep.maxpacket);
650 + DMSG("read %s udccsr:%02x, count:%d bytes%s req %p %d/%d\n",
651 + ep->ep.name, *ep->reg_udccsr, count,
652 + is_short ? "/S" : "",
653 + &req->req, req->req.actual, req->req.length);
654 +
655 +// dump_regs(ep->ep_num );
656 + count = min(count, bufferspace);
657 + while (likely (count > 0)) {
658 + *buf++ = *ep->reg_udcdr;
659 + count -= 4;
660 + }
661 + DMSG("Buf:0x%p\n", req->req.buf);
662 +
663 + *ep->reg_udccsr = UDCCSR_PC;
664 + /* RPC/RSP/RNE could now reflect the other packet buffer */
665 +
666 + /* completion */
667 + if (is_short || req->req.actual == req->req.length) {
668 + done (ep, req, 0);
669 + if (list_empty(&ep->queue))
670 + pio_irq_disable (ep->ep_num);
671 + return 1;
672 + }
673 +
674 + /* finished that packet. the next one may be waiting... */
675 + }
676 + return 0;
677 +}
678 +
679 +/*
680 + * special ep0 version of the above. no UBCR0 or double buffering; status
681 + * handshaking is magic. most device protocols don't need control-OUT.
682 + * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
683 + * protocols do use them.
684 + */
685 +static int
686 +read_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
687 +{
688 + u32 *buf, word;
689 + unsigned bufferspace;
690 +
691 + buf = (u32*) (req->req.buf + req->req.actual);
692 + bufferspace = req->req.length - req->req.actual;
693 +
694 + while (UDCCSR0 & UDCCSR0_RNE) {
695 + word = UDCDR0;
696 +
697 + if (unlikely (bufferspace == 0)) {
698 + /* this happens when the driver's buffer
699 + * is smaller than what the host sent.
700 + * discard the extra data.
701 + */
702 + if (req->req.status != -EOVERFLOW)
703 + DMSG("%s overflow\n", ep->ep.name);
704 + req->req.status = -EOVERFLOW;
705 + } else {
706 + *buf++ = word;
707 + req->req.actual += 4;
708 + bufferspace -= 4;
709 + }
710 + }
711 +
712 + UDCCSR0 = UDCCSR0_OPC ;
713 +
714 + /* completion */
715 + if (req->req.actual >= req->req.length)
716 + return 1;
717 +
718 + /* finished that packet. the next one may be waiting... */
719 + return 0;
720 +}
721 +
722 +#ifdef USE_DMA
723 +
724 +#define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
725 +static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req)
726 +{
727 + u32 dcmd = 0;
728 + u32 len = req->req.length;
729 + u32 buf = req->req.dma;
730 + u32 fifo = io_v2p ((u32)ep->reg_udcdr);
731 +
732 + buf += req->req.actual;
733 + len -= req->req.actual;
734 + ep->dma_con = 0;
735 +
736 + DMSG("%s: req:0x%p length:%d, actual:%d dma:%d\n",
737 + __FUNCTION__, &req->req, req->req.length,
738 + req->req.actual,ep->dma);
739 +
740 + /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
741 + DCSR(ep->dma) = DCSR_NODESC;
742 + if (buf & 0x3)
743 + DALGN |= 1 << ep->dma;
744 + else
745 + DALGN &= ~(1 << ep->dma);
746 +
747 + if (ep->dir_in) {
748 + DSADR(ep->dma) = buf;
749 + DTADR(ep->dma) = fifo;
750 + if (len > MAX_IN_DMA) {
751 + len= MAX_IN_DMA;
752 + ep->dma_con =1 ;
753 + } else if (len >= ep->ep.maxpacket) {
754 + if ((ep->dma_con = (len % ep->ep.maxpacket) != 0))
755 + len = ep->ep.maxpacket;
756 + }
757 + dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN
758 + | DCMD_FLOWTRG | DCMD_INCSRCADDR;
759 + } else {
760 + DSADR(ep->dma) = fifo;
761 + DTADR(ep->dma) = buf;
762 + dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN
763 + | DCMD_FLOWSRC | DCMD_INCTRGADDR;
764 + }
765 + *ep->reg_udccsr = UDCCSR_DME;
766 + DCMD(ep->dma) = dcmd;
767 + DCSR(ep->dma) = DCSR_NODESC | DCSR_EORIRQEN \
768 + | ((ep->dir_in) ? DCSR_STOPIRQEN : 0);
769 + *ep->reg_drcmr = ep->dma | DRCMR_MAPVLD;
770 + DCSR(ep->dma) |= DCSR_RUN;
771 +}
772 +
773 +static void cancel_dma(struct pxa27x_ep *ep)
774 +{
775 + struct pxa27x_request *req;
776 + u32 tmp;
777 +
778 + if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
779 + return;
780 +
781 + DMSG("hehe dma:%d,dcsr:0x%x\n", ep->dma, DCSR(ep->dma));
782 + DCSR(ep->dma) = 0;
783 + while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
784 + cpu_relax();
785 +
786 + req = list_entry(ep->queue.next, struct pxa27x_request, queue);
787 + tmp = DCMD(ep->dma) & DCMD_LENGTH;
788 + req->req.actual = req->req.length - tmp;
789 +
790 + /* the last tx packet may be incomplete, so flush the fifo.
791 + * FIXME correct req.actual if we can
792 + */
793 + *ep->reg_udccsr = UDCCSR_FEF;
794 +}
795 +
796 +static void dma_nodesc_handler(int dmach, void *_ep)
797 +{
798 + struct pxa27x_ep *ep = _ep;
799 + struct pxa27x_request *req, *req_next;
800 + u32 dcsr, tmp, completed;
801 +
802 + local_irq_disable();
803 +
804 + req = list_entry(ep->queue.next, struct pxa27x_request, queue);
805 +
806 + DMSG("%s, buf:0x%p\n",__FUNCTION__, req->req.buf);
807 +
808 + ep->dma_irqs++;
809 + ep->dev->stats.irqs++;
810 + HEX_DISPLAY(ep->dev->stats.irqs);
811 +
812 + completed = 0;
813 +
814 + dcsr = DCSR(dmach);
815 + DCSR(ep->dma) &= ~DCSR_RUN;
816 +
817 + if (dcsr & DCSR_BUSERR) {
818 + DCSR(dmach) = DCSR_BUSERR;
819 + printk(KERN_ERR " Buss Error\n");
820 + req->req.status = -EIO;
821 + completed = 1;
822 + } else if (dcsr & DCSR_ENDINTR) {
823 + DCSR(dmach) = DCSR_ENDINTR;
824 + if (ep->dir_in) {
825 + tmp = req->req.length - req->req.actual;
826 + /* Last packet is a short one*/
827 + if ( tmp < ep->ep.maxpacket) {
828 + int count = 0;
829 +
830 + *ep->reg_udccsr = UDCCSR_SP | \
831 + (*ep->reg_udccsr & UDCCSR_MASK);
832 + /*Wait for packet out */
833 + while( (count++ < 10000) && \
834 + !(*ep->reg_udccsr & UDCCSR_FS));
835 + if (count >= 10000)
836 + DMSG("Failed to send packet\n");
837 + else
838 + DMSG("%s: short packet sent len:%d,"
839 + "length:%d,actual:%d\n", __FUNCTION__,
840 + tmp, req->req.length, req->req.actual);
841 + req->req.actual = req->req.length;
842 + completed = 1;
843 + /* There are still packets to transfer */
844 + } else if ( ep->dma_con) {
845 + DMSG("%s: more packets,length:%d,actual:%d\n",
846 + __FUNCTION__,req->req.length,
847 + req->req.actual);
848 + req->req.actual += ep->ep.maxpacket;
849 + completed = 0;
850 + } else {
851 + DMSG("%s: no more packets,length:%d,"
852 + "actual:%d\n", __FUNCTION__,
853 + req->req.length, req->req.actual);
854 + req->req.actual = req->req.length;
855 + completed = 1;
856 + }
857 + } else {
858 + req->req.actual = req->req.length;
859 + completed = 1;
860 + }
861 + } else if (dcsr & DCSR_EORINTR) { //Only happened in OUT DMA
862 + int remain,udccsr ;
863 +
864 + DCSR(dmach) = DCSR_EORINTR;
865 + remain = DCMD(dmach) & DCMD_LENGTH;
866 + req->req.actual = req->req.length - remain;
867 +
868 + udccsr = *ep->reg_udccsr;
869 + if (udccsr & UDCCSR_SP) {
870 + *ep->reg_udccsr = UDCCSR_PC | (udccsr & UDCCSR_MASK);
871 + completed = 1;
872 + }
873 + DMSG("%s: length:%d actual:%d\n",
874 + __FUNCTION__, req->req.length, req->req.actual);
875 + } else
876 + DMSG("%s: Others dma:%d DCSR:0x%x DCMD:0x%x\n",
877 + __FUNCTION__, dmach, DCSR(dmach), DCMD(dmach));
878 +
879 + if (likely(completed)) {
880 + if (req->queue.next != &ep->queue) {
881 + req_next = list_entry(req->queue.next,
882 + struct pxa27x_request, queue);
883 + kick_dma(ep, req_next);
884 + }
885 + done(ep, req, 0);
886 + } else {
887 + kick_dma(ep, req);
888 + }
889 +
890 + local_irq_enable();
891 +}
892 +
893 +#endif
894 +/*-------------------------------------------------------------------------*/
895 +
896 +static int
897 +pxa27x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, unsigned gfp_flags)
898 +{
899 + struct pxa27x_ep *ep;
900 + struct pxa27x_request *req;
901 + struct pxa27x_udc *dev;
902 + unsigned long flags;
903 +
904 + req = container_of(_req, struct pxa27x_request, req);
905 + if (unlikely (!_req || !_req->complete || !_req->buf||
906 + !list_empty(&req->queue))) {
907 + DMSG("%s, bad params\n", __FUNCTION__);
908 + return -EINVAL;
909 + }
910 +
911 + ep = container_of(_ep, struct pxa27x_ep, ep);
912 + if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
913 + DMSG("%s, bad ep\n", __FUNCTION__);
914 + return -EINVAL;
915 + }
916 +
917 + DMSG("%s, ep point %d is queue\n", __FUNCTION__, ep->ep_num);
918 +
919 + dev = ep->dev;
920 + if (unlikely (!dev->driver
921 + || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
922 + DMSG("%s, bogus device state\n", __FUNCTION__);
923 + return -ESHUTDOWN;
924 + }
925 +
926 + /* iso is always one packet per request, that's the only way
927 + * we can report per-packet status. that also helps with dma.
928 + */
929 + if (unlikely (ep->ep_type == USB_ENDPOINT_XFER_ISOC
930 + && req->req.length > le16_to_cpu
931 + (ep->desc->wMaxPacketSize)))
932 + return -EMSGSIZE;
933 +
934 +#ifdef USE_DMA
935 + // FIXME caller may already have done the dma mapping
936 + if (ep->dma >= 0) {
937 + _req->dma = dma_map_single(dev->dev, _req->buf, _req->length,
938 + (ep->dir_in) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
939 + }
940 +#endif
941 +
942 + DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
943 + _ep->name, _req, _req->length, _req->buf);
944 +
945 + local_irq_save(flags);
946 +
947 + _req->status = -EINPROGRESS;
948 + _req->actual = 0;
949 +
950 + /* kickstart this i/o queue? */
951 + if (list_empty(&ep->queue) && !ep->stopped) {
952 + if (ep->desc == 0 /* ep0 */) {
953 + unsigned length = _req->length;
954 +
955 + switch (dev->ep0state) {
956 + case EP0_IN_DATA_PHASE:
957 + dev->stats.write.ops++;
958 + if (write_ep0_fifo(ep, req))
959 + req = 0;
960 + break;
961 +
962 + case EP0_OUT_DATA_PHASE:
963 + dev->stats.read.ops++;
964 + if (dev->req_pending)
965 + ep0start(dev, UDCCSR0_IPR, "OUT");
966 + if (length == 0 || ((UDCCSR0 & UDCCSR0_RNE) != 0
967 + && read_ep0_fifo(ep, req))) {
968 + ep0_idle(dev);
969 + done(ep, req, 0);
970 + req = 0;
971 + }
972 + break;
973 + case EP0_NO_ACTION:
974 + ep0_idle(dev);
975 + req=0;
976 + break;
977 + default:
978 + DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
979 + local_irq_restore (flags);
980 + return -EL2HLT;
981 + }
982 +#ifdef USE_DMA
983 + /* either start dma or prime pio pump */
984 + } else if (ep->dma >= 0) {
985 + kick_dma(ep, req);
986 +#endif
987 + /* can the FIFO can satisfy the request immediately? */
988 + } else if (ep->dir_in
989 + && (*ep->reg_udccsr & UDCCSR_FS) != 0
990 + && write_fifo(ep, req)) {
991 + req = 0;
992 + } else if ((*ep->reg_udccsr & UDCCSR_FS) != 0
993 + && read_fifo(ep, req)) {
994 + req = 0;
995 + }
996 + DMSG("req:%p,ep->desc:%p,ep->dma:%d\n", req, ep->desc, ep->dma);
997 + if (likely (req && ep->desc) && ep->dma < 0)
998 + pio_irq_enable(ep->ep_num);
999 + }
1000 +
1001 + /* pio or dma irq handler advances the queue. */
1002 + if (likely (req != 0))
1003 + list_add_tail(&req->queue, &ep->queue);
1004 + local_irq_restore(flags);
1005 +
1006 + return 0;
1007 +}
1008 +
1009 +
1010 +/*
1011 + * nuke - dequeue ALL requests
1012 + */
1013 +static void nuke(struct pxa27x_ep *ep, int status)
1014 +{
1015 + struct pxa27x_request *req;
1016 +
1017 + /* called with irqs blocked */
1018 +#ifdef USE_DMA
1019 + if (ep->dma >= 0 && !ep->stopped)
1020 + cancel_dma(ep);
1021 +#endif
1022 + while (!list_empty(&ep->queue)) {
1023 + req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1024 + done(ep, req, status);
1025 + }
1026 + if (ep->desc)
1027 + pio_irq_disable (ep->ep_num);
1028 +}
1029 +
1030 +
1031 +/* dequeue JUST ONE request */
1032 +static int pxa27x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1033 +{
1034 + struct pxa27x_ep *ep;
1035 + struct pxa27x_request *req;
1036 + unsigned long flags;
1037 +
1038 + ep = container_of(_ep, struct pxa27x_ep, ep);
1039 + if (!_ep || ep->ep.name == ep0name)
1040 + return -EINVAL;
1041 +
1042 + local_irq_save(flags);
1043 +
1044 + /* make sure it's actually queued on this endpoint */
1045 + list_for_each_entry (req, &ep->queue, queue) {
1046 + if (&req->req == _req)
1047 + break;
1048 + }
1049 + if (&req->req != _req) {
1050 + local_irq_restore(flags);
1051 + return -EINVAL;
1052 + }
1053 +
1054 +#ifdef USE_DMA
1055 + if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1056 + cancel_dma(ep);
1057 + done(ep, req, -ECONNRESET);
1058 + /* restart i/o */
1059 + if (!list_empty(&ep->queue)) {
1060 + req = list_entry(ep->queue.next,
1061 + struct pxa27x_request, queue);
1062 + kick_dma(ep, req);
1063 + }
1064 + } else
1065 +#endif
1066 + done(ep, req, -ECONNRESET);
1067 +
1068 + local_irq_restore(flags);
1069 + return 0;
1070 +}
1071 +
1072 +/*-------------------------------------------------------------------------*/
1073 +
1074 +static int pxa27x_ep_set_halt(struct usb_ep *_ep, int value)
1075 +{
1076 + struct pxa27x_ep *ep;
1077 + unsigned long flags;
1078 +
1079 + DMSG("%s is called\n", __FUNCTION__);
1080 + ep = container_of(_ep, struct pxa27x_ep, ep);
1081 + if (unlikely (!_ep
1082 + || (!ep->desc && ep->ep.name != ep0name))
1083 + || ep->ep_type == USB_ENDPOINT_XFER_ISOC) {
1084 + DMSG("%s, bad ep\n", __FUNCTION__);
1085 + return -EINVAL;
1086 + }
1087 + if (value == 0) {
1088 + /* this path (reset toggle+halt) is needed to implement
1089 + * SET_INTERFACE on normal hardware. but it can't be
1090 + * done from software on the PXA UDC, and the hardware
1091 + * forgets to do it as part of SET_INTERFACE automagic.
1092 + */
1093 + DMSG("only host can clear %s halt\n", _ep->name);
1094 + return -EROFS;
1095 + }
1096 +
1097 + local_irq_save(flags);
1098 +
1099 + if (ep->dir_in && ((*ep->reg_udccsr & UDCCSR_FS) == 0
1100 + || !list_empty(&ep->queue))) {
1101 + local_irq_restore(flags);
1102 + return -EAGAIN;
1103 + }
1104 +
1105 + /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1106 + *ep->reg_udccsr = UDCCSR_FST|UDCCSR_FEF;
1107 +
1108 + /* ep0 needs special care */
1109 + if (!ep->desc) {
1110 + start_watchdog(ep->dev);
1111 + ep->dev->req_pending = 0;
1112 + ep->dev->ep0state = EP0_STALL;
1113 + LED_EP0_OFF;
1114 +
1115 + /* and bulk/intr endpoints like dropping stalls too */
1116 + } else {
1117 + unsigned i;
1118 + for (i = 0; i < 1000; i += 20) {
1119 + if (*ep->reg_udccsr & UDCCSR_SST)
1120 + break;
1121 + udelay(20);
1122 + }
1123 + }
1124 + local_irq_restore(flags);
1125 +
1126 + DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1127 + return 0;
1128 +}
1129 +
1130 +static int pxa27x_ep_fifo_status(struct usb_ep *_ep)
1131 +{
1132 + struct pxa27x_ep *ep;
1133 +
1134 + ep = container_of(_ep, struct pxa27x_ep, ep);
1135 + if (!_ep) {
1136 + DMSG("%s, bad ep\n", __FUNCTION__);
1137 + return -ENODEV;
1138 + }
1139 + /* pxa can't report unclaimed bytes from IN fifos */
1140 + if (ep->dir_in)
1141 + return -EOPNOTSUPP;
1142 + if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1143 + || (*ep->reg_udccsr & UDCCSR_FS) == 0)
1144 + return 0;
1145 + else
1146 + return (*ep->reg_udcbcr & 0xfff) + 1;
1147 +}
1148 +
1149 +static void pxa27x_ep_fifo_flush(struct usb_ep *_ep)
1150 +{
1151 + struct pxa27x_ep *ep;
1152 +
1153 + ep = container_of(_ep, struct pxa27x_ep, ep);
1154 + if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1155 + DMSG("%s, bad ep\n", __FUNCTION__);
1156 + return;
1157 + }
1158 +
1159 + /* toggle and halt bits stay unchanged */
1160 +
1161 + /* for OUT, just read and discard the FIFO contents. */
1162 + if (!ep->dir_in) {
1163 + while (((*ep->reg_udccsr) & UDCCSR_BNE) != 0)
1164 + (void) *ep->reg_udcdr;
1165 + return;
1166 + }
1167 +
1168 + /* most IN status is the same, but ISO can't stall */
1169 + *ep->reg_udccsr = UDCCSR_PC|UDCCSR_FST|UDCCSR_TRN
1170 + | (ep->ep_type == USB_ENDPOINT_XFER_ISOC)
1171 + ? 0 : UDCCSR_SST;
1172 +}
1173 +
1174 +
1175 +static struct usb_ep_ops pxa27x_ep_ops = {
1176 + .enable = pxa27x_ep_enable,
1177 + .disable = pxa27x_ep_disable,
1178 +
1179 + .alloc_request = pxa27x_ep_alloc_request,
1180 + .free_request = pxa27x_ep_free_request,
1181 +
1182 + .alloc_buffer = pxa27x_ep_alloc_buffer,
1183 + .free_buffer = pxa27x_ep_free_buffer,
1184 +
1185 + .queue = pxa27x_ep_queue,
1186 + .dequeue = pxa27x_ep_dequeue,
1187 +
1188 + .set_halt = pxa27x_ep_set_halt,
1189 + .fifo_status = pxa27x_ep_fifo_status,
1190 + .fifo_flush = pxa27x_ep_fifo_flush,
1191 +};
1192 +
1193 +
1194 +/* ---------------------------------------------------------------------------
1195 + * device-scoped parts of the api to the usb controller hardware
1196 + * ---------------------------------------------------------------------------
1197 + */
1198 +
1199 +static int pxa27x_udc_get_frame(struct usb_gadget *_gadget)
1200 +{
1201 + return (UDCFNR & 0x3FF);
1202 +}
1203 +
1204 +static int pxa27x_udc_wakeup(struct usb_gadget *_gadget)
1205 +{
1206 + /* host may not have enabled remote wakeup */
1207 + if ((UDCCR & UDCCR_DWRE) == 0)
1208 + return -EHOSTUNREACH;
1209 + udc_set_mask_UDCCR(UDCCR_UDR);
1210 + return 0;
1211 +}
1212 +
1213 +static const struct usb_gadget_ops pxa27x_udc_ops = {
1214 + .get_frame = pxa27x_udc_get_frame,
1215 + .wakeup = pxa27x_udc_wakeup,
1216 + // current versions must always be self-powered
1217 +};
1218 +
1219 +
1220 +/*-------------------------------------------------------------------------*/
1221 +
1222 +#ifdef UDC_PROC_FILE
1223 +
1224 +static const char proc_node_name [] = "driver/udc";
1225 +
1226 +static int
1227 +udc_proc_read(char *page, char **start, off_t off, int count,
1228 + int *eof, void *_dev)
1229 +{
1230 + char *buf = page;
1231 + struct pxa27x_udc *dev = _dev;
1232 + char *next = buf;
1233 + unsigned size = count;
1234 + unsigned long flags;
1235 + int i, t;
1236 + u32 tmp;
1237 +
1238 + if (off != 0)
1239 + return 0;
1240 +
1241 + local_irq_save(flags);
1242 +
1243 + /* basic device status */
1244 + t = scnprintf(next, size, DRIVER_DESC "\n"
1245 + "%s version: %s\nGadget driver: %s\n",
1246 + driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1247 + dev->driver ? dev->driver->driver.name : "(none)");
1248 + size -= t;
1249 + next += t;
1250 +
1251 + /* registers for device and ep0 */
1252 + t = scnprintf(next, size,
1253 + "uicr %02X.%02X, usir %02X.%02x, ufnr %02X\n",
1254 + UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR);
1255 + size -= t;
1256 + next += t;
1257 +
1258 + tmp = UDCCR;
1259 + t = scnprintf(next, size,"udccr %02X =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n", tmp,
1260 + (tmp & UDCCR_OEN) ? " oen":"",
1261 + (tmp & UDCCR_AALTHNP) ? " aalthnp":"",
1262 + (tmp & UDCCR_AHNP) ? " rem" : "",
1263 + (tmp & UDCCR_BHNP) ? " rstir" : "",
1264 + (tmp & UDCCR_DWRE) ? " dwre" : "",
1265 + (tmp & UDCCR_SMAC) ? " smac" : "",
1266 + (tmp & UDCCR_EMCE) ? " emce" : "",
1267 + (tmp & UDCCR_UDR) ? " udr" : "",
1268 + (tmp & UDCCR_UDA) ? " uda" : "",
1269 + (tmp & UDCCR_UDE) ? " ude" : "",
1270 + (tmp & UDCCR_ACN) >> UDCCR_ACN_S,
1271 + (tmp & UDCCR_AIN) >> UDCCR_AIN_S,
1272 + (tmp & UDCCR_AAISN)>> UDCCR_AAISN_S );
1273 +
1274 + size -= t;
1275 + next += t;
1276 +
1277 + tmp = UDCCSR0;
1278 + t = scnprintf(next, size,
1279 + "udccsr0 %02X =%s%s%s%s%s%s%s\n", tmp,
1280 + (tmp & UDCCSR0_SA) ? " sa" : "",
1281 + (tmp & UDCCSR0_RNE) ? " rne" : "",
1282 + (tmp & UDCCSR0_FST) ? " fst" : "",
1283 + (tmp & UDCCSR0_SST) ? " sst" : "",
1284 + (tmp & UDCCSR0_DME) ? " dme" : "",
1285 + (tmp & UDCCSR0_IPR) ? " ipr" : "",
1286 + (tmp & UDCCSR0_OPC) ? " opc" : "");
1287 + size -= t;
1288 + next += t;
1289 +
1290 + if (!dev->driver)
1291 + goto done;
1292 +
1293 + t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1294 + dev->stats.write.bytes, dev->stats.write.ops,
1295 + dev->stats.read.bytes, dev->stats.read.ops,
1296 + dev->stats.irqs);
1297 + size -= t;
1298 + next += t;
1299 +
1300 + /* dump endpoint queues */
1301 + for (i = 0; i < UDC_EP_NUM; i++) {
1302 + struct pxa27x_ep *ep = &dev->ep [i];
1303 + struct pxa27x_request *req;
1304 + int t;
1305 +
1306 + if (i != 0) {
1307 + const struct usb_endpoint_descriptor *d;
1308 +
1309 + d = ep->desc;
1310 + if (!d)
1311 + continue;
1312 + tmp = *dev->ep [i].reg_udccsr;
1313 + t = scnprintf(next, size,
1314 + "%s max %d %s udccs %02x udccr:0x%x\n",
1315 + ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1316 + (ep->dma >= 0) ? "dma" : "pio", tmp,
1317 + *dev->ep[i].reg_udccr);
1318 + /* TODO translate all five groups of udccs bits! */
1319 +
1320 + } else /* ep0 should only have one transfer queued */
1321 + t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1322 + ep->pio_irqs);
1323 + if (t <= 0 || t > size)
1324 + goto done;
1325 + size -= t;
1326 + next += t;
1327 +
1328 + if (list_empty(&ep->queue)) {
1329 + t = scnprintf(next, size, "\t(nothing queued)\n");
1330 + if (t <= 0 || t > size)
1331 + goto done;
1332 + size -= t;
1333 + next += t;
1334 + continue;
1335 + }
1336 + list_for_each_entry(req, &ep->queue, queue) {
1337 +#ifdef USE_DMA
1338 + if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1339 + t = scnprintf(next, size,
1340 + "\treq %p len %d/%d "
1341 + "buf %p (dma%d dcmd %08x)\n",
1342 + &req->req, req->req.actual,
1343 + req->req.length, req->req.buf,
1344 + ep->dma, DCMD(ep->dma)
1345 + // low 13 bits == bytes-to-go
1346 + );
1347 + else
1348 +#endif
1349 + t = scnprintf(next, size,
1350 + "\treq %p len %d/%d buf %p\n",
1351 + &req->req, req->req.actual,
1352 + req->req.length, req->req.buf);
1353 + if (t <= 0 || t > size)
1354 + goto done;
1355 + size -= t;
1356 + next += t;
1357 + }
1358 + }
1359 +
1360 +done:
1361 + local_irq_restore(flags);
1362 + *eof = 1;
1363 + return count - size;
1364 +}
1365 +
1366 +#define create_proc_files() \
1367 + create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1368 +#define remove_proc_files() \
1369 + remove_proc_entry(proc_node_name, NULL)
1370 +
1371 +#else /* !UDC_PROC_FILE */
1372 +#define create_proc_files() do {} while (0)
1373 +#define remove_proc_files() do {} while (0)
1374 +
1375 +#endif /* UDC_PROC_FILE */
1376 +
1377 +/* "function" sysfs attribute */
1378 +static ssize_t
1379 +show_function (struct device *_dev, struct device_attribute *attr, char *buf)
1380 +{
1381 + struct pxa27x_udc *dev = dev_get_drvdata (_dev);
1382 +
1383 + if (!dev->driver
1384 + || !dev->driver->function
1385 + || strlen (dev->driver->function) > PAGE_SIZE)
1386 + return 0;
1387 + return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1388 +}
1389 +static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1390 +
1391 +/*-------------------------------------------------------------------------*/
1392 +
1393 +/*
1394 + * udc_disable - disable USB device controller
1395 + */
1396 +static void udc_disable(struct pxa27x_udc *dev)
1397 +{
1398 + UDCICR0 = UDCICR1 = 0x00000000;
1399 +
1400 + udc_clear_mask_UDCCR(UDCCR_UDE);
1401 +
1402 + /* Disable clock for USB device */
1403 + pxa_set_cken(CKEN11_USB, 0);
1404 +
1405 + ep0_idle (dev);
1406 + dev->gadget.speed = USB_SPEED_UNKNOWN;
1407 + LED_CONNECTED_OFF;
1408 + if (dev->mach->udc_command)
1409 + dev->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
1410 +}
1411 +
1412 +
1413 +/*
1414 + * udc_reinit - initialize software state
1415 + */
1416 +static void udc_reinit(struct pxa27x_udc *dev)
1417 +{
1418 + u32 i;
1419 +
1420 + dev->ep0state = EP0_IDLE;
1421 +
1422 + /* basic endpoint records init */
1423 + for (i = 0; i < UDC_EP_NUM; i++) {
1424 + struct pxa27x_ep *ep = &dev->ep[i];
1425 +
1426 + ep->stopped = 0;
1427 + ep->pio_irqs = ep->dma_irqs = 0;
1428 + }
1429 + dev->configuration = 0;
1430 + dev->interface = 0;
1431 + dev->alternate = 0;
1432 + /* the rest was statically initialized, and is read-only */
1433 +}
1434 +
1435 +/* until it's enabled, this UDC should be completely invisible
1436 + * to any USB host.
1437 + */
1438 +static void udc_enable (struct pxa27x_udc *dev)
1439 +{
1440 + udc_clear_mask_UDCCR(UDCCR_UDE);
1441 +
1442 + // MST_MSCWR2 &= ~(MST_MSCWR2_nUSBC_SC);
1443 +
1444 + /* Enable clock for USB device */
1445 + pxa_set_cken(CKEN11_USB, 1);
1446 +
1447 + UDCICR0 = UDCICR1 = 0;
1448 +
1449 + ep0_idle(dev);
1450 + dev->gadget.speed = USB_SPEED_FULL;
1451 + dev->stats.irqs = 0;
1452 +
1453 + udc_set_mask_UDCCR(UDCCR_UDE);
1454 + udelay (2);
1455 + if (UDCCR & UDCCR_EMCE)
1456 + {
1457 + printk(KERN_ERR ": There are error in configuration, udc disabled\n");
1458 + }
1459 +
1460 + /* caller must be able to sleep in order to cope
1461 + * with startup transients.
1462 + */
1463 + msleep(100);
1464 +
1465 + /* enable suspend/resume and reset irqs */
1466 + UDCICR1 = UDCICR1_IECC | UDCICR1_IERU | UDCICR1_IESU | UDCICR1_IERS;
1467 +
1468 + /* enable ep0 irqs */
1469 + UDCICR0 = UDCICR_INT(0,UDCICR_INT_MASK);
1470 +#if 0
1471 + for(i=1; i < UDC_EP_NUM; i++) {
1472 + if (dev->ep[i].assigned)
1473 + pio_irq_enable(i);
1474 + }
1475 +#endif
1476 + if (dev->mach->udc_command)
1477 + dev->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
1478 +}
1479 +
1480 +
1481 +/* when a driver is successfully registered, it will receive
1482 + * control requests including set_configuration(), which enables
1483 + * non-control requests. then usb traffic follows until a
1484 + * disconnect is reported. then a host may connect again, or
1485 + * the driver might get unbound.
1486 + */
1487 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1488 +{
1489 + struct pxa27x_udc *dev = the_controller;
1490 + int retval;
1491 +#if 0
1492 + DMSG("dev=0x%x, driver=0x%x, speed=%d,"
1493 + "bind=0x%x, unbind=0x%x, disconnect=0x%x, setup=0x%x\n",
1494 + (unsigned)dev, (unsigned)driver, driver->speed,
1495 + (unsigned)driver->bind, (unsigned)driver->unbind,
1496 + (unsigned)driver->disconnect, (unsigned)driver->setup);
1497 +#endif
1498 + if (!driver || driver->speed != USB_SPEED_FULL
1499 + || !driver->bind
1500 + || !driver->unbind
1501 + || !driver->disconnect
1502 + || !driver->setup)
1503 + return -EINVAL;
1504 + if (!dev)
1505 + return -ENODEV;
1506 + if (dev->driver)
1507 + return -EBUSY;
1508 +
1509 + /* first hook up the driver ... */
1510 + dev->driver = driver;
1511 + dev->gadget.dev.driver = &driver->driver;
1512 +
1513 + device_add (&dev->gadget.dev);
1514 + retval = driver->bind(&dev->gadget);
1515 + if (retval) {
1516 + DMSG("bind to driver %s --> error %d\n",
1517 + driver->driver.name, retval);
1518 + device_del (&dev->gadget.dev);
1519 +
1520 + dev->driver = 0;
1521 + dev->gadget.dev.driver = 0;
1522 + return retval;
1523 + }
1524 + device_create_file(dev->dev, &dev_attr_function);
1525 +
1526 + /* ... then enable host detection and ep0; and we're ready
1527 + * for set_configuration as well as eventual disconnect.
1528 + * NOTE: this shouldn't power up until later.
1529 + */
1530 + DMSG("registered gadget driver '%s'\n", driver->driver.name);
1531 + udc_enable(dev);
1532 + dump_state(dev);
1533 + return 0;
1534 +}
1535 +EXPORT_SYMBOL(usb_gadget_register_driver);
1536 +
1537 +static void
1538 +stop_activity(struct pxa27x_udc *dev, struct usb_gadget_driver *driver)
1539 +{
1540 + int i;
1541 +
1542 + DMSG("Trace path 1\n");
1543 + /* don't disconnect drivers more than once */
1544 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1545 + driver = 0;
1546 + dev->gadget.speed = USB_SPEED_UNKNOWN;
1547 +
1548 + /* prevent new request submissions, kill any outstanding requests */
1549 + for (i = 0; i < UDC_EP_NUM; i++) {
1550 + struct pxa27x_ep *ep = &dev->ep[i];
1551 +
1552 + ep->stopped = 1;
1553 + nuke(ep, -ESHUTDOWN);
1554 + }
1555 + del_timer_sync(&dev->timer);
1556 +
1557 + /* report disconnect; the driver is already quiesced */
1558 + if (driver)
1559 + driver->disconnect(&dev->gadget);
1560 +
1561 + /* re-init driver-visible data structures */
1562 + udc_reinit(dev);
1563 +}
1564 +
1565 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1566 +{
1567 + struct pxa27x_udc *dev = the_controller;
1568 +
1569 + if (!dev)
1570 + return -ENODEV;
1571 + if (!driver || driver != dev->driver)
1572 + return -EINVAL;
1573 +
1574 + local_irq_disable();
1575 + udc_disable(dev);
1576 + stop_activity(dev, driver);
1577 + local_irq_enable();
1578 +
1579 + driver->unbind(&dev->gadget);
1580 + dev->driver = 0;
1581 +
1582 + device_del (&dev->gadget.dev);
1583 + device_remove_file(dev->dev, &dev_attr_function);
1584 +
1585 + DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1586 + dump_state(dev);
1587 + return 0;
1588 +}
1589 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
1590 +
1591 +#ifndef enable_disconnect_irq
1592 +#define enable_disconnect_irq() do {} while (0)
1593 +#define disable_disconnect_irq() do {} while (0)
1594 +#endif
1595 +
1596 +
1597 +/*-------------------------------------------------------------------------*/
1598 +
1599 +static inline void clear_ep_state (struct pxa27x_udc *dev)
1600 +{
1601 + unsigned i;
1602 +
1603 + /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1604 + * fifos, and pending transactions mustn't be continued in any case.
1605 + */
1606 + for (i = 1; i < UDC_EP_NUM; i++)
1607 + nuke(&dev->ep[i], -ECONNABORTED);
1608 +}
1609 +
1610 +static void udc_watchdog(unsigned long _dev)
1611 +{
1612 + struct pxa27x_udc *dev = (void *)_dev;
1613 +
1614 + local_irq_disable();
1615 + if (dev->ep0state == EP0_STALL
1616 + && (UDCCSR0 & UDCCSR0_FST) == 0
1617 + && (UDCCSR0 & UDCCSR0_SST) == 0) {
1618 + UDCCSR0 = UDCCSR0_FST|UDCCSR0_FTF;
1619 + DBG(DBG_VERBOSE, "ep0 re-stall\n");
1620 + start_watchdog(dev);
1621 + }
1622 + local_irq_enable();
1623 +}
1624 +
1625 +static void handle_ep0 (struct pxa27x_udc *dev)
1626 +{
1627 + u32 udccsr0 = UDCCSR0;
1628 + struct pxa27x_ep *ep = &dev->ep [0];
1629 + struct pxa27x_request *req;
1630 + union {
1631 + struct usb_ctrlrequest r;
1632 + u8 raw [8];
1633 + u32 word [2];
1634 + } u;
1635 +
1636 + if (list_empty(&ep->queue))
1637 + req = 0;
1638 + else
1639 + req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1640 +
1641 + /* clear stall status */
1642 + if (udccsr0 & UDCCSR0_SST) {
1643 + nuke(ep, -EPIPE);
1644 + UDCCSR0 = UDCCSR0_SST;
1645 + del_timer(&dev->timer);
1646 + ep0_idle(dev);
1647 + }
1648 +
1649 + /* previous request unfinished? non-error iff back-to-back ... */
1650 + if ((udccsr0 & UDCCSR0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1651 + nuke(ep, 0);
1652 + del_timer(&dev->timer);
1653 + ep0_idle(dev);
1654 + }
1655 +
1656 + switch (dev->ep0state) {
1657 + case EP0_NO_ACTION:
1658 + printk(KERN_INFO"%s: Busy\n", __FUNCTION__);
1659 + /*Fall through */
1660 + case EP0_IDLE:
1661 + /* late-breaking status? */
1662 + udccsr0 = UDCCSR0;
1663 +
1664 + /* start control request? */
1665 + if (likely((udccsr0 & (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))
1666 + == (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))) {
1667 + int i;
1668 +
1669 + nuke (ep, -EPROTO);
1670 + /* read SETUP packet */
1671 + for (i = 0; i < 2; i++) {
1672 + if (unlikely(!(UDCCSR0 & UDCCSR0_RNE))) {
1673 +bad_setup:
1674 + DMSG("SETUP %d!\n", i);
1675 + goto stall;
1676 + }
1677 + u.word [i] = UDCDR0;
1678 + }
1679 + if (unlikely((UDCCSR0 & UDCCSR0_RNE) != 0))
1680 + goto bad_setup;
1681 +
1682 + le16_to_cpus (&u.r.wValue);
1683 + le16_to_cpus (&u.r.wIndex);
1684 + le16_to_cpus (&u.r.wLength);
1685 +
1686 + LED_EP0_ON;
1687 +
1688 + DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1689 + u.r.bRequestType, u.r.bRequest,
1690 + u.r.wValue, u.r.wIndex, u.r.wLength);
1691 + /* cope with automagic for some standard requests. */
1692 + dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1693 + == USB_TYPE_STANDARD;
1694 + dev->req_config = 0;
1695 + dev->req_pending = 1;
1696 +#if 0
1697 + switch (u.r.bRequest) {
1698 + /* hardware was supposed to hide this */
1699 + case USB_REQ_SET_CONFIGURATION:
1700 + case USB_REQ_SET_INTERFACE:
1701 + case USB_REQ_SET_ADDRESS:
1702 + printk(KERN_ERR "Should not come here\n");
1703 + break;
1704 + }
1705 +
1706 +#endif
1707 + if (u.r.bRequestType & USB_DIR_IN)
1708 + dev->ep0state = EP0_IN_DATA_PHASE;
1709 + else
1710 + dev->ep0state = EP0_OUT_DATA_PHASE;
1711 + i = dev->driver->setup(&dev->gadget, &u.r);
1712 +
1713 + if (i < 0) {
1714 + /* hardware automagic preventing STALL... */
1715 + if (dev->req_config) {
1716 + /* hardware sometimes neglects to tell
1717 + * tell us about config change events,
1718 + * so later ones may fail...
1719 + */
1720 + WARN("config change %02x fail %d?\n",
1721 + u.r.bRequest, i);
1722 + return;
1723 + /* TODO experiment: if has_cfr,
1724 + * hardware didn't ACK; maybe we
1725 + * could actually STALL!
1726 + */
1727 + }
1728 + DBG(DBG_VERBOSE, "protocol STALL, "
1729 + "%02x err %d\n", UDCCSR0, i);
1730 +stall:
1731 + /* the watchdog timer helps deal with cases
1732 + * where udc seems to clear FST wrongly, and
1733 + * then NAKs instead of STALLing.
1734 + */
1735 + ep0start(dev, UDCCSR0_FST|UDCCSR0_FTF, "stall");
1736 + start_watchdog(dev);
1737 + dev->ep0state = EP0_STALL;
1738 + LED_EP0_OFF;
1739 +
1740 + /* deferred i/o == no response yet */
1741 + } else if (dev->req_pending) {
1742 + if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1743 + || dev->req_std || u.r.wLength))
1744 + ep0start(dev, 0, "defer");
1745 + else
1746 + ep0start(dev, UDCCSR0_IPR, "defer/IPR");
1747 + }
1748 +
1749 + /* expect at least one data or status stage irq */
1750 + return;
1751 +
1752 + } else {
1753 + /* some random early IRQ:
1754 + * - we acked FST
1755 + * - IPR cleared
1756 + * - OPC got set, without SA (likely status stage)
1757 + */
1758 + UDCCSR0 = udccsr0 & (UDCCSR0_SA|UDCCSR0_OPC);
1759 + }
1760 + break;
1761 + case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1762 + if (udccsr0 & UDCCSR0_OPC) {
1763 + UDCCSR0 = UDCCSR0_OPC|UDCCSR0_FTF;
1764 + DBG(DBG_VERBOSE, "ep0in premature status\n");
1765 + if (req)
1766 + done(ep, req, 0);
1767 + ep0_idle(dev);
1768 + } else /* irq was IPR clearing */ {
1769 + if (req) {
1770 + /* this IN packet might finish the request */
1771 + (void) write_ep0_fifo(ep, req);
1772 + } /* else IN token before response was written */
1773 + }
1774 + break;
1775 + case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1776 + if (udccsr0 & UDCCSR0_OPC) {
1777 + if (req) {
1778 + /* this OUT packet might finish the request */
1779 + if (read_ep0_fifo(ep, req))
1780 + done(ep, req, 0);
1781 + /* else more OUT packets expected */
1782 + } /* else OUT token before read was issued */
1783 + } else /* irq was IPR clearing */ {
1784 + DBG(DBG_VERBOSE, "ep0out premature status\n");
1785 + if (req)
1786 + done(ep, req, 0);
1787 + ep0_idle(dev);
1788 + }
1789 + break;
1790 + case EP0_STALL:
1791 + UDCCSR0 = UDCCSR0_FST;
1792 + break;
1793 + }
1794 + UDCISR0 = UDCISR_INT(0, UDCISR_INT_MASK);
1795 +}
1796 +
1797 +
1798 +static void handle_ep(struct pxa27x_ep *ep)
1799 +{
1800 + struct pxa27x_request *req;
1801 + int completed;
1802 + u32 udccsr=0;
1803 +
1804 + DMSG("%s is called\n", __FUNCTION__);
1805 + do {
1806 + completed = 0;
1807 + if (likely (!list_empty(&ep->queue))) {
1808 + req = list_entry(ep->queue.next,
1809 + struct pxa27x_request, queue);
1810 + } else
1811 + req = 0;
1812 +
1813 +// udccsr = *ep->reg_udccsr;
1814 + DMSG("%s: req:%p, udcisr0:0x%x udccsr %p:0x%x\n", __FUNCTION__,
1815 + req, UDCISR0, ep->reg_udccsr, *ep->reg_udccsr);
1816 + if (unlikely(ep->dir_in)) {
1817 + udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr;
1818 + if (unlikely (udccsr))
1819 + *ep->reg_udccsr = udccsr;
1820 +
1821 + if (req && likely ((*ep->reg_udccsr & UDCCSR_FS) != 0))
1822 + completed = write_fifo(ep, req);
1823 +
1824 + } else {
1825 + udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr;
1826 + if (unlikely(udccsr))
1827 + *ep->reg_udccsr = udccsr;
1828 +
1829 + /* fifos can hold packets, ready for reading... */
1830 + if (likely(req)) {
1831 + completed = read_fifo(ep, req);
1832 + } else {
1833 + pio_irq_disable (ep->ep_num);
1834 + *ep->reg_udccsr = UDCCSR_FEF;
1835 + DMSG("%s: no req for out data\n",
1836 + __FUNCTION__);
1837 + }
1838 + }
1839 + ep->pio_irqs++;
1840 + } while (completed);
1841 +}
1842 +
1843 +static void pxa27x_change_configuration (struct pxa27x_udc *dev)
1844 +{
1845 + struct usb_ctrlrequest req ;
1846 +
1847 + req.bRequestType = 0;
1848 + req.bRequest = USB_REQ_SET_CONFIGURATION;
1849 + req.wValue = dev->configuration;
1850 + req.wIndex = 0;
1851 + req.wLength = 0;
1852 +
1853 + dev->ep0state = EP0_NO_ACTION;
1854 + dev->driver->setup(&dev->gadget, &req);
1855 +
1856 +}
1857 +
1858 +static void pxa27x_change_interface (struct pxa27x_udc *dev)
1859 +{
1860 + struct usb_ctrlrequest req;
1861 +
1862 + req.bRequestType = USB_RECIP_INTERFACE;
1863 + req.bRequest = USB_REQ_SET_INTERFACE;
1864 + req.wValue = dev->alternate;
1865 + req.wIndex = dev->interface;
1866 + req.wLength = 0;
1867 +
1868 + dev->ep0state = EP0_NO_ACTION;
1869 + dev->driver->setup(&dev->gadget, &req);
1870 +}
1871 +
1872 +/*
1873 + * pxa27x_udc_irq - interrupt handler
1874 + *
1875 + * avoid delays in ep0 processing. the control handshaking isn't always
1876 + * under software control (pxa250c0 and the pxa255 are better), and delays
1877 + * could cause usb protocol errors.
1878 + */
1879 +static irqreturn_t
1880 +pxa27x_udc_irq(int irq, void *_dev)
1881 +{
1882 + struct pxa27x_udc *dev = _dev;
1883 + int handled;
1884 +
1885 + dev->stats.irqs++;
1886 + HEX_DISPLAY(dev->stats.irqs);
1887 +
1888 +// printk("\n");
1889 + DBG(DBG_VERBOSE, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
1890 + "UDCCR:0x%08x\n", UDCISR0, UDCISR1, UDCCR);
1891 + do {
1892 + u32 udcir = UDCISR1 & 0xF8000000;
1893 +
1894 + handled = 0;
1895 +
1896 + /* SUSpend Interrupt Request */
1897 + if (unlikely(udcir & UDCISR1_IRSU)) {
1898 + UDCISR1 = UDCISR1_IRSU;
1899 + handled = 1;
1900 + DBG(DBG_VERBOSE, "USB suspend\n");
1901 + if (dev->gadget.speed != USB_SPEED_UNKNOWN
1902 + && dev->driver
1903 + && dev->driver->suspend)
1904 + dev->driver->suspend(&dev->gadget);
1905 + ep0_idle (dev);
1906 + }
1907 +
1908 + /* RESume Interrupt Request */
1909 + if (unlikely(udcir & UDCISR1_IRRU)) {
1910 + UDCISR1 = UDCISR1_IRRU;
1911 + handled = 1;
1912 + DBG(DBG_VERBOSE, "USB resume\n");
1913 +
1914 + if (dev->gadget.speed != USB_SPEED_UNKNOWN
1915 + && dev->driver
1916 + && dev->driver->resume)
1917 + dev->driver->resume(&dev->gadget);
1918 + }
1919 +
1920 + if (unlikely(udcir & UDCISR1_IRCC)) {
1921 + unsigned config, interface, alternate;
1922 +
1923 + handled = 1;
1924 + DBG(DBG_VERBOSE, "USB SET_CONFIGURATION or "
1925 + "SET_INTERFACE command received\n");
1926 +
1927 + UDCCR |= UDCCR_SMAC;
1928 +
1929 + config = (UDCCR & UDCCR_ACN) >> UDCCR_ACN_S;
1930 +
1931 + if (dev->configuration != config) {
1932 + dev->configuration = config;
1933 + pxa27x_change_configuration(dev) ;
1934 + }
1935 +
1936 + interface = (UDCCR & UDCCR_AIN) >> UDCCR_AIN_S;
1937 + alternate = (UDCCR & UDCCR_AAISN) >> UDCCR_AAISN_S;
1938 +
1939 + if ( (dev->configuration != interface) || \
1940 + (dev->alternate != alternate)){
1941 + dev->interface = config;
1942 + dev->alternate = alternate;
1943 + pxa27x_change_interface(dev);
1944 + }
1945 +
1946 + UDCISR1 = UDCISR1_IRCC;
1947 + DMSG("%s: con:%d,inter:%d,alt:%d\n",
1948 + __FUNCTION__, config,interface, alternate);
1949 + }
1950 +
1951 + /* ReSeT Interrupt Request - USB reset */
1952 + if (unlikely(udcir & UDCISR1_IRRS)) {
1953 + UDCISR1 = UDCISR1_IRRS;
1954 + handled = 1;
1955 +
1956 + if ((UDCCR & UDCCR_UDA) == 0) {
1957 + DBG(DBG_VERBOSE, "USB reset start\n");
1958 +
1959 + /* reset driver and endpoints,
1960 + * in case that's not yet done
1961 + */
1962 + stop_activity (dev, dev->driver);
1963 +
1964 + }
1965 + INFO("USB reset\n");
1966 + dev->gadget.speed = USB_SPEED_FULL;
1967 + memset(&dev->stats, 0, sizeof dev->stats);
1968 +
1969 + } else {
1970 + u32 udcisr0 = UDCISR0 ;
1971 + u32 udcisr1 = UDCISR1 & 0xFFFF;
1972 + int i;
1973 +
1974 + if (unlikely (!udcisr0 && !udcisr1))
1975 + continue;
1976 +
1977 + DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", udcisr1,udcisr0);
1978 +
1979 + /* control traffic */
1980 + if (udcisr0 & UDCISR0_IR0) {
1981 + dev->ep[0].pio_irqs++;
1982 + handle_ep0(dev);
1983 + handled = 1;
1984 + }
1985 +
1986 + udcisr0 >>= 2;
1987 + /* endpoint data transfers */
1988 + for (i = 1; udcisr0!=0 && i < 16; udcisr0>>=2,i++) {
1989 + UDCISR0 = UDCISR_INT(i, UDCISR_INT_MASK);
1990 +
1991 + if (udcisr0 & UDC_INT_FIFOERROR)
1992 + printk(KERN_ERR" Endpoint %d Fifo error\n", i);
1993 + if (udcisr0 & UDC_INT_PACKETCMP) {
1994 + handle_ep(&dev->ep[i]);
1995 + handled = 1;
1996 + }
1997 +
1998 + }
1999 +
2000 + for (i = 0; udcisr1!=0 && i < 8; udcisr1 >>= 2, i++) {
2001 + UDCISR1 = UDCISR_INT(i, UDCISR_INT_MASK);
2002 +
2003 + if (udcisr1 & UDC_INT_FIFOERROR) {
2004 + printk(KERN_ERR" Endpoint %d fifo error\n", (i+16));
2005 + }
2006 +
2007 + if (udcisr1 & UDC_INT_PACKETCMP) {
2008 + handle_ep(&dev->ep[i+16]);
2009 + handled = 1;
2010 + }
2011 + }
2012 + }
2013 +
2014 + /* we could also ask for 1 msec SOF (SIR) interrupts */
2015 +
2016 + } while (handled);
2017 + return IRQ_HANDLED;
2018 +}
2019 +
2020 +static inline void validate_fifo_size(struct pxa27x_ep *pxa_ep, u8 bmAttributes)
2021 +{
2022 + switch (bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2023 + case USB_ENDPOINT_XFER_CONTROL:
2024 + pxa_ep->fifo_size = EP0_FIFO_SIZE;
2025 + break;
2026 + case USB_ENDPOINT_XFER_ISOC:
2027 + pxa_ep->fifo_size = ISO_FIFO_SIZE;
2028 + break;
2029 + case USB_ENDPOINT_XFER_BULK:
2030 + pxa_ep->fifo_size = BULK_FIFO_SIZE;
2031 + break;
2032 + case USB_ENDPOINT_XFER_INT:
2033 + pxa_ep->fifo_size = INT_FIFO_SIZE;
2034 + break;
2035 + default:
2036 + break;
2037 + }
2038 +}
2039 +
2040 +static void udc_init_ep(struct pxa27x_udc *dev)
2041 +{
2042 + int i;
2043 +
2044 + INIT_LIST_HEAD (&dev->gadget.ep_list);
2045 + INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
2046 +
2047 + for (i = 0; i < UDC_EP_NUM; i++) {
2048 + struct pxa27x_ep *ep = &dev->ep[i];
2049 +
2050 + ep->dma = -1;
2051 + if (i != 0) {
2052 + memset(ep, 0, sizeof(*ep));
2053 + }
2054 + INIT_LIST_HEAD (&ep->queue);
2055 + }
2056 +}
2057 +#define NAME_SIZE 18
2058 +
2059 +struct usb_ep* pxa27x_ep_config(
2060 + struct usb_gadget *gadget,
2061 + struct usb_endpoint_descriptor *desc,
2062 + int config, int interface, int alt
2063 +)
2064 +{
2065 + u32 tmp ;
2066 + unsigned i;
2067 + char* name;
2068 + struct usb_ep * ep = NULL;
2069 + struct pxa27x_ep *pxa_ep = NULL;
2070 + struct pxa27x_udc *dev = the_controller;
2071 +
2072 + DMSG("pxa27x_config_ep is called\n");
2073 + DMSG(" usb endpoint descriptor is:\n"
2074 + " bLength:%d\n"
2075 + " bDescriptorType:%x\n"
2076 + " bEndpointAddress:%x\n"
2077 + " bmAttributes:%x\n"
2078 + " wMaxPacketSize:%d\n",
2079 + desc->bLength,
2080 + desc->bDescriptorType,desc->bEndpointAddress,
2081 + desc->bmAttributes,desc->wMaxPacketSize);
2082 +
2083 + for (i = 1; i < UDC_EP_NUM; i++) {
2084 + if(!dev->ep[i].assigned) {
2085 + pxa_ep = &dev->ep[i];
2086 + pxa_ep->assigned = 1;
2087 + pxa_ep->ep_num = i;
2088 + break;
2089 + }
2090 + }
2091 + if (unlikely(i == UDC_EP_NUM)) {
2092 + printk(KERN_ERR __FILE__ ": Failed to find a spare endpoint\n");
2093 + return ep;
2094 + }
2095 +
2096 +
2097 + ep = &pxa_ep->ep;
2098 +
2099 + pxa_ep->dev = dev;
2100 + pxa_ep->desc = desc;
2101 + pxa_ep->pio_irqs = pxa_ep->dma_irqs = 0;
2102 + pxa_ep->dma = -1;
2103 +
2104 + if (!(desc->bEndpointAddress & 0xF))
2105 + desc->bEndpointAddress |= i;
2106 +
2107 + if (!(desc->wMaxPacketSize)) {
2108 + validate_fifo_size(pxa_ep, desc->bmAttributes);
2109 + desc->wMaxPacketSize = pxa_ep->fifo_size;
2110 + } else
2111 + pxa_ep->fifo_size = desc->wMaxPacketSize;
2112 +
2113 + pxa_ep->dir_in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
2114 + pxa_ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
2115 + pxa_ep->stopped = 1;
2116 + pxa_ep->dma_con = 0;
2117 + pxa_ep->config = config;
2118 + pxa_ep->interface = interface;
2119 + pxa_ep->aisn = alt;
2120 +
2121 + pxa_ep->reg_udccsr = &UDCCSR0 + i;
2122 + pxa_ep->reg_udcbcr = &UDCBCR0 + i;
2123 + pxa_ep->reg_udcdr = &UDCDR0 + i ;
2124 + pxa_ep->reg_udccr = &UDCCRA - 1 + i;
2125 +#ifdef USE_DMA
2126 + pxa_ep->reg_drcmr = &DRCMR24 + i;
2127 +#endif
2128 +
2129 +#if 0
2130 + DMSG("udccsr=0x%8x, udcbcr=0x%8x, udcdr=0x%8x,"
2131 + "udccr0=0x%8x\n",
2132 + (unsigned)pxa_ep->reg_udccsr,
2133 + (unsigned)pxa_ep->reg_udcbcr,
2134 + (unsigned)pxa_ep->reg_udcdr,
2135 + (unsigned)pxa_ep->reg_udccr);
2136 +#endif
2137 + /* Configure UDCCR */
2138 + tmp = 0;
2139 + tmp |= (pxa_ep->config << UDCCONR_CN_S) & UDCCONR_CN;
2140 + tmp |= (pxa_ep->interface << UDCCONR_IN_S) & UDCCONR_IN;
2141 + tmp |= (pxa_ep->aisn << UDCCONR_AISN_S) & UDCCONR_AISN;
2142 + tmp |= (desc->bEndpointAddress << UDCCONR_EN_S) & UDCCONR_EN;
2143 + tmp |= (pxa_ep->ep_type << UDCCONR_ET_S) & UDCCONR_ET;
2144 + tmp |= (pxa_ep->dir_in) ? UDCCONR_ED : 0;
2145 + tmp |= (min(pxa_ep->fifo_size, (unsigned)desc->wMaxPacketSize) \
2146 + << UDCCONR_MPS_S ) & UDCCONR_MPS;
2147 + tmp |= UDCCONR_DE | UDCCONR_EE;
2148 +// tmp |= UDCCONR_EE;
2149 +
2150 + *pxa_ep->reg_udccr = tmp;
2151 +
2152 +#ifdef USE_DMA
2153 + /* Only BULK use DMA */
2154 + if ((pxa_ep->ep_type & USB_ENDPOINT_XFERTYPE_MASK)\
2155 + == USB_ENDPOINT_XFER_BULK)
2156 + *pxa_ep->reg_udccsr = UDCCSR_DME;
2157 +#endif
2158 +
2159 + DMSG("UDCCR: 0x%p is 0x%x\n", pxa_ep->reg_udccr,*pxa_ep->reg_udccr);
2160 +
2161 + /* Fill ep name*/
2162 + name = kmalloc(NAME_SIZE, GFP_KERNEL);
2163 + if (!name) {
2164 + printk(KERN_ERR "%s: Error\n", __FUNCTION__);
2165 + return NULL;
2166 + }
2167 +
2168 + switch (pxa_ep->ep_type) {
2169 + case USB_ENDPOINT_XFER_BULK:
2170 + sprintf(name, "Bulk-%s-%d", (pxa_ep->dir_in ? "in":"out"), i);
2171 + break;
2172 + case USB_ENDPOINT_XFER_INT:
2173 + sprintf(name, "Interrupt-%s-%d", (pxa_ep->dir_in ? \
2174 + "in":"out"), i);
2175 + break;
2176 + default:
2177 + sprintf(name, "endpoint-%s-%d", (pxa_ep->dir_in ? \
2178 + "in":"out"), i);
2179 + break;
2180 + }
2181 + ep->name = name;
2182 +
2183 + ep->ops = &pxa27x_ep_ops;
2184 + ep->maxpacket = min((ushort)pxa_ep->fifo_size, desc->wMaxPacketSize);
2185 +
2186 + list_add_tail (&ep->ep_list, &gadget->ep_list);
2187 + return ep;
2188 +}
2189 +
2190 +EXPORT_SYMBOL(pxa27x_ep_config);
2191 +
2192 +/*-------------------------------------------------------------------------*/
2193 +
2194 +static void nop_release (struct device *dev)
2195 +{
2196 + DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2197 +}
2198 +
2199 +/* this uses load-time allocation and initialization (instead of
2200 + * doing it at run-time) to save code, eliminate fault paths, and
2201 + * be more obviously correct.
2202 + */
2203 +static struct pxa27x_udc memory = {
2204 + .gadget = {
2205 + .ops = &pxa27x_udc_ops,
2206 + .ep0 = &memory.ep[0].ep,
2207 + .name = driver_name,
2208 + .dev = {
2209 + .bus_id = "gadget",
2210 + .release = nop_release,
2211 + },
2212 + },
2213 +
2214 + /* control endpoint */
2215 + .ep[0] = {
2216 + .ep = {
2217 + .name = ep0name,
2218 + .ops = &pxa27x_ep_ops,
2219 + .maxpacket = EP0_FIFO_SIZE,
2220 + },
2221 + .dev = &memory,
2222 + .reg_udccsr = &UDCCSR0,
2223 + .reg_udcdr = &UDCDR0,
2224 + }
2225 +};
2226 +
2227 +#define CP15R0_VENDOR_MASK 0xffffe000
2228 +
2229 +#define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/xscale */
2230 +
2231 +/*
2232 + * probe - binds to the platform device
2233 + */
2234 +static int __init pxa27x_udc_probe(struct platform_device *_dev)
2235 +{
2236 + struct pxa27x_udc *dev = &memory;
2237 + int retval;
2238 + u32 chiprev;
2239 +
2240 + /* insist on Intel/ARM/XScale */
2241 + asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2242 + if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2243 + printk(KERN_ERR "%s: not XScale!\n", driver_name);
2244 + return -ENODEV;
2245 + }
2246 + /* other non-static parts of init */
2247 + dev->dev = &_dev->dev;
2248 + dev->mach = _dev->dev.platform_data;
2249 +
2250 + init_timer(&dev->timer);
2251 + dev->timer.function = udc_watchdog;
2252 + dev->timer.data = (unsigned long) dev;
2253 +
2254 + device_initialize(&dev->gadget.dev);
2255 + dev->gadget.dev.parent = &_dev->dev;
2256 + dev->gadget.dev.dma_mask = _dev->dev.dma_mask;
2257 +
2258 + the_controller = dev;
2259 + platform_set_drvdata(_dev, dev);
2260 +
2261 + udc_disable(dev);
2262 + udc_init_ep(dev);
2263 + udc_reinit(dev);
2264 +
2265 + /* irq setup after old hardware state is cleaned up */
2266 + retval = request_irq(IRQ_USB, pxa27x_udc_irq,
2267 + SA_INTERRUPT, driver_name, dev);
2268 + if (retval != 0) {
2269 + printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2270 + driver_name, IRQ_USB, retval);
2271 + return -EBUSY;
2272 + }
2273 + dev->got_irq = 1;
2274 +
2275 + create_proc_files();
2276 +
2277 + return 0;
2278 +}
2279 +
2280 +static int __exit pxa27x_udc_remove(struct platform_device *_dev)
2281 +{
2282 + struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2283 +
2284 + udc_disable(dev);
2285 + remove_proc_files();
2286 + usb_gadget_unregister_driver(dev->driver);
2287 +
2288 + if (dev->got_irq) {
2289 + free_irq(IRQ_USB, dev);
2290 + dev->got_irq = 0;
2291 + }
2292 + if (machine_is_lubbock() && dev->got_disc) {
2293 + free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2294 + dev->got_disc = 0;
2295 + }
2296 + platform_set_drvdata(_dev, 0);
2297 + the_controller = 0;
2298 + return 0;
2299 +}
2300 +
2301 +#ifdef CONFIG_PM
2302 +static void pxa27x_udc_shutdown(struct platform_device *_dev)
2303 +{
2304 + struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2305 +
2306 + udc_disable(dev);
2307 +}
2308 +
2309 +static int pxa27x_udc_suspend(struct platform_device *_dev, pm_message_t state)
2310 +{
2311 + int i;
2312 + struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2313 +
2314 + DMSG("%s is called\n", __FUNCTION__);
2315 + dev->udccsr0 = UDCCSR0;
2316 + for(i=1; (i<UDC_EP_NUM); i++) {
2317 + if (dev->ep[i].assigned) {
2318 + struct pxa27x_ep *ep = &dev->ep[i];
2319 +
2320 + ep->udccsr_value = *ep->reg_udccsr;
2321 + ep->udccr_value = *ep->reg_udccr;
2322 + DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n",
2323 + i, *ep->reg_udccsr, *ep->reg_udccr);
2324 + }
2325 + }
2326 +
2327 + udc_clear_mask_UDCCR(UDCCR_UDE);
2328 + pxa_set_cken(CKEN11_USB, 0);
2329 + // MST_MSCWR2 |= MST_MSCWR2_nUSBC_SC;
2330 +
2331 + return 0;
2332 +}
2333 +
2334 +static int pxa27x_udc_resume(struct platform_device *_dev)
2335 +{
2336 + int i;
2337 + struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2338 +
2339 + DMSG("%s is called\n", __FUNCTION__);
2340 +
2341 + UDCCSR0 = dev->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME);
2342 + for (i=1; i < UDC_EP_NUM; i++) {
2343 + if (dev->ep[i].assigned) {
2344 + struct pxa27x_ep *ep = &dev->ep[i];
2345 +
2346 + *ep->reg_udccsr = ep->udccsr_value;
2347 + *ep->reg_udccr = ep->udccr_value;
2348 + DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n",
2349 + i, *ep->reg_udccsr, *ep->reg_udccr);
2350 + }
2351 + }
2352 + udc_enable(dev);
2353 + /* OTGPH bit is set when sleep mode is entered.
2354 + * it indicates that OTG pad is retaining its state.
2355 + * Upon exit from sleep mode and before clearing OTGPH,
2356 + * Software must configure the USB OTG pad, UDC, and UHC
2357 + * to the state they were in before entering sleep mode.*/
2358 + PSSR |= PSSR_OTGPH;
2359 + return 0;
2360 +}
2361 +#endif
2362 +
2363 +/*-------------------------------------------------------------------------*/
2364 +
2365 +static struct platform_driver udc_driver = {
2366 + .driver = {
2367 + .name = "pxa2xx-udc",
2368 + },
2369 + .probe = pxa27x_udc_probe,
2370 + .remove = __exit_p(pxa27x_udc_remove),
2371 +
2372 +#ifdef CONFIG_PM
2373 + // FIXME power management support
2374 + .shutdown = pxa27x_udc_shutdown,
2375 + .suspend = pxa27x_udc_suspend,
2376 + .resume = pxa27x_udc_resume
2377 +#endif
2378 +};
2379 +
2380 +static int __init udc_init(void)
2381 +{
2382 + printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2383 + return platform_driver_register(&udc_driver);
2384 +}
2385 +module_init(udc_init);
2386 +
2387 +static void __exit udc_exit(void)
2388 +{
2389 + platform_driver_unregister(&udc_driver);
2390 +}
2391 +module_exit(udc_exit);
2392 +
2393 +MODULE_DESCRIPTION(DRIVER_DESC);
2394 +MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2395 +MODULE_LICENSE("GPL");
2396 +
2397 --- /dev/null
2398 +++ b/drivers/usb/gadget/pxa27x_udc.h
2399 @@ -0,0 +1,332 @@
2400 +/*
2401 + * linux/drivers/usb/gadget/pxa27x_udc.h
2402 + * Intel PXA27x on-chip full speed USB device controller
2403 + *
2404 + * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
2405 + * Copyright (C) 2003 David Brownell
2406 + * Copyright (C) 2004 Intel Corporation
2407 + *
2408 + * This program is free software; you can redistribute it and/or modify
2409 + * it under the terms of the GNU General Public License as published by
2410 + * the Free Software Foundation; either version 2 of the License, or
2411 + * (at your option) any later version.
2412 + *
2413 + * This program is distributed in the hope that it will be useful,
2414 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2415 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2416 + * GNU General Public License for more details.
2417 + *
2418 + * You should have received a copy of the GNU General Public License
2419 + * along with this program; if not, write to the Free Software
2420 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2421 + */
2422 +
2423 +#ifndef __LINUX_USB_GADGET_PXA27X_H
2424 +#define __LINUX_USB_GADGET_PXA27X_H
2425 +
2426 +#include <linux/types.h>
2427 +
2428 +struct pxa27x_udc;
2429 +
2430 +struct pxa27x_ep {
2431 + struct usb_ep ep;
2432 + struct pxa27x_udc *dev;
2433 +
2434 + const struct usb_endpoint_descriptor *desc;
2435 + struct list_head queue;
2436 + unsigned long pio_irqs;
2437 + unsigned long dma_irqs;
2438 +
2439 + int dma;
2440 + unsigned fifo_size;
2441 + unsigned ep_num;
2442 + unsigned ep_type;
2443 +
2444 + unsigned stopped : 1;
2445 + unsigned dma_con : 1;
2446 + unsigned dir_in : 1;
2447 + unsigned assigned : 1;
2448 +
2449 + unsigned config;
2450 + unsigned interface;
2451 + unsigned aisn;
2452 + /* UDCCSR = UDC Control/Status Register for this EP
2453 + * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
2454 + * UDCDR = UDC Endpoint Data Register (the fifo)
2455 + * UDCCR = UDC Endpoint Configuration Registers
2456 + * DRCM = DMA Request Channel Map
2457 + */
2458 + volatile u32 *reg_udccsr;
2459 + volatile u32 *reg_udcbcr;
2460 + volatile u32 *reg_udcdr;
2461 + volatile u32 *reg_udccr;
2462 +#ifdef USE_DMA
2463 + volatile u32 *reg_drcmr;
2464 +#define drcmr(n) .reg_drcmr = & DRCMR ## n ,
2465 +#else
2466 +#define drcmr(n)
2467 +#endif
2468 +
2469 +#ifdef CONFIG_PM
2470 + unsigned udccsr_value;
2471 + unsigned udccr_value;
2472 +#endif
2473 +};
2474 +
2475 +struct pxa27x_request {
2476 + struct usb_request req;
2477 + struct list_head queue;
2478 +};
2479 +
2480 +enum ep0_state {
2481 + EP0_IDLE,
2482 + EP0_IN_DATA_PHASE,
2483 + EP0_OUT_DATA_PHASE,
2484 +// EP0_END_XFER,
2485 + EP0_STALL,
2486 + EP0_NO_ACTION
2487 +};
2488 +
2489 +#define EP0_FIFO_SIZE ((unsigned)16)
2490 +#define BULK_FIFO_SIZE ((unsigned)64)
2491 +#define ISO_FIFO_SIZE ((unsigned)256)
2492 +#define INT_FIFO_SIZE ((unsigned)8)
2493 +
2494 +struct udc_stats {
2495 + struct ep0stats {
2496 + unsigned long ops;
2497 + unsigned long bytes;
2498 + } read, write;
2499 + unsigned long irqs;
2500 +};
2501 +
2502 +#ifdef CONFIG_USB_PXA27X_SMALL
2503 +/* when memory's tight, SMALL config saves code+data. */
2504 +//#undef USE_DMA
2505 +//#define UDC_EP_NUM 3
2506 +#endif
2507 +
2508 +#ifndef UDC_EP_NUM
2509 +#define UDC_EP_NUM 24
2510 +#endif
2511 +
2512 +struct pxa27x_udc {
2513 + struct usb_gadget gadget;
2514 + struct usb_gadget_driver *driver;
2515 +
2516 + enum ep0_state ep0state;
2517 + struct udc_stats stats;
2518 + unsigned got_irq : 1,
2519 + got_disc : 1,
2520 + has_cfr : 1,
2521 + req_pending : 1,
2522 + req_std : 1,
2523 + req_config : 1;
2524 +
2525 +#define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
2526 + struct timer_list timer;
2527 +
2528 + struct device *dev;
2529 + struct pxa2xx_udc_mach_info *mach;
2530 + u64 dma_mask;
2531 + struct pxa27x_ep ep [UDC_EP_NUM];
2532 +
2533 + unsigned configuration,
2534 + interface,
2535 + alternate;
2536 +#ifdef CONFIG_PM
2537 + unsigned udccsr0;
2538 +#endif
2539 +};
2540 +
2541 +/*-------------------------------------------------------------------------*/
2542 +#if 0
2543 +#ifdef DEBUG
2544 +#define HEX_DISPLAY(n) do { \
2545 + if (machine_is_mainstone())\
2546 + { MST_LEDDAT1 = (n); } \
2547 + } while(0)
2548 +
2549 +#define HEX_DISPLAY1(n) HEX_DISPLAY(n)
2550 +
2551 +#define HEX_DISPLAY2(n) do { \
2552 + if (machine_is_mainstone()) \
2553 + { MST_LEDDAT2 = (n); } \
2554 + } while(0)
2555 +
2556 +#endif /* DEBUG */
2557 +#endif
2558 +/*-------------------------------------------------------------------------*/
2559 +
2560 +/* LEDs are only for debug */
2561 +#ifndef HEX_DISPLAY
2562 +#define HEX_DISPLAY(n) do {} while(0)
2563 +#endif
2564 +
2565 +#ifndef LED_CONNECTED_ON
2566 +#define LED_CONNECTED_ON do {} while(0)
2567 +#define LED_CONNECTED_OFF do {} while(0)
2568 +#endif
2569 +#ifndef LED_EP0_ON
2570 +#define LED_EP0_ON do {} while (0)
2571 +#define LED_EP0_OFF do {} while (0)
2572 +#endif
2573 +
2574 +static struct pxa27x_udc *the_controller;
2575 +
2576 +#if 0
2577 +/*-------------------------------------------------------------------------*/
2578 +
2579 +
2580 +/* one GPIO should be used to detect host disconnect */
2581 +static inline int is_usb_connected(void)
2582 +{
2583 + if (!the_controller->mach->udc_is_connected)
2584 + return 1;
2585 + return the_controller->mach->udc_is_connected();
2586 +}
2587 +
2588 +/* one GPIO should force the host to see this device (or not) */
2589 +static inline void make_usb_disappear(void)
2590 +{
2591 + if (!the_controller->mach->udc_command)
2592 + return;
2593 + the_controller->mach->udc_command(PXA27X_UDC_CMD_DISCONNECT);
2594 +}
2595 +
2596 +static inline void let_usb_appear(void)
2597 +{
2598 + if (!the_controller->mach->udc_command)
2599 + return;
2600 + the_controller->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
2601 +}
2602 +#endif
2603 +
2604 +/*-------------------------------------------------------------------------*/
2605 +
2606 +/*
2607 + * Debugging support vanishes in non-debug builds. DBG_NORMAL should be
2608 + * mostly silent during normal use/testing, with no timing side-effects.
2609 + */
2610 +#define DBG_NORMAL 1 /* error paths, device state transitions */
2611 +#define DBG_VERBOSE 2 /* add some success path trace info */
2612 +#define DBG_NOISY 3 /* ... even more: request level */
2613 +#define DBG_VERY_NOISY 4 /* ... even more: packet level */
2614 +
2615 +#ifdef DEBUG
2616 +
2617 +static const char *state_name[] = {
2618 + "EP0_IDLE",
2619 + "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
2620 + "EP0_END_XFER", "EP0_STALL"
2621 +};
2622 +
2623 +#define DMSG(stuff...) printk(KERN_ERR "udc: " stuff)
2624 +
2625 +#ifdef VERBOSE
2626 +# define UDC_DEBUG DBG_VERBOSE
2627 +#else
2628 +# define UDC_DEBUG DBG_NORMAL
2629 +#endif
2630 +
2631 +static void __attribute__ ((__unused__))
2632 +dump_udccr(const char *label)
2633 +{
2634 + u32 udccr = UDCCR;
2635 + DMSG("%s 0x%08x =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n",
2636 + label, udccr,
2637 + (udccr & UDCCR_OEN) ? " oen":"",
2638 + (udccr & UDCCR_AALTHNP) ? " aalthnp":"",
2639 + (udccr & UDCCR_AHNP) ? " rem" : "",
2640 + (udccr & UDCCR_BHNP) ? " rstir" : "",
2641 + (udccr & UDCCR_DWRE) ? " dwre" : "",
2642 + (udccr & UDCCR_SMAC) ? " smac" : "",
2643 + (udccr & UDCCR_EMCE) ? " emce" : "",
2644 + (udccr & UDCCR_UDR) ? " udr" : "",
2645 + (udccr & UDCCR_UDA) ? " uda" : "",
2646 + (udccr & UDCCR_UDE) ? " ude" : "",
2647 + (udccr & UDCCR_ACN) >> UDCCR_ACN_S,
2648 + (udccr & UDCCR_AIN) >> UDCCR_AIN_S,
2649 + (udccr & UDCCR_AAISN)>> UDCCR_AAISN_S );
2650 +}
2651 +
2652 +static void __attribute__ ((__unused__))
2653 +dump_udccsr0(const char *label)
2654 +{
2655 + u32 udccsr0 = UDCCSR0;
2656 +
2657 + DMSG("%s %s 0x%08x =%s%s%s%s%s%s%s\n",
2658 + label, state_name[the_controller->ep0state], udccsr0,
2659 + (udccsr0 & UDCCSR0_SA) ? " sa" : "",
2660 + (udccsr0 & UDCCSR0_RNE) ? " rne" : "",
2661 + (udccsr0 & UDCCSR0_FST) ? " fst" : "",
2662 + (udccsr0 & UDCCSR0_SST) ? " sst" : "",
2663 + (udccsr0 & UDCCSR0_DME) ? " dme" : "",
2664 + (udccsr0 & UDCCSR0_IPR) ? " ipr" : "",
2665 + (udccsr0 & UDCCSR0_OPC) ? " opr" : "");
2666 +}
2667 +
2668 +static void __attribute__ ((__unused__))
2669 +dump_state(struct pxa27x_udc *dev)
2670 +{
2671 + unsigned i;
2672 +
2673 + DMSG("%s, udcicr %02X.%02X, udcsir %02X.%02x, udcfnr %02X\n",
2674 + state_name[dev->ep0state],
2675 + UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR);
2676 + dump_udccr("udccr");
2677 +
2678 + if (!dev->driver) {
2679 + DMSG("no gadget driver bound\n");
2680 + return;
2681 + } else
2682 + DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
2683 +
2684 +
2685 + dump_udccsr0 ("udccsr0");
2686 + DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
2687 + dev->stats.write.bytes, dev->stats.write.ops,
2688 + dev->stats.read.bytes, dev->stats.read.ops);
2689 +
2690 + for (i = 1; i < UDC_EP_NUM; i++) {
2691 + if (dev->ep [i].desc == 0)
2692 + continue;
2693 + DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccsr);
2694 + }
2695 +}
2696 +
2697 +#if 0
2698 +static void dump_regs(u8 ep)
2699 +{
2700 + DMSG("EP:%d UDCCSR:0x%08x UDCBCR:0x%08x\n UDCCR:0x%08x\n",
2701 + ep,UDCCSN(ep), UDCBCN(ep), UDCCN(ep));
2702 +}
2703 +static void dump_req (struct pxa27x_request *req)
2704 +{
2705 + struct usb_request *r = &req->req;
2706 +
2707 + DMSG("%s: buf:0x%08x length:%d dma:0x%08x actual:%d\n",
2708 + __FUNCTION__, (unsigned)r->buf, r->length,
2709 + r->dma, r->actual);
2710 +}
2711 +#endif
2712 +
2713 +#else
2714 +
2715 +#define DMSG(stuff...) do{}while(0)
2716 +
2717 +#define dump_udccr(x) do{}while(0)
2718 +#define dump_udccsr0(x) do{}while(0)
2719 +#define dump_state(x) do{}while(0)
2720 +
2721 +#define UDC_DEBUG ((unsigned)0)
2722 +
2723 +#endif
2724 +
2725 +#define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
2726 +
2727 +#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
2728 +#define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
2729 +
2730 +
2731 +#endif /* __LINUX_USB_GADGET_PXA27X_H */
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