target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #ifndef __AG71XX_H
  15 #define __AG71XX_H
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/types.h>
  21 #include <linux/random.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/phy.h>
  28 #include <linux/skbuff.h>
  29 #include <linux/dma-mapping.h>
  30
  31 #include <linux/bitops.h>
  32
  33 #include <asm/mach-ar71xx/ar71xx.h>
  34 #include <asm/mach-ar71xx/platform.h>
  35
  36 #define ETH_FCS_LEN     4
  37
  38 #define AG71XX_DRV_NAME         "ag71xx"
  39 #define AG71XX_DRV_VERSION      "0.3.10"
  40
  41 #define AG71XX_NAPI_TX          1
  42
  43 #define AG71XX_NAPI_WEIGHT      64
  44
  45 #define AG71XX_INT_ERR  (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  46 #define AG71XX_INT_TX   (AG71XX_INT_TX_PS)
  47 #define AG71XX_INT_RX   (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  48
  49 #ifdef AG71XX_NAPI_TX
  50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  52 #else
  53 #define AG71XX_INT_POLL (AG71XX_INT_RX)
  54 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
  55 #endif
  56
  57 #define AG71XX_TX_FIFO_LEN      2048
  58 #define AG71XX_TX_MTU_LEN       1536
  59 #define AG71XX_RX_PKT_RESERVE   64
  60 #define AG71XX_RX_PKT_SIZE      \
  61         (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
  62
  63 #define AG71XX_TX_RING_SIZE     64
  64 #define AG71XX_TX_THRES_STOP    (AG71XX_TX_RING_SIZE - 4)
  65 #define AG71XX_TX_THRES_WAKEUP  \
  66                 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
  67
  68 #define AG71XX_RX_RING_SIZE     128
  69
  70 #undef DEBUG
  71 #ifdef DEBUG
  72 #define DBG(fmt, args...)       printk(KERN_DEBUG fmt, ## args)
  73 #else
  74 #define DBG(fmt, args...)       do {} while (0)
  75 #endif
  76
  77 #define ag71xx_assert(_cond)                                            \
  78 do {                                                                    \
  79         if (_cond)                                                      \
  80                 break;                                                  \
  81         printk("%s,%d: assertion failed\n", __FILE__, __LINE__);        \
  82         BUG();                                                          \
  83 } while (0)
  84
  85 struct ag71xx_desc {
  86         u32     data;
  87         u32     ctrl;
  88 #define DESC_EMPTY      BIT(31)
  89 #define DESC_MORE       BIT(24)
  90 #define DESC_PKTLEN_M   0x1fff
  91         u32     next;
  92 };
  93
  94 struct ag71xx_buf {
  95         struct sk_buff  *skb;
  96 };
  97
  98 struct ag71xx_ring {
  99         struct ag71xx_buf       *buf;
 100         struct ag71xx_desc      *descs;
 101         dma_addr_t              descs_dma;
 102         unsigned int            curr;
 103         unsigned int            dirty;
 104         unsigned int            size;
 105 };
 106
 107 struct ag71xx {
 108         void __iomem            *mac_base;
 109         void __iomem            *mii_ctrl;
 110
 111         spinlock_t              lock;
 112         struct platform_device  *pdev;
 113         struct net_device       *dev;
 114         struct napi_struct      napi;
 115
 116         struct ag71xx_ring      rx_ring;
 117         struct ag71xx_ring      tx_ring;
 118
 119         struct phy_device       *phy_dev;
 120         struct mii_bus          mii_bus;
 121
 122         unsigned int            link;
 123         unsigned int            speed;
 124         int                     duplex;
 125 };
 126
 127 extern struct ethtool_ops ag71xx_ethtool_ops;
 128
 129 extern int ag71xx_mdio_init(struct ag71xx *ag, int id);
 130 extern void ag71xx_mdio_cleanup(struct ag71xx *ag);
 131 extern int ag71xx_mii_peek(struct ag71xx *ag);
 132 extern void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if);
 133 extern void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, unsigned int speed);
 134 extern void ag71xx_link_update(struct ag71xx *ag);
 135
 136 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 137 {
 138         return ag->pdev->dev.platform_data;
 139 }
 140
 141 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 142 {
 143         __raw_writel(value, ag->mac_base + reg);
 144 }
 145
 146 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 147 {
 148         return __raw_readl(ag->mac_base + reg);
 149 }
 150
 151 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 152 {
 153         void __iomem *r = ag->mac_base + reg;
 154
 155         __raw_writel(__raw_readl(r) | mask, r);
 156 }
 157
 158 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 159 {
 160         void __iomem *r = ag->mac_base + reg;
 161
 162         __raw_writel(__raw_readl(r) & ~mask, r);
 163 }
 164
 165 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
 166 {
 167         return ((desc->ctrl & DESC_EMPTY) != 0);
 168 }
 169
 170 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 171 {
 172         return (desc->ctrl & DESC_PKTLEN_M);
 173 }
 174
 175 /* Register offsets */
 176 #define AG71XX_REG_MAC_CFG1     0x0000
 177 #define AG71XX_REG_MAC_CFG2     0x0004
 178 #define AG71XX_REG_MAC_IPG      0x0008
 179 #define AG71XX_REG_MAC_HDX      0x000c
 180 #define AG71XX_REG_MAC_MFL      0x0010
 181 #define AG71XX_REG_MII_CFG      0x0020
 182 #define AG71XX_REG_MII_CMD      0x0024
 183 #define AG71XX_REG_MII_ADDR     0x0028
 184 #define AG71XX_REG_MII_CTRL     0x002c
 185 #define AG71XX_REG_MII_STATUS   0x0030
 186 #define AG71XX_REG_MII_IND      0x0034
 187 #define AG71XX_REG_MAC_IFCTL    0x0038
 188 #define AG71XX_REG_MAC_ADDR1    0x0040
 189 #define AG71XX_REG_MAC_ADDR2    0x0044
 190 #define AG71XX_REG_FIFO_CFG0    0x0048
 191 #define AG71XX_REG_FIFO_CFG1    0x004c
 192 #define AG71XX_REG_FIFO_CFG2    0x0050
 193 #define AG71XX_REG_FIFO_CFG3    0x0054
 194 #define AG71XX_REG_FIFO_CFG4    0x0058
 195 #define AG71XX_REG_FIFO_CFG5    0x005c
 196 #define AG71XX_REG_FIFO_RAM0    0x0060
 197 #define AG71XX_REG_FIFO_RAM1    0x0064
 198 #define AG71XX_REG_FIFO_RAM2    0x0068
 199 #define AG71XX_REG_FIFO_RAM3    0x006c
 200 #define AG71XX_REG_FIFO_RAM4    0x0070
 201 #define AG71XX_REG_FIFO_RAM5    0x0074
 202 #define AG71XX_REG_FIFO_RAM6    0x0078
 203 #define AG71XX_REG_FIFO_RAM7    0x007c
 204
 205 #define AG71XX_REG_TX_CTRL      0x0180
 206 #define AG71XX_REG_TX_DESC      0x0184
 207 #define AG71XX_REG_TX_STATUS    0x0188
 208 #define AG71XX_REG_RX_CTRL      0x018c
 209 #define AG71XX_REG_RX_DESC      0x0190
 210 #define AG71XX_REG_RX_STATUS    0x0194
 211 #define AG71XX_REG_INT_ENABLE   0x0198
 212 #define AG71XX_REG_INT_STATUS   0x019c
 213
 214 #define MAC_CFG1_TXE            BIT(0)
 215 #define MAC_CFG1_STX            BIT(1)
 216 #define MAC_CFG1_RXE            BIT(2)
 217 #define MAC_CFG1_SRX            BIT(3)
 218 #define MAC_CFG1_LB             BIT(8)
 219 #define MAC_CFG1_SR             BIT(31)
 220
 221 #define MAC_CFG2_FDX            BIT(0)
 222 #define MAC_CFG2_CRC_EN         BIT(1)
 223 #define MAC_CFG2_PAD_CRC_EN     BIT(2)
 224 #define MAC_CFG2_LEN_CHECK      BIT(4)
 225 #define MAC_CFG2_HUGE_FRAME_EN  BIT(5)
 226 #define MAC_CFG2_IF_1000        BIT(9)
 227 #define MAC_CFG2_IF_10_100      BIT(8)
 228
 229 #define AG71XX_INT_TX_PS        BIT(0)
 230 #define AG71XX_INT_TX_UR        BIT(1)
 231 #define AG71XX_INT_TX_BE        BIT(3)
 232 #define AG71XX_INT_RX_PR        BIT(4)
 233 #define AG71XX_INT_RX_OF        BIT(6)
 234 #define AG71XX_INT_RX_BE        BIT(7)
 235
 236 #define MAC_IFCTL_SPEED         BIT(16)
 237
 238 #define MII_CFG_CLK_DIV_4       0
 239 #define MII_CFG_CLK_DIV_6       2
 240 #define MII_CFG_CLK_DIV_8       3
 241 #define MII_CFG_CLK_DIV_10      4
 242 #define MII_CFG_CLK_DIV_14      5
 243 #define MII_CFG_CLK_DIV_20      6
 244 #define MII_CFG_CLK_DIV_28      7
 245
 246 #define MII_CMD_WRITE           0x0
 247 #define MII_CMD_READ            0x1
 248 #define MII_ADDR_S              8
 249 #define MII_IND_BUSY            BIT(0)
 250 #define MII_IND_INVALID         BIT(2)
 251
 252 #define TX_CTRL_TXE             BIT(0)
 253
 254 #define TX_STATUS_PS            BIT(0)
 255 #define TX_STATUS_UR            BIT(1)
 256 #define TX_STATUS_BE            BIT(3)
 257
 258 #define RX_CTRL_RXE             BIT(0)
 259
 260 #define RX_STATUS_PR            BIT(0)
 261 #define RX_STATUS_OF            BIT(1)
 262 #define RX_STATUS_BE            BIT(3)
 263
 264 #define FIFO_CFG5_BYTE_PER_CLK  BIT(19)
 265
 266 #define MII_CTRL_SPEED_S        4
 267 #define MII_CTRL_SPEED_M        3
 268 #define MII_CTRL_SPEED_10       0
 269 #define MII_CTRL_SPEED_100      1
 270 #define MII_CTRL_SPEED_1000     2
 271
 272 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
 273 {
 274         ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
 275 }
 276
 277 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 278 {
 279         ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
 280 }
 281
 282 #endif /* _AG71XX_H */