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[openwrt.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
40
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
45
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
49
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
52
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
58
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
63
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
67
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_CTRL_REG 0x11F0
73 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
74 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
75 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
76
77 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
78 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
79 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
80
81
82 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
83 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
84 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
85 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
86 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
87
88
89 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
90 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
91
92 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123
124 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_UNKNOWN | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_UNKNOWN)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
146 RTL8366_PORT_CPU)
147
148 struct rtl8366s {
149 struct device *parent;
150 struct rtl8366_smi smi;
151 struct switch_dev dev;
152 char buf[4096];
153 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
154 struct dentry *debugfs_root;
155 #endif
156 };
157
158 struct rtl8366s_vlanconfig {
159 u16 reserved2:1;
160 u16 priority:3;
161 u16 vid:12;
162
163 u16 reserved1:1;
164 u16 fid:3;
165 u16 untag:6;
166 u16 member:6;
167 };
168
169 struct rtl8366s_vlan4kentry {
170 u16 reserved1:4;
171 u16 vid:12;
172
173 u16 reserved2:1;
174 u16 fid:3;
175 u16 untag:6;
176 u16 member:6;
177 };
178
179 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
180 u16 g_dbg_reg;
181 #endif
182
183 struct mib_counter {
184 unsigned offset;
185 unsigned length;
186 const char *name;
187 };
188
189 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
190 { 0, 4, "IfInOctets " },
191 { 4, 4, "EtherStatsOctets " },
192 { 8, 2, "EtherStatsUnderSizePkts " },
193 { 10, 2, "EtherFregament " },
194 { 12, 2, "EtherStatsPkts64Octets " },
195 { 14, 2, "EtherStatsPkts65to127Octets " },
196 { 16, 2, "EtherStatsPkts128to255Octets " },
197 { 18, 2, "EtherStatsPkts256to511Octets " },
198 { 20, 2, "EtherStatsPkts512to1023Octets " },
199 { 22, 2, "EtherStatsPkts1024to1518Octets " },
200 { 24, 2, "EtherOversizeStats " },
201 { 26, 2, "EtherStatsJabbers " },
202 { 28, 2, "IfInUcastPkts " },
203 { 30, 2, "EtherStatsMulticastPkts " },
204 { 32, 2, "EtherStatsBroadcastPkts " },
205 { 34, 2, "EtherStatsDropEvents " },
206 { 36, 2, "Dot3StatsFCSErrors " },
207 { 38, 2, "Dot3StatsSymbolErrors " },
208 { 40, 2, "Dot3InPauseFrames " },
209 { 42, 2, "Dot3ControlInUnknownOpcodes " },
210 { 44, 4, "IfOutOctets " },
211 { 48, 2, "Dot3StatsSingleCollisionFrames " },
212 { 50, 2, "Dot3StatMultipleCollisionFrames " },
213 { 52, 2, "Dot3sDeferredTransmissions " },
214 { 54, 2, "Dot3StatsLateCollisions " },
215 { 56, 2, "EtherStatsCollisions " },
216 { 58, 2, "Dot3StatsExcessiveCollisions " },
217 { 60, 2, "Dot3OutPauseFrames " },
218 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
219 { 64, 2, "Dot1dTpPortInDiscards " },
220 { 66, 2, "IfOutUcastPkts " },
221 { 68, 2, "IfOutMulticastPkts " },
222 { 70, 2, "IfOutBroadcastPkts " },
223 };
224
225 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
226 {
227 return container_of(smi, struct rtl8366s, smi);
228 }
229
230 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
231 {
232 return container_of(sw, struct rtl8366s, dev);
233 }
234
235 static int rtl8366s_reset_chip(struct rtl8366s *rtl)
236 {
237 struct rtl8366_smi *smi = &rtl->smi;
238 int timeout = 10;
239 u32 data;
240
241 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
242 RTL8366_CHIP_CTRL_RESET_HW);
243 do {
244 msleep(1);
245 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
246 return -EIO;
247
248 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
249 break;
250 } while (--timeout);
251
252 if (!timeout) {
253 printk("Timeout waiting for the switch to reset\n");
254 return -EIO;
255 }
256
257 return 0;
258 }
259
260 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
261 u32 phy_no, u32 page, u32 addr, u32 *data)
262 {
263 u32 reg;
264 int ret;
265
266 if (phy_no > RTL8366S_PHY_NO_MAX)
267 return -EINVAL;
268
269 if (page > RTL8366S_PHY_PAGE_MAX)
270 return -EINVAL;
271
272 if (addr > RTL8366S_PHY_ADDR_MAX)
273 return -EINVAL;
274
275 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
276 RTL8366S_PHY_CTRL_READ);
277 if (ret)
278 return ret;
279
280 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
281 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
282 (addr & RTL8366S_PHY_REG_MASK);
283
284 ret = rtl8366_smi_write_reg(smi, reg, 0);
285 if (ret)
286 return ret;
287
288 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
289 if (ret)
290 return ret;
291
292 return 0;
293 }
294
295 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
296 u32 phy_no, u32 page, u32 addr, u32 data)
297 {
298 u32 reg;
299 int ret;
300
301 if (phy_no > RTL8366S_PHY_NO_MAX)
302 return -EINVAL;
303
304 if (page > RTL8366S_PHY_PAGE_MAX)
305 return -EINVAL;
306
307 if (addr > RTL8366S_PHY_ADDR_MAX)
308 return -EINVAL;
309
310 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
311 RTL8366S_PHY_CTRL_WRITE);
312 if (ret)
313 return ret;
314
315 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
316 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
317 (addr & RTL8366S_PHY_REG_MASK);
318
319 ret = rtl8366_smi_write_reg(smi, reg, data);
320 if (ret)
321 return ret;
322
323 return 0;
324 }
325
326 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
327 int port, unsigned long long *val)
328 {
329 struct rtl8366_smi *smi = &rtl->smi;
330 int i;
331 int err;
332 u32 addr, data;
333 u64 mibvalue;
334
335 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
336 return -EINVAL;
337
338 addr = RTL8366S_MIB_COUNTER_BASE +
339 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
340 rtl8366s_mib_counters[counter].offset;
341
342 /*
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
345 */
346 data = 0; /* writing data will be discard by ASIC */
347 err = rtl8366_smi_write_reg(smi, addr, data);
348 if (err)
349 return err;
350
351 /* read MIB control register */
352 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
353 if (err)
354 return err;
355
356 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
357 return -EBUSY;
358
359 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
360 return -EIO;
361
362 mibvalue = 0;
363 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
364 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
365 if (err)
366 return err;
367
368 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
369 }
370
371 *val = mibvalue;
372 return 0;
373 }
374
375 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
376 struct rtl8366s_vlan4kentry *vlan4k)
377 {
378 struct rtl8366_smi *smi = &rtl->smi;
379 int err;
380 u32 data;
381 u16 *tableaddr;
382
383 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
384 vlan4k->vid = vid;
385
386 if (vid >= RTL8366_NUM_VIDS)
387 return -EINVAL;
388
389 tableaddr = (u16 *)vlan4k;
390
391 /* write VID */
392 data = *tableaddr;
393 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
394 if (err)
395 return err;
396
397 /* write table access control word */
398 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
399 RTL8366S_TABLE_VLAN_READ_CTRL);
400 if (err)
401 return err;
402
403 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
404 if (err)
405 return err;
406
407 *tableaddr = data;
408 tableaddr++;
409
410 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
411 &data);
412 if (err)
413 return err;
414
415 *tableaddr = data;
416 vlan4k->vid = vid;
417
418 return 0;
419 }
420
421 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
422 const struct rtl8366s_vlan4kentry *vlan4k)
423 {
424 struct rtl8366_smi *smi = &rtl->smi;
425 int err;
426 u32 data;
427 u16 *tableaddr;
428
429 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
430 vlan4k->member > RTL8366_PORT_ALL ||
431 vlan4k->untag > RTL8366_PORT_ALL ||
432 vlan4k->fid > RTL8366S_FIDMAX)
433 return -EINVAL;
434
435 tableaddr = (u16 *)vlan4k;
436
437 data = *tableaddr;
438
439 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
440 if (err)
441 return err;
442
443 tableaddr++;
444
445 data = *tableaddr;
446
447 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
448 data);
449 if (err)
450 return err;
451
452 /* write table access control word */
453 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
454 RTL8366S_TABLE_VLAN_WRITE_CTRL);
455
456 return err;
457 }
458
459 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
460 struct rtl8366s_vlanconfig *vlanmc)
461 {
462 struct rtl8366_smi *smi = &rtl->smi;
463 int err;
464 u32 addr;
465 u32 data;
466 u16 *tableaddr;
467
468 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
469
470 if (index >= RTL8366_NUM_VLANS)
471 return -EINVAL;
472
473 tableaddr = (u16 *)vlanmc;
474
475 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
476 err = rtl8366_smi_read_reg(smi, addr, &data);
477 if (err)
478 return err;
479
480 *tableaddr = data;
481 tableaddr++;
482
483 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
484 err = rtl8366_smi_read_reg(smi, addr, &data);
485 if (err)
486 return err;
487
488 *tableaddr = data;
489
490 return 0;
491 }
492
493 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
494 const struct rtl8366s_vlanconfig
495 *vlanmc)
496 {
497 struct rtl8366_smi *smi = &rtl->smi;
498 int err;
499 u32 addr;
500 u32 data;
501 u16 *tableaddr;
502
503 if (index >= RTL8366_NUM_VLANS ||
504 vlanmc->vid >= RTL8366_NUM_VIDS ||
505 vlanmc->priority > RTL8366S_PRIORITYMAX ||
506 vlanmc->member > RTL8366_PORT_ALL ||
507 vlanmc->untag > RTL8366_PORT_ALL ||
508 vlanmc->fid > RTL8366S_FIDMAX)
509 return -EINVAL;
510
511 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
512
513 tableaddr = (u16 *)vlanmc;
514 data = *tableaddr;
515
516 err = rtl8366_smi_write_reg(smi, addr, data);
517 if (err)
518 return err;
519
520 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
521
522 tableaddr++;
523 data = *tableaddr;
524
525 err = rtl8366_smi_write_reg(smi, addr, data);
526 if (err)
527 return err;
528
529 return 0;
530 }
531
532 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
533 int *val)
534 {
535 struct rtl8366_smi *smi = &rtl->smi;
536 u32 data;
537 int err;
538
539 if (port >= RTL8366_NUM_PORTS)
540 return -EINVAL;
541
542 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
543 &data);
544 if (err)
545 return err;
546
547 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
548 RTL8366S_PORT_VLAN_CTRL_MASK;
549
550 return 0;
551
552 }
553
554 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
555 int *val)
556 {
557 struct rtl8366s_vlanconfig vlanmc;
558 int err;
559 int index;
560
561 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
562 if (err)
563 return err;
564
565 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
566 if (err)
567 return err;
568
569 *val = vlanmc.vid;
570 return 0;
571 }
572
573 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
574 int index)
575 {
576 struct rtl8366_smi *smi = &rtl->smi;
577 u32 data;
578 int err;
579
580 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
581 return -EINVAL;
582
583 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
584 &data);
585 if (err)
586 return err;
587
588 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
589 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
590 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
591 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
592
593 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
594 data);
595 return err;
596 }
597
598 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
599 {
600 int i;
601 struct rtl8366s_vlanconfig vlanmc;
602 struct rtl8366s_vlan4kentry vlan4k;
603
604 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
605 return -EINVAL;
606
607 /* Updating the 4K entry; lookup it and change the port member set */
608 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
609 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
610 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
611 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
612
613 /*
614 * For the 16 entries more work needs to be done. First see if such
615 * VID is already there and change it
616 */
617 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
618 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
619
620 /* Try to find an existing vid and update port member set */
621 if (val == vlanmc.vid) {
622 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
623 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
624
625 /* Now update PVID register settings */
626 rtl8366s_set_port_vlan_index(rtl, port, i);
627
628 return 0;
629 }
630 }
631
632 /*
633 * PVID could not be found from vlan table. Replace unused (one that
634 * has no member ports) with new one
635 */
636 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
637 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
638
639 /*
640 * See if this vlan member configuration is unused. It is
641 * unused if member set contains no ports or CPU port only
642 */
643 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
644 vlanmc.vid = val;
645 vlanmc.priority = 0;
646 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
647 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
648 vlanmc.fid = 0;
649
650 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
651
652 /* Now update PVID register settings */
653 rtl8366s_set_port_vlan_index(rtl, port, i);
654
655 return 0;
656 }
657 }
658
659 dev_err(rtl->parent,
660 "All 16 vlan member configurations are in use\n");
661
662 return -EINVAL;
663 }
664
665
666 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
667 {
668 struct rtl8366_smi *smi = &rtl->smi;
669 u32 data = 0;
670
671 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
672
673 if (enable)
674 data |= RTL8366_CHIP_CTRL_VLAN;
675 else
676 data &= ~RTL8366_CHIP_CTRL_VLAN;
677
678 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
679 }
680
681 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
682 {
683 struct rtl8366_smi *smi = &rtl->smi;
684 u32 data = 0;
685
686 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
687
688 if (enable)
689 data |= 1;
690 else
691 data &= ~1;
692
693 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
694 }
695
696 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
697 {
698 struct rtl8366s_vlan4kentry vlan4k;
699 struct rtl8366s_vlanconfig vlanmc;
700 int err;
701 int i;
702
703 /* clear 16 VLAN member configuration */
704 vlanmc.vid = 0;
705 vlanmc.priority = 0;
706 vlanmc.member = 0;
707 vlanmc.untag = 0;
708 vlanmc.fid = 0;
709 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
710 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
711 if (err)
712 return err;
713 }
714
715 /* Set a default VLAN with vid 1 to 4K table for all ports */
716 vlan4k.vid = 1;
717 vlan4k.member = RTL8366_PORT_ALL;
718 vlan4k.untag = RTL8366_PORT_ALL;
719 vlan4k.fid = 0;
720 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
721 if (err)
722 return err;
723
724 /* Set all ports PVID to default VLAN */
725 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
726 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
727 if (err)
728 return err;
729 }
730
731 return 0;
732 }
733
734 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
735 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
736 {
737 file->private_data = inode->i_private;
738 return 0;
739 }
740
741 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
742 char __user *user_buf,
743 size_t count, loff_t *ppos)
744 {
745 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
746 int i, j, len = 0;
747 char *buf = rtl->buf;
748
749 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
750 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
751 " "
752 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
753 "Port 4\n");
754
755 for (i = 0; i < 33; ++i) {
756 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
757 i, rtl8366s_mib_counters[i].name);
758 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
759 unsigned long long counter = 0;
760
761 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
762 len += snprintf(buf + len,
763 sizeof(rtl->buf) - len,
764 "[%llu]", counter);
765 else
766 len += snprintf(buf + len,
767 sizeof(rtl->buf) - len,
768 "[error]");
769
770 if (j != RTL8366_NUM_PORTS - 1) {
771 if (counter < 100000)
772 len += snprintf(buf + len,
773 sizeof(rtl->buf) - len,
774 "\t");
775
776 len += snprintf(buf + len,
777 sizeof(rtl->buf) - len,
778 "\t");
779 }
780 }
781 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
782 }
783
784 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
785
786 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
787 }
788
789 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
790 char __user *user_buf,
791 size_t count, loff_t *ppos)
792 {
793 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
794 int i, j, len = 0;
795 char *buf = rtl->buf;
796
797 len += snprintf(buf + len, sizeof(rtl->buf) - len,
798 "VLAN Member Config:\n");
799 len += snprintf(buf + len, sizeof(rtl->buf) - len,
800 "\t id \t vid \t prio \t member \t untag \t fid "
801 "\tports\n");
802
803 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
804 struct rtl8366s_vlanconfig vlanmc;
805
806 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
807
808 len += snprintf(buf + len, sizeof(rtl->buf) - len,
809 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
810 "\t", i, vlanmc.vid, vlanmc.priority,
811 vlanmc.member, vlanmc.untag, vlanmc.fid);
812
813 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
814 int index = 0;
815 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
816 if (index == i)
817 len += snprintf(buf + len,
818 sizeof(rtl->buf) - len,
819 "%d", j);
820 }
821 }
822 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
823 }
824
825 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
826 }
827
828 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
829 char __user *user_buf,
830 size_t count, loff_t *ppos)
831 {
832 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
833 struct rtl8366_smi *smi = &rtl->smi;
834 u32 t, reg = g_dbg_reg;
835 int err, len = 0;
836 char *buf = rtl->buf;
837
838 memset(buf, '\0', sizeof(rtl->buf));
839
840 err = rtl8366_smi_read_reg(smi, reg, &t);
841 if (err) {
842 len += snprintf(buf, sizeof(rtl->buf),
843 "Read failed (reg: 0x%04x)\n", reg);
844 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
845 }
846
847 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
848 reg, t);
849
850 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
851 }
852
853 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
854 const char __user *user_buf,
855 size_t count, loff_t *ppos)
856 {
857 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
858 struct rtl8366_smi *smi = &rtl->smi;
859 unsigned long data;
860 u32 reg = g_dbg_reg;
861 int err;
862 size_t len;
863 char *buf = rtl->buf;
864
865 len = min(count, sizeof(rtl->buf) - 1);
866 if (copy_from_user(buf, user_buf, len)) {
867 dev_err(rtl->parent, "copy from user failed\n");
868 return -EFAULT;
869 }
870
871 buf[len] = '\0';
872 if (len > 0 && buf[len - 1] == '\n')
873 buf[len - 1] = '\0';
874
875
876 if (strict_strtoul(buf, 16, &data)) {
877 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
878 } else {
879 err = rtl8366_smi_write_reg(smi, reg, data);
880 if (err) {
881 dev_err(rtl->parent,
882 "writing reg 0x%04x val 0x%04lx failed\n",
883 reg, data);
884 }
885 }
886
887 return count;
888 }
889
890 static const struct file_operations fops_rtl8366s_regs = {
891 .read = rtl8366s_read_debugfs_reg,
892 .write = rtl8366s_write_debugfs_reg,
893 .open = rtl8366s_debugfs_open,
894 .owner = THIS_MODULE
895 };
896
897 static const struct file_operations fops_rtl8366s_vlan = {
898 .read = rtl8366s_read_debugfs_vlan,
899 .open = rtl8366s_debugfs_open,
900 .owner = THIS_MODULE
901 };
902
903 static const struct file_operations fops_rtl8366s_mibs = {
904 .read = rtl8366s_read_debugfs_mibs,
905 .open = rtl8366s_debugfs_open,
906 .owner = THIS_MODULE
907 };
908
909 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
910 {
911 struct dentry *node;
912 struct dentry *root;
913
914 if (!rtl->debugfs_root)
915 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
916
917 if (!rtl->debugfs_root) {
918 dev_err(rtl->parent, "Unable to create debugfs dir\n");
919 return;
920 }
921 root = rtl->debugfs_root;
922
923 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
924 if (!node) {
925 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
926 "reg");
927 return;
928 }
929
930 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
931 &fops_rtl8366s_regs);
932 if (!node) {
933 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
934 "val");
935 return;
936 }
937
938 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
939 &fops_rtl8366s_vlan);
940 if (!node) {
941 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
942 "vlan");
943 return;
944 }
945
946 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
947 &fops_rtl8366s_mibs);
948 if (!node) {
949 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
950 "mibs");
951 return;
952 }
953 }
954
955 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
956 {
957 if (rtl->debugfs_root) {
958 debugfs_remove_recursive(rtl->debugfs_root);
959 rtl->debugfs_root = NULL;
960 }
961 }
962
963 #else
964 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
965 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
966 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
967
968 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
969 const struct switch_attr *attr,
970 struct switch_val *val)
971 {
972 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
973 struct rtl8366_smi *smi = &rtl->smi;
974 u32 data = 0;
975
976 if (val->value.i == 1) {
977 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
978 data |= (1 << 2);
979 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
980 }
981
982 return 0;
983 }
984
985 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
986 const struct switch_attr *attr,
987 struct switch_val *val)
988 {
989 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
990 struct rtl8366_smi *smi = &rtl->smi;
991 u32 data;
992
993 if (attr->ofs == 1) {
994 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
995
996 if (data & RTL8366_CHIP_CTRL_VLAN)
997 val->value.i = 1;
998 else
999 val->value.i = 0;
1000 } else if (attr->ofs == 2) {
1001 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1002
1003 if (data & 0x0001)
1004 val->value.i = 1;
1005 else
1006 val->value.i = 0;
1007 }
1008
1009 return 0;
1010 }
1011
1012 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1013 const struct switch_attr *attr,
1014 struct switch_val *val)
1015 {
1016 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1017 struct rtl8366_smi *smi = &rtl->smi;
1018 u32 data;
1019
1020 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1021
1022 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1023
1024 return 0;
1025 }
1026
1027 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1028 const struct switch_attr *attr,
1029 struct switch_val *val)
1030 {
1031 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1032 struct rtl8366_smi *smi = &rtl->smi;
1033 u32 data;
1034
1035 if (val->value.i >= 6)
1036 return -EINVAL;
1037
1038 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1039
1040 data &= ~RTL8366_LED_BLINKRATE_MASK;
1041 data |= val->value.i;
1042
1043 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1044
1045 return 0;
1046 }
1047
1048 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1049 const struct switch_attr *attr,
1050 struct switch_val *val)
1051 {
1052 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1053
1054 if (attr->ofs == 1)
1055 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1056 else
1057 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1058 }
1059
1060 static const char *rtl8366s_speed_str(unsigned speed)
1061 {
1062 switch (speed) {
1063 case 0:
1064 return "10baseT";
1065 case 1:
1066 return "100baseT";
1067 case 2:
1068 return "1000baseT";
1069 }
1070
1071 return "unknown";
1072 }
1073
1074 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1075 const struct switch_attr *attr,
1076 struct switch_val *val)
1077 {
1078 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1079 struct rtl8366_smi *smi = &rtl->smi;
1080 u32 len = 0, data = 0;
1081
1082 if (val->port_vlan >= RTL8366_NUM_PORTS)
1083 return -EINVAL;
1084
1085 memset(rtl->buf, '\0', sizeof(rtl->buf));
1086 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1087 (val->port_vlan / 2), &data);
1088
1089 if (val->port_vlan % 2)
1090 data = data >> 8;
1091
1092 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1093 len = snprintf(rtl->buf, sizeof(rtl->buf),
1094 "port:%d link:up speed:%s %s-duplex %s%s%s",
1095 val->port_vlan,
1096 rtl8366s_speed_str(data &
1097 RTL8366S_PORT_STATUS_SPEED_MASK),
1098 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1099 "full" : "half",
1100 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1101 "tx-pause ": "",
1102 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1103 "rx-pause " : "",
1104 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1105 "nway ": "");
1106 } else {
1107 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1108 val->port_vlan);
1109 }
1110
1111 val->value.s = rtl->buf;
1112 val->len = len;
1113
1114 return 0;
1115 }
1116
1117 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1118 const struct switch_attr *attr,
1119 struct switch_val *val)
1120 {
1121 int i;
1122 u32 len = 0;
1123 struct rtl8366s_vlanconfig vlanmc;
1124 struct rtl8366s_vlan4kentry vlan4k;
1125 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1126 char *buf = rtl->buf;
1127
1128 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1129 return -EINVAL;
1130
1131 memset(buf, '\0', sizeof(rtl->buf));
1132
1133 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1134 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1135
1136 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1137 val->port_vlan);
1138
1139 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1140 int index = 0;
1141 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1142 index == val->port_vlan)
1143 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1144 "%d", i);
1145 }
1146 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1147
1148 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1149 "\t\t vid \t prio \t member \t untag \t fid\n");
1150 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1151 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1152 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1153 vlanmc.vid, vlanmc.priority, vlanmc.member,
1154 vlanmc.untag, vlanmc.fid);
1155 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1156 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1157 "%d \t \t 0x%04x \t 0x%04x \t %d",
1158 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1159
1160 val->value.s = buf;
1161 val->len = len;
1162
1163 return 0;
1164 }
1165
1166 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1167 const struct switch_attr *attr,
1168 struct switch_val *val)
1169 {
1170 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1171 struct rtl8366_smi *smi = &rtl->smi;
1172 u32 data = 0;
1173
1174 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1175 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1176 return -EINVAL;
1177
1178 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1179 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1180 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1181 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1182 } else {
1183 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1184 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1185 (val->value.i << (val->port_vlan * 4));
1186 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1187 }
1188
1189 return 0;
1190 }
1191
1192 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1193 const struct switch_attr *attr,
1194 struct switch_val *val)
1195 {
1196 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1197 struct rtl8366_smi *smi = &rtl->smi;
1198 u32 data = 0;
1199
1200 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1201 return -EINVAL;
1202
1203 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1204 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1205
1206 return 0;
1207 }
1208
1209 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1210 const struct switch_attr *attr,
1211 struct switch_val *val)
1212 {
1213 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1214 struct rtl8366_smi *smi = &rtl->smi;
1215 u32 data = 0;
1216
1217 if (val->port_vlan >= RTL8366_NUM_PORTS)
1218 return -EINVAL;
1219
1220 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1221 data |= (1 << (val->port_vlan + 3));
1222 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1223
1224 return 0;
1225 }
1226
1227 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1228 const struct switch_attr *attr,
1229 struct switch_val *val)
1230 {
1231 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1232 int i, len = 0;
1233 unsigned long long counter = 0;
1234 char *buf = rtl->buf;
1235
1236 if (val->port_vlan >= RTL8366_NUM_PORTS)
1237 return -EINVAL;
1238
1239 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1240 "Port %d MIB counters\n",
1241 val->port_vlan);
1242
1243 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1244 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1245 "%d:%s\t", i, rtl8366s_mib_counters[i].name);
1246 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1247 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1248 "[%llu]\n", counter);
1249 else
1250 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1251 "[error]\n");
1252 }
1253
1254 val->value.s = buf;
1255 val->len = len;
1256 return 0;
1257 }
1258
1259 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1260 struct switch_val *val)
1261 {
1262 struct rtl8366s_vlanconfig vlanmc;
1263 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1264 struct switch_port *port;
1265 int i;
1266
1267 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1268 return -EINVAL;
1269
1270 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1271
1272 port = &val->value.ports[0];
1273 val->len = 0;
1274 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1275 if (!(vlanmc.member & BIT(i)))
1276 continue;
1277
1278 port->id = i;
1279 port->flags = (vlanmc.untag & BIT(i)) ?
1280 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1281 val->len++;
1282 port++;
1283 }
1284 return 0;
1285 }
1286
1287 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1288 struct switch_val *val)
1289 {
1290 struct rtl8366s_vlanconfig vlanmc;
1291 struct rtl8366s_vlan4kentry vlan4k;
1292 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1293 struct switch_port *port;
1294 int i;
1295
1296 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1297 return -EINVAL;
1298
1299 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1300 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1301
1302 vlanmc.untag = 0;
1303 vlanmc.member = 0;
1304
1305 port = &val->value.ports[0];
1306 for (i = 0; i < val->len; i++, port++) {
1307 vlanmc.member |= BIT(port->id);
1308
1309 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1310 vlanmc.untag |= BIT(port->id);
1311 }
1312
1313 vlan4k.member = vlanmc.member;
1314 vlan4k.untag = vlanmc.untag;
1315
1316 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1317 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1318 return 0;
1319 }
1320
1321 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1322 {
1323 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1324 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1325 }
1326
1327 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1328 {
1329 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1330 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1331 }
1332
1333 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1334 {
1335 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1336 int err;
1337
1338 err = rtl8366s_reset_chip(rtl);
1339 if (err)
1340 return err;
1341
1342 return rtl8366s_reset_vlan(rtl);
1343 }
1344
1345 static struct switch_attr rtl8366s_globals[] = {
1346 {
1347 .type = SWITCH_TYPE_INT,
1348 .name = "enable_vlan",
1349 .description = "Enable VLAN mode",
1350 .set = rtl8366s_sw_set_vlan_enable,
1351 .get = rtl8366s_sw_get_vlan_enable,
1352 .max = 1,
1353 .ofs = 1
1354 }, {
1355 .type = SWITCH_TYPE_INT,
1356 .name = "enable_vlan4k",
1357 .description = "Enable VLAN 4K mode",
1358 .set = rtl8366s_sw_set_vlan_enable,
1359 .get = rtl8366s_sw_get_vlan_enable,
1360 .max = 1,
1361 .ofs = 2
1362 }, {
1363 .type = SWITCH_TYPE_INT,
1364 .name = "reset_mibs",
1365 .description = "Reset all MIB counters",
1366 .set = rtl8366s_sw_reset_mibs,
1367 .get = NULL,
1368 .max = 1
1369 }, {
1370 .type = SWITCH_TYPE_INT,
1371 .name = "blinkrate",
1372 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1373 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1374 .set = rtl8366s_sw_set_blinkrate,
1375 .get = rtl8366s_sw_get_blinkrate,
1376 .max = 5
1377 },
1378 };
1379
1380 static struct switch_attr rtl8366s_port[] = {
1381 {
1382 .type = SWITCH_TYPE_STRING,
1383 .name = "link",
1384 .description = "Get port link information",
1385 .max = 1,
1386 .set = NULL,
1387 .get = rtl8366s_sw_get_port_link,
1388 }, {
1389 .type = SWITCH_TYPE_INT,
1390 .name = "reset_mib",
1391 .description = "Reset single port MIB counters",
1392 .max = 1,
1393 .set = rtl8366s_sw_reset_port_mibs,
1394 .get = NULL,
1395 }, {
1396 .type = SWITCH_TYPE_STRING,
1397 .name = "mib",
1398 .description = "Get MIB counters for port",
1399 .max = 33,
1400 .set = NULL,
1401 .get = rtl8366s_sw_get_port_mib,
1402 }, {
1403 .type = SWITCH_TYPE_INT,
1404 .name = "led",
1405 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1406 .max = 15,
1407 .set = rtl8366s_sw_set_port_led,
1408 .get = rtl8366s_sw_get_port_led,
1409 },
1410 };
1411
1412 static struct switch_attr rtl8366s_vlan[] = {
1413 {
1414 .type = SWITCH_TYPE_STRING,
1415 .name = "info",
1416 .description = "Get vlan information",
1417 .max = 1,
1418 .set = NULL,
1419 .get = rtl8366s_sw_get_vlan_info,
1420 },
1421 };
1422
1423 /* template */
1424 static struct switch_dev rtl8366_switch_dev = {
1425 .name = "RTL8366S",
1426 .cpu_port = RTL8366_PORT_NUM_CPU,
1427 .ports = RTL8366_NUM_PORTS,
1428 .vlans = RTL8366_NUM_VLANS,
1429 .attr_global = {
1430 .attr = rtl8366s_globals,
1431 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1432 },
1433 .attr_port = {
1434 .attr = rtl8366s_port,
1435 .n_attr = ARRAY_SIZE(rtl8366s_port),
1436 },
1437 .attr_vlan = {
1438 .attr = rtl8366s_vlan,
1439 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1440 },
1441
1442 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1443 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1444 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1445 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1446 .reset_switch = rtl8366s_sw_reset_switch,
1447 };
1448
1449 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1450 {
1451 struct switch_dev *dev = &rtl->dev;
1452 int err;
1453
1454 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1455 dev->priv = rtl;
1456 dev->devname = dev_name(rtl->parent);
1457
1458 err = register_switch(dev, NULL);
1459 if (err)
1460 dev_err(rtl->parent, "switch registration failed\n");
1461
1462 return err;
1463 }
1464
1465 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1466 {
1467 unregister_switch(&rtl->dev);
1468 }
1469
1470 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1471 {
1472 struct rtl8366_smi *smi = bus->priv;
1473 u32 val = 0;
1474 int err;
1475
1476 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1477 if (err)
1478 return 0xffff;
1479
1480 return val;
1481 }
1482
1483 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1484 {
1485 struct rtl8366_smi *smi = bus->priv;
1486 u32 t;
1487 int err;
1488
1489 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1490 /* flush write */
1491 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1492
1493 return err;
1494 }
1495
1496 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1497 {
1498 return (bus->read == rtl8366s_mii_read &&
1499 bus->write == rtl8366s_mii_write);
1500 }
1501
1502 static int rtl8366s_setup(struct rtl8366s *rtl)
1503 {
1504 int ret;
1505
1506 ret = rtl8366s_reset_chip(rtl);
1507 if (ret)
1508 return ret;
1509
1510 rtl8366s_debugfs_init(rtl);
1511 return 0;
1512 }
1513
1514 static int rtl8366s_detect(struct rtl8366_smi *smi)
1515 {
1516 u32 chip_id = 0;
1517 u32 chip_ver = 0;
1518 int ret;
1519
1520 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1521 if (ret) {
1522 dev_err(smi->parent, "unable to read chip id\n");
1523 return ret;
1524 }
1525
1526 switch (chip_id) {
1527 case RTL8366S_CHIP_ID_8366:
1528 break;
1529 default:
1530 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1531 return -ENODEV;
1532 }
1533
1534 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1535 &chip_ver);
1536 if (ret) {
1537 dev_err(smi->parent, "unable to read chip version\n");
1538 return ret;
1539 }
1540
1541 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1542 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1543
1544 return 0;
1545 }
1546
1547 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1548 .detect = rtl8366s_detect,
1549 .mii_read = rtl8366s_mii_read,
1550 .mii_write = rtl8366s_mii_write,
1551 };
1552
1553 static int __init rtl8366s_probe(struct platform_device *pdev)
1554 {
1555 static int rtl8366_smi_version_printed;
1556 struct rtl8366s_platform_data *pdata;
1557 struct rtl8366s *rtl;
1558 struct rtl8366_smi *smi;
1559 int err;
1560
1561 if (!rtl8366_smi_version_printed++)
1562 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1563 " version " RTL8366S_DRIVER_VER"\n");
1564
1565 pdata = pdev->dev.platform_data;
1566 if (!pdata) {
1567 dev_err(&pdev->dev, "no platform data specified\n");
1568 err = -EINVAL;
1569 goto err_out;
1570 }
1571
1572 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1573 if (!rtl) {
1574 dev_err(&pdev->dev, "no memory for private data\n");
1575 err = -ENOMEM;
1576 goto err_out;
1577 }
1578
1579 rtl->parent = &pdev->dev;
1580
1581 smi = &rtl->smi;
1582 smi->parent = &pdev->dev;
1583 smi->gpio_sda = pdata->gpio_sda;
1584 smi->gpio_sck = pdata->gpio_sck;
1585 smi->ops = &rtl8366s_smi_ops;
1586
1587 err = rtl8366_smi_init(smi);
1588 if (err)
1589 goto err_free_rtl;
1590
1591 platform_set_drvdata(pdev, rtl);
1592
1593 err = rtl8366s_setup(rtl);
1594 if (err)
1595 goto err_clear_drvdata;
1596
1597 err = rtl8366s_switch_init(rtl);
1598 if (err)
1599 goto err_clear_drvdata;
1600
1601 return 0;
1602
1603 err_clear_drvdata:
1604 platform_set_drvdata(pdev, NULL);
1605 rtl8366_smi_cleanup(smi);
1606 err_free_rtl:
1607 kfree(rtl);
1608 err_out:
1609 return err;
1610 }
1611
1612 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1613 {
1614 if (!rtl8366s_mii_bus_match(phydev->bus))
1615 return -EINVAL;
1616
1617 return 0;
1618 }
1619
1620 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1621 {
1622 return 0;
1623 }
1624
1625 static struct phy_driver rtl8366s_phy_driver = {
1626 .phy_id = 0x001cc960,
1627 .name = "Realtek RTL8366S",
1628 .phy_id_mask = 0x1ffffff0,
1629 .features = PHY_GBIT_FEATURES,
1630 .config_aneg = rtl8366s_phy_config_aneg,
1631 .config_init = rtl8366s_phy_config_init,
1632 .read_status = genphy_read_status,
1633 .driver = {
1634 .owner = THIS_MODULE,
1635 },
1636 };
1637
1638 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1639 {
1640 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1641
1642 if (rtl) {
1643 rtl8366s_switch_cleanup(rtl);
1644 rtl8366s_debugfs_remove(rtl);
1645 platform_set_drvdata(pdev, NULL);
1646 rtl8366_smi_cleanup(&rtl->smi);
1647 kfree(rtl);
1648 }
1649
1650 return 0;
1651 }
1652
1653 static struct platform_driver rtl8366s_driver = {
1654 .driver = {
1655 .name = RTL8366S_DRIVER_NAME,
1656 .owner = THIS_MODULE,
1657 },
1658 .probe = rtl8366s_probe,
1659 .remove = __devexit_p(rtl8366s_remove),
1660 };
1661
1662 static int __init rtl8366s_module_init(void)
1663 {
1664 int ret;
1665 ret = platform_driver_register(&rtl8366s_driver);
1666 if (ret)
1667 return ret;
1668
1669 ret = phy_driver_register(&rtl8366s_phy_driver);
1670 if (ret)
1671 goto err_platform_unregister;
1672
1673 return 0;
1674
1675 err_platform_unregister:
1676 platform_driver_unregister(&rtl8366s_driver);
1677 return ret;
1678 }
1679 module_init(rtl8366s_module_init);
1680
1681 static void __exit rtl8366s_module_exit(void)
1682 {
1683 phy_driver_unregister(&rtl8366s_phy_driver);
1684 platform_driver_unregister(&rtl8366s_driver);
1685 }
1686 module_exit(rtl8366s_module_exit);
1687
1688 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1689 MODULE_VERSION(RTL8366S_DRIVER_VER);
1690 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1691 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1692 MODULE_LICENSE("GPL v2");
1693 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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